[U-Boot] [PATCH 1/3] OMAP3: Change some USB related MUX settings to values used by the kernel.

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[U-Boot] [PATCH 1/3] OMAP3: Change some USB related MUX settings to values used by the kernel.

Alexander Holler
Signed-off-by: Alexander Holler <[hidden email]>
---
 board/ti/beagle/beagle.h |   27 ++++++++++++++-------------
 1 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h
index b22b653..abb69e7 100644
--- a/board/ti/beagle/beagle.h
+++ b/board/ti/beagle/beagle.h
@@ -273,18 +273,18 @@ const omap3_sysinfo sysinfo = {
  MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN  | M0)) /*McSPI1_CS1*/\
  MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
  /* USB EHCI (port 2) */\
- MUX_VAL(CP(MCSPI1_CS3), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA2*/\
- MUX_VAL(CP(MCSPI2_CLK), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA7*/\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA4*/\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA5*/\
- MUX_VAL(CP(MCSPI2_CS0), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA6*/\
- MUX_VAL(CP(MCSPI2_CS1), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA3*/\
- MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
- MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
- MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTU | DIS | M3)) /*HSUSB2_DIR*/\
- MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTU | DIS | M3)) /*HSUSB2_NXT*/\
- MUX_VAL(CP(ETK_D14_ES2), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
- MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA3*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN  | PTD | EN  | M3)) /*HSUSB2_DIR*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN  | PTD | EN  | M3)) /*HSUSB2_NXT*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA0*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN  | PTD | EN  | M3)) /*HSUSB2_DATA1*/\
  /*Control and debug */\
  MUX_VAL(CP(SYS_32K), (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
  MUX_VAL(CP(SYS_CLKREQ), (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
@@ -383,7 +383,8 @@ const omap3_sysinfo sysinfo = {
  MUX_VAL(CP(MCBSP3_CLKX), (IEN  | PTD | DIS | M4)) /*GPIO_141*/\
  MUX_VAL(CP(UART2_CTS), (IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
  MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IDIS | PTU | EN  | M4)) /*GPIO_147*/
 
 #define MUX_BEAGLE_XM() \
  MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | EN  | M4)) /*GPIO_56*/\
--
1.7.3.4

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[U-Boot] [PATCH 2/3] OMAP3: Add support for DPLL5 (usbhost)

Alexander Holler
Signed-off-by: Alexander Holler <[hidden email]>
---
 arch/arm/cpu/armv7/omap3/clock.c               |   20 ++++++++++++++++++
 arch/arm/cpu/armv7/omap3/lowlevel_init.S       |   22 ++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/clocks.h       |    1 +
 arch/arm/include/asm/arch-omap3/clocks_omap3.h |   26 ++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/cpu.h          |   21 ++++++++++++++----
 5 files changed, 85 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 2238c52..3d38d08 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -278,6 +278,25 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
  wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
 }
 
+static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* PER2 DPLL (DPLL5) */
+ sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
+ wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
+ sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
+ sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
+ sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
+ sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);   /* FREQSEL */
+ sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK);   /* lock mode */
+ wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
+}
+
 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
 {
  struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -587,6 +606,7 @@ void prcm_init(void)
 
  dpll3_init_34xx(sil_index, clk_index);
  dpll4_init_34xx(sil_index, clk_index);
+ dpll5_init_34xx(sil_index, clk_index);
  iva_init_34xx(sil_index, clk_index);
  mpu_init_34xx(sil_index, clk_index);
 
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 109481e..1458072 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -360,6 +360,28 @@ get_per_dpll_param:
  adr r0, per_dpll_param
  mov pc, lr
 
+/* PER2 DPLL values */
+per2_dpll_param:
+/* 12MHz */
+.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
+
+/* 13MHz */
+.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
+
+/* 19.2MHz */
+.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
+
+/* 26MHz */
+.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
+
+/* 38.4MHz */
+.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
+
+.globl get_per2_dpll_param
+get_per2_dpll_param:
+ adr r0, per2_dpll_param
+ mov pc, lr
+
 /*
  * Tables for 36XX/37XX devices
  *
diff --git a/arch/arm/include/asm/arch-omap3/clocks.h b/arch/arm/include/asm/arch-omap3/clocks.h
index 40f80ba..bed0002 100644
--- a/arch/arm/include/asm/arch-omap3/clocks.h
+++ b/arch/arm/include/asm/arch-omap3/clocks.h
@@ -68,6 +68,7 @@ extern dpll_param *get_mpu_dpll_param(void);
 extern dpll_param *get_iva_dpll_param(void);
 extern dpll_param *get_core_dpll_param(void);
 extern dpll_param *get_per_dpll_param(void);
+extern dpll_param *get_per2_dpll_param(void);
 
 extern dpll_param *get_36x_mpu_dpll_param(void);
 extern dpll_param *get_36x_iva_dpll_param(void);
diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
index 30ef690..ef600dd 100644
--- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
+++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
@@ -282,6 +282,32 @@
 #define PER_FSEL_38P4 0x07
 #define PER_M2_38P4 0x09
 
+/* PER2 DPLL */
+#define PER2_M_12 0x78
+#define PER2_N_12 0x0B
+#define PER2_FSEL_12 0x03
+#define PER2_M2_12 0x01
+
+#define PER2_M_13 0x78
+#define PER2_N_13 0x0C
+#define PER2_FSEL_13 0x03
+#define PER2_M2_13 0x01
+
+#define PER2_M_19P2 0x2EE
+#define PER2_N_19P2 0x0B
+#define PER2_FSEL_19P2 0x06
+#define PER2_M2_19P2 0x0A
+
+#define PER2_M_26 0x78
+#define PER2_N_26 0x0C
+#define PER2_FSEL_26 0x03
+#define PER2_M2_26 0x01
+
+#define PER2_M_38P4 0x2EE
+#define PER2_N_38P4 0x0B
+#define PER2_FSEL_38P4 0x06
+#define PER2_M2_38P4 0x0A
+
 /* 36XX PER DPLL */
 
 #define PER_36XX_M_12 0x1B0
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 962d6d4..e944de7 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -347,10 +347,13 @@ struct prcm {
  u32 clksel2_pll_mpu; /* 0x944 */
  u8 res6[0xb8];
  u32 fclken1_core; /* 0xa00 */
- u8 res7[0xc];
+ u32 res_fclken2_core;
+ u32 fclken3_core; /* 0xa08 */
+ u8 res7[0x4];
  u32 iclken1_core; /* 0xa10 */
  u32 iclken2_core; /* 0xa14 */
- u8 res8[0x28];
+ u32 iclken3_core; /* 0xa18 */
+ u8 res8[0x24];
  u32 clksel_core; /* 0xa40 */
  u8 res9[0xbc];
  u32 fclken_gfx; /* 0xb00 */
@@ -368,13 +371,17 @@ struct prcm {
  u32 clksel_wkup; /* 0xc40 */
  u8 res16[0xbc];
  u32 clken_pll; /* 0xd00 */
- u8 res17[0x1c];
+ u32 clken2_pll;        /* 0xd04 */
+ u8 res17[0x18];
  u32 idlest_ckgen; /* 0xd20 */
- u8 res18[0x1c];
+ u32 idlest2_ckgen; /* 0xd24 */
+ u8 res18[0x18];
  u32 clksel1_pll; /* 0xd40 */
  u32 clksel2_pll; /* 0xd44 */
  u32 clksel3_pll; /* 0xd48 */
- u8 res19[0xb4];
+ u32 clksel4_pll; /* 0xd4c */
+ u32 clksel5_pll; /* 0xd50 */
+ u8 res19[0xac];
  u32 fclken_dss; /* 0xe00 */
  u8 res20[0xc];
  u32 iclken_dss; /* 0xe10 */
@@ -394,6 +401,10 @@ struct prcm {
  u32 clksel_per; /* 0x1040 */
  u8 res28[0xfc];
  u32 clksel1_emu; /* 0x1140 */
+ u8 res29[0x2bc];
+ u32 fclken_usbhost; /* 0x1400 */
+ u8 res30[0xc];
+ u32 iclken_usbhost; /* 0x1410 */
 };
 #else /* __ASSEMBLY__ */
 #define CM_CLKSEL_CORE 0x48004a40
--
1.7.3.4

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[U-Boot] [PATCH 3/3] omap3_beagle: enable EHCI and USB storage.

Alexander Holler
In reply to this post by Alexander Holler
The reset sequence/configuration for ehci is highly board specific,
so this will be done in the source for the board, instead of
introducing several CONFIG_* which would be needed to make those
few lines in beagle.c usable across different OMAP boards.

Signed-off-by: Alexander Holler <[hidden email]>
---
 arch/arm/include/asm/arch-omap3/ehci_omap3.h |   58 ++++++++++++++
 board/ti/beagle/beagle.c                     |  106 ++++++++++++++++++++++++++
 include/configs/omap3_beagle.h               |    6 ++
 3 files changed, 170 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-omap3/ehci_omap3.h

diff --git a/arch/arm/include/asm/arch-omap3/ehci_omap3.h b/arch/arm/include/asm/arch-omap3/ehci_omap3.h
new file mode 100644
index 0000000..cd01f50
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/ehci_omap3.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2011
+ * Alexander Holler <[hidden email]>
+ *
+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37
+ *
+ * See there for additional Copyrights.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#ifndef _EHCI_OMAP3_H_
+#define _EHCI_OMAP3_H_
+
+/* USB/EHCI registers */
+#define OMAP3_USBTLL_BASE 0x48062000UL
+#define OMAP3_UHH_BASE 0x48064000UL
+#define OMAP3_EHCI_BASE 0x48064800UL
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG (0x10)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
+
+#define OMAP_USBTLL_SYSSTATUS (0x14)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
+
+/* UHH Register Set */
+#define OMAP_UHH_SYSCONFIG (0x10)
+#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
+#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
+#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
+#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
+#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
+
+#define OMAP_UHH_HOSTCONFIG (0x40)
+#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
+#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
+#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
+
+#endif /* _EHCI_OMAP3_H_ */
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index c066d6e..03242c1 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -37,8 +37,19 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/gpio.h>
 #include <asm/mach-types.h>
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/clocks_omap3.h>
+#include <asm/arch/ehci_omap3.h>
+/* from drivers/usb/host/ehci-core.h */
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+#endif
 #include "beagle.h"
 
+#define pr_debug(fmt, args...) debug(fmt, ##args)
+
 #define TWL4030_I2C_BUS 0
 #define EXPANSION_EEPROM_I2C_BUS 1
 #define EXPANSION_EEPROM_I2C_ADDRESS 0x50
@@ -273,3 +284,98 @@ int board_mmc_init(bd_t *bis)
  return 0;
 }
 #endif
+
+#ifdef CONFIG_USB_EHCI
+
+#define GPIO_PHY_RESET 147
+
+/* Reset is needed otherwise the kernel-driver will throw an error. */
+int ehci_hcd_stop(void)
+{
+ pr_debug("Resetting OMAP3 EHCI\n");
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+ writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
+ return 0;
+}
+
+/* Call usb_stop() before starting the kernel */
+void show_boot_progress(int val)
+{
+ if(val == 15)
+ usb_stop();
+}
+
+/*
+ * Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
+ * See there for additional Copyrights.
+ */
+int ehci_hcd_init(void)
+{
+ pr_debug("Initializing OMAP3 ECHI\n");
+
+ /* Put the PHY in RESET */
+ omap_request_gpio(GPIO_PHY_RESET);
+ omap_set_gpio_direction(GPIO_PHY_RESET, 0);
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 0);
+
+ /* Hold the PHY in RESET for enough time till DIR is high */
+ /* Refer: ISSUE1 */
+ udelay(10);
+
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
+ sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
+ /*
+ * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
+ * and USBHOST_120M_FCLK (USBHOST_FCLK2)
+ */
+ sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
+ /* Enable USBTTL_ICLK */
+ sr32(&prcm_base->iclken3_core, 2, 1, 1);
+ /* Enable USBTTL_FCLK */
+ sr32(&prcm_base->fclken3_core, 2, 1, 1);
+ pr_debug("USB clocks enabled\n");
+
+ /* perform TLL soft reset, and wait until reset is complete */
+ writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+ /* Wait for TLL reset to complete */
+ while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
+ & OMAP_USBTLL_SYSSTATUS_RESETDONE));
+ pr_debug("TLL reset done\n");
+
+ writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
+ OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
+ OMAP_USBTLL_SYSCONFIG_CACTIVITY,
+ OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
+
+ /* Put UHH in NoIdle/NoStandby mode */
+ writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
+ | OMAP_UHH_SYSCONFIG_SIDLEMODE
+ | OMAP_UHH_SYSCONFIG_CACTIVITY
+ | OMAP_UHH_SYSCONFIG_MIDLEMODE,
+ OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
+
+ /* setup burst configurations */
+ writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
+ | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
+ OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
+
+ /*
+ * Refer ISSUE1:
+ * Hold the PHY in RESET for enough time till
+ * PHY is settled and ready
+ */
+ udelay(10);
+ omap_set_gpio_dataout(GPIO_PHY_RESET, 1);
+
+ hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
+ hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
+
+ pr_debug("OMAP3 EHCI init done\n");
+ return 0;
+}
+
+#endif /* CONFIG_USB_EHCI */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 5cfa4cb..ba34e8a 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -121,6 +121,11 @@
 #define CONFIG_USB_TTY 1
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
 
+/* USB EHCI */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
 /* commands to include */
 #include <config_cmd_default.h>
 
@@ -137,6 +142,7 @@
 
 #define CONFIG_CMD_I2C /* I2C serial bus support */
 #define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_USB_STORAGE /* USB storage support */
 #define CONFIG_CMD_NAND /* NAND support */
 
 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
--
1.7.3.4

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