[PATCHv6 00/18] powerpc: convert p1010, p1020 and p2020 RDB boards to DM_ETH

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[PATCHv6 00/18] powerpc: convert p1010, p1020 and p2020 RDB boards to DM_ETH

Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH.

V5:
Merged the following thread:
https://patchwork.ozlabs.org/project/uboot/list/?series=174343&archive=both&state=*

Hou Zhiqiang (16):
  net: fsl_mdio: Change to use virtual address
  net: fsl_mdio: Correct the MII management register block address
  net: tsec: convert to use DM_MDIO when DM_ETH enabled
  net: tsec: Add fixed-link PHY support
  net: tsec: Add the compatible string "gianfar" support
  powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled
  fsl: p1_p2_rdb: Move vsc7835 firmware uploading to
    board_early_init_r()
  configs: p1_p2_rdb: Add the default address of vsc7385 firmware
  dts: powerpc: p1020rdb: Add eTSEC DT nodes
  powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled
  configs: P1020RDB: Enable DM_ETH config
  dts: powerpc: p1010rdb: Add eTSEC DT nodes
  powerpc: p1010rdb: Compile legacy ethernet init function when no
    DM_ETH
  configs: P1010RDB: Enable DM_ETH config
  dts: powerpc: p2020rdb: Add eTSEC DT nodes
  configs: P2020RDB: Enable DM_ETH config

Vladimir Oltean (2):
  phy: make phy_connect_fixed work with a null mdio bus
  configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN

 arch/powerpc/cpu/mpc8xxx/cpu.c                |  2 +
 arch/powerpc/dts/p1010rdb-pa.dts              |  1 +
 arch/powerpc/dts/p1010rdb-pa_36b.dts          |  1 +
 arch/powerpc/dts/p1010rdb.dtsi                | 50 +++++++++++++++
 arch/powerpc/dts/p1010si-post.dtsi            | 25 ++++++++
 arch/powerpc/dts/p1020-post.dtsi              | 20 +++++-
 arch/powerpc/dts/p1020rdb-pc.dts              |  1 +
 arch/powerpc/dts/p1020rdb-pc.dtsi             | 55 ++++++++++++++++
 arch/powerpc/dts/p1020rdb-pc_36b.dts          |  1 +
 arch/powerpc/dts/p1020rdb-pd.dts              | 45 ++++++++++++++
 arch/powerpc/dts/p2020-post.dtsi              |  8 ++-
 arch/powerpc/dts/p2020rdb-pc.dts              |  1 +
 arch/powerpc/dts/p2020rdb-pc.dtsi             | 50 +++++++++++++++
 arch/powerpc/dts/p2020rdb-pc_36b.dts          |  1 +
 arch/powerpc/dts/pq3-etsec1-0.dtsi            | 28 +++++++++
 arch/powerpc/dts/pq3-etsec1-1.dtsi            | 28 +++++++++
 arch/powerpc/dts/pq3-etsec1-2.dtsi            | 28 +++++++++
 arch/powerpc/dts/pq3-etsec1-3.dtsi            | 28 +++++++++
 arch/powerpc/dts/pq3-etsec2-0.dtsi            | 35 +++++++++++
 arch/powerpc/dts/pq3-etsec2-1.dtsi            | 35 +++++++++++
 arch/powerpc/dts/pq3-etsec2-2.dtsi            | 35 +++++++++++
 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi       | 16 +++++
 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi       | 16 +++++
 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi       | 16 +++++
 board/freescale/p1010rdb/p1010rdb.c           |  2 +
 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c   | 37 ++++++-----
 configs/P1010RDB-PA_36BIT_NAND_defconfig      |  2 +
 configs/P1010RDB-PA_36BIT_NOR_defconfig       |  2 +
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig    |  2 +
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig  |  2 +
 configs/P1010RDB-PA_NAND_defconfig            |  2 +
 configs/P1010RDB-PA_NOR_defconfig             |  2 +
 configs/P1010RDB-PA_SDCARD_defconfig          |  2 +
 configs/P1010RDB-PA_SPIFLASH_defconfig        |  2 +
 configs/P1010RDB-PB_36BIT_NAND_defconfig      |  2 +
 configs/P1010RDB-PB_36BIT_NOR_defconfig       |  2 +
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig    |  2 +
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig  |  2 +
 configs/P1010RDB-PB_NAND_defconfig            |  2 +
 configs/P1010RDB-PB_NOR_defconfig             |  2 +
 configs/P1010RDB-PB_SDCARD_defconfig          |  2 +
 configs/P1010RDB-PB_SPIFLASH_defconfig        |  2 +
 configs/P1020RDB-PC_36BIT_NAND_defconfig      |  3 +
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig    |  3 +
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig  |  3 +
 configs/P1020RDB-PC_36BIT_defconfig           |  3 +
 configs/P1020RDB-PC_NAND_defconfig            |  3 +
 configs/P1020RDB-PC_SDCARD_defconfig          |  3 +
 configs/P1020RDB-PC_SPIFLASH_defconfig        |  3 +
 configs/P1020RDB-PC_defconfig                 |  3 +
 configs/P1020RDB-PD_NAND_defconfig            |  3 +
 configs/P1020RDB-PD_SDCARD_defconfig          |  3 +
 configs/P1020RDB-PD_SPIFLASH_defconfig        |  3 +
 configs/P1020RDB-PD_defconfig                 |  3 +
 configs/P2020RDB-PC_36BIT_NAND_defconfig      |  3 +
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig    |  3 +
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig  |  3 +
 configs/P2020RDB-PC_36BIT_defconfig           |  3 +
 configs/P2020RDB-PC_NAND_defconfig            |  3 +
 configs/P2020RDB-PC_SDCARD_defconfig          |  3 +
 configs/P2020RDB-PC_SPIFLASH_defconfig        |  3 +
 configs/P2020RDB-PC_defconfig                 |  3 +
 configs/ls1021atsn_qspi_defconfig             |  1 +
 configs/ls1021atsn_sdcard_defconfig           |  1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig  |  1 +
 configs/ls1021atwr_nor_defconfig              |  1 +
 configs/ls1021atwr_nor_lpuart_defconfig       |  1 +
 configs/ls1021atwr_qspi_defconfig             |  1 +
 ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig |  1 +
 configs/ls1021atwr_sdcard_ifc_defconfig       |  1 +
 configs/ls1021atwr_sdcard_qspi_defconfig      |  1 +
 doc/device-tree-bindings/net/fsl-tsec-phy.txt |  2 +-
 drivers/net/fsl_mdio.c                        | 28 +++++++--
 drivers/net/phy/phy.c                         |  4 +-
 drivers/net/tsec.c                            | 62 ++++++++-----------
 include/configs/p1_p2_rdb_pc.h                |  2 +
 include/fsl_mdio.h                            |  4 ++
 include/tsec.h                                |  4 ++
 78 files changed, 707 insertions(+), 65 deletions(-)
 create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi
 create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi

--
2.17.1

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[PATCHv6 01/18] phy: make phy_connect_fixed work with a null mdio bus

Zhiqiang Hou-2
From: Vladimir Oltean <[hidden email]>

It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.

Signed-off-by: Vladimir Oltean <[hidden email]>
Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 drivers/net/phy/phy.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 67789897c2..9587e6b9fa 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -664,7 +664,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
  dev = malloc(sizeof(*dev));
  if (!dev) {
  printf("Failed to allocate PHY device for %s:%d\n",
-       bus->name, addr);
+       bus ? bus->name : "(null bus)", addr);
  return NULL;
  }
 
@@ -692,7 +692,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
  return NULL;
  }
 
- if (addr >= 0 && addr < PHY_MAX_ADDR)
+ if (addr >= 0 && addr < PHY_MAX_ADDR && phy_id != PHY_FIXED_ID)
  bus->phymap[addr] = dev;
 
  return dev;
--
2.17.1

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[PATCHv6 02/18] net: fsl_mdio: Change to use virtual address

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

Use virtual address to access the MII block registers instead
of physical address.

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 drivers/net/fsl_mdio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index d2edd1751c..ae96ce4c7b 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -213,7 +213,7 @@ static int tsec_mdio_probe(struct udevice *dev)
  printf("dev_get_priv(dev %p) = NULL\n", dev);
  return -1;
  }
- priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
+ priv->regs = dev_remap_addr(dev);
  debug("%s priv %p @ regs %p, pdata %p\n", __func__,
       priv, priv->regs, pdata);
 
--
2.17.1

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[PATCHv6 03/18] net: fsl_mdio: Correct the MII management register block address

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.

Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 drivers/net/fsl_mdio.c | 28 ++++++++++++++++++++++------
 include/fsl_mdio.h     |  4 ++++
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index ae96ce4c7b..77f1a96a2e 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,6 +11,7 @@
 #include <fsl_mdio.h>
 #include <asm/io.h>
 #include <linux/errno.h>
+#include <tsec.h>
 
 #ifdef CONFIG_DM_MDIO
 struct tsec_mdio_priv {
@@ -190,17 +191,30 @@ static const struct mdio_ops tsec_mdio_ops = {
  .reset = tsec_mdio_reset,
 };
 
+static struct fsl_pq_mdio_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct fsl_pq_mdio_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
+static struct fsl_pq_mdio_data fman_data = {
+ .mdio_regs_off = 0x0,
+};
+
 static const struct udevice_id tsec_mdio_ids[] = {
- { .compatible = "fsl,gianfar-tbi" },
- { .compatible = "fsl,gianfar-mdio" },
- { .compatible = "fsl,etsec2-tbi" },
- { .compatible = "fsl,etsec2-mdio" },
- { .compatible = "fsl,fman-mdio" },
+ { .compatible = "fsl,gianfar-tbi", .data = (ulong)&gianfar_data },
+ { .compatible = "fsl,gianfar-mdio", .data = (ulong)&gianfar_data },
+ { .compatible = "fsl,etsec2-tbi", .data = (ulong)&etsec2_data },
+ { .compatible = "fsl,etsec2-mdio", .data = (ulong)&etsec2_data },
+ { .compatible = "fsl,fman-mdio", .data = (ulong)&fman_data },
  {}
 };
 
 static int tsec_mdio_probe(struct udevice *dev)
 {
+ struct fsl_pq_mdio_data *data;
  struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
  struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
  NULL;
@@ -213,7 +227,9 @@ static int tsec_mdio_probe(struct udevice *dev)
  printf("dev_get_priv(dev %p) = NULL\n", dev);
  return -1;
  }
- priv->regs = dev_remap_addr(dev);
+
+ data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev);
+ priv->regs = dev_remap_addr(dev) + data->mdio_regs_off;
  debug("%s priv %p @ regs %p, pdata %p\n", __func__,
       priv, priv->regs, pdata);
 
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 41cb73717b..b6c02cf342 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -55,6 +55,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
  int regnum);
 int memac_mdio_reset(struct mii_dev *bus);
 
+struct fsl_pq_mdio_data {
+ u32 mdio_regs_off;
+};
+
 struct fsl_pq_mdio_info {
  struct tsec_mii_mng __iomem *regs;
  char *name;
--
2.17.1

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[PATCHv6 04/18] net: tsec: convert to use DM_MDIO when DM_ETH enabled

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.

Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.

Signed-off-by: Vladimir Oltean <[hidden email]>
Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 drivers/net/tsec.c | 43 ++++++++++---------------------------------
 1 file changed, 10 insertions(+), 33 deletions(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 5d12e4b775..9d68c6f829 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -18,6 +18,7 @@
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
+#include <miiphy.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 
@@ -681,8 +682,12 @@ static int init_phy(struct tsec_private *priv)
  if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  tsec_configure_serdes(priv);
 
+#ifdef CONFIG_DM_ETH
+ phydev = dm_eth_phy_connect(priv->dev);
+#else
  phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
      priv->interface);
+#endif
  if (!phydev)
  return 0;
 
@@ -789,14 +794,17 @@ int tsec_standard_init(struct bd_info *bis)
  return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 }
 #else /* CONFIG_DM_ETH */
+
+#ifndef CONFIG_DM_MDIO
+#error "TSEC with DM_ETH also requires DM_MDIO"
+#endif
+
 int tsec_probe(struct udevice *dev)
 {
  struct eth_pdata *pdata = dev_get_platdata(dev);
  struct tsec_private *priv = dev_get_priv(dev);
- struct tsec_mii_mng __iomem *ext_phyregs_mii;
  struct ofnode_phandle_args phandle_args;
  u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
- struct fsl_pq_mdio_info mdio_info;
  const char *phy_mode;
  fdt_addr_t reg;
  ofnode parent;
@@ -805,31 +813,6 @@ int tsec_probe(struct udevice *dev)
  pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  priv->regs = dev_remap_addr(dev);
 
- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
-       &phandle_args)) {
- printf("phy-handle does not exist under tsec %s\n", dev->name);
- return -ENOENT;
- } else {
- int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
-
- priv->phyaddr = reg;
- }
-
- parent = ofnode_get_parent(phandle_args.node);
- if (!ofnode_valid(parent)) {
- printf("No parent node for PHY?\n");
- return -ENOENT;
- }
-
- reg = ofnode_get_addr_index(parent, 0);
- if (reg == FDT_ADDR_T_NONE) {
- printf("No 'reg' property of MII for external PHY\n");
- return -ENOENT;
- }
-
- ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
-      MAP_NOCACHE);
-
  ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
  &phandle_args);
  if (ret == 0) {
@@ -867,12 +850,6 @@ int tsec_probe(struct udevice *dev)
  if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  priv->flags |= TSEC_SGMII;
 
- mdio_info.regs = ext_phyregs_mii;
- mdio_info.name = (char *)dev->name;
- ret = fsl_pq_mdio_init(NULL, &mdio_info);
- if (ret)
- return ret;
-
  /* Reset the MAC */
  setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
--
2.17.1

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[PATCHv6 05/18] net: tsec: Add fixed-link PHY support

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.

Signed-off-by: Vladimir Oltean <[hidden email]>
Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 drivers/net/tsec.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9d68c6f829..1e04a89102 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -683,7 +683,10 @@ static int init_phy(struct tsec_private *priv)
  tsec_configure_serdes(priv);
 
 #ifdef CONFIG_DM_ETH
- phydev = dm_eth_phy_connect(priv->dev);
+ if (ofnode_valid(ofnode_find_subnode(priv->dev->node, "fixed-link")))
+ phydev = phy_connect(NULL, 0, priv->dev, priv->interface);
+ else
+ phydev = dm_eth_phy_connect(priv->dev);
 #else
  phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
      priv->interface);
--
2.17.1

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[PATCHv6 06/18] net: tsec: Add the compatible string "gianfar" support

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

Add compatible string "gianfar" support and update the
device-tree-bindings doc.

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 doc/device-tree-bindings/net/fsl-tsec-phy.txt |  2 +-
 drivers/net/tsec.c                            | 16 ++++++++++++++--
 include/tsec.h                                |  4 ++++
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
index 8e8574bc97..a44c5fd9d9 100644
--- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt
+++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt
@@ -2,7 +2,7 @@
 
 Properties:
 
-  - compatible : Should be "fsl,etsec2"
+  - compatible : Should be "fsl,etsec2" or "gianfar"
   - reg : Offset and length of the register set for the device
   - phy-handle : See ethernet.txt file in the same directory.
   - phy-connection-type : See ethernet.txt file in the same directory. This
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 1e04a89102..e59a107ea8 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -808,11 +808,14 @@ int tsec_probe(struct udevice *dev)
  struct tsec_private *priv = dev_get_priv(dev);
  struct ofnode_phandle_args phandle_args;
  u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
+ struct tsec_data *data;
  const char *phy_mode;
  fdt_addr_t reg;
  ofnode parent;
  int ret;
 
+ data = (struct tsec_data *)dev_get_driver_data(dev);
+
  pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  priv->regs = dev_remap_addr(dev);
 
@@ -833,7 +836,7 @@ int tsec_probe(struct udevice *dev)
  return -ENOENT;
  }
 
- priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
+ priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
   0, MAP_NOCACHE);
  }
 
@@ -885,8 +888,17 @@ static const struct eth_ops tsec_ops = {
  .mcast = tsec_mcast_addr,
 };
 
+static struct tsec_data etsec2_data = {
+ .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
+};
+
+static struct tsec_data gianfar_data = {
+ .mdio_regs_off = 0x0,
+};
+
 static const struct udevice_id tsec_ids[] = {
- { .compatible = "fsl,etsec2" },
+ { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
+ { .compatible = "gianfar", .data = (ulong)&gianfar_data },
  { }
 };
 
diff --git a/include/tsec.h b/include/tsec.h
index 43255e538f..5433cfd966 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -394,6 +394,10 @@ struct tsec {
 
 #define TX_BUF_CNT 2
 
+struct tsec_data {
+ u32 mdio_regs_off;
+};
+
 struct tsec_private {
  struct txbd8 __iomem txbd[TX_BUF_CNT];
  struct rxbd8 __iomem rxbd[PKTBUFSRX];
--
2.17.1

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[PATCHv6 07/18] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

The cpu_eth_init() is only used by the legacy ethernet driver framework.

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 2b24e755fa..67857c3760 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -347,6 +347,7 @@ int fixup_cpu(void)
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
  */
+#ifndef CONFIG_DM_ETH
 int cpu_eth_init(struct bd_info *bis)
 {
 #if defined(CONFIG_ETHER_ON_FCC)
@@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis)
 #endif
  return 0;
 }
+#endif
--
2.17.1

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[PATCHv6 08/18] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

Move vsc7835 firmware uploading to board_early_init_r(), so that
the switch also can work in DM eTSEC driver.

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++++++++++----------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 7c703b354f..d0562ba95a 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -316,6 +316,10 @@ int board_early_init_r(void)
 {
  const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  int flash_esel = find_tlb_idx((void *)flashbase, 1);
+#ifdef CONFIG_VSC7385_ENET
+ unsigned int vscfw_addr;
+ char *tmp;
+#endif
 
  /*
  * Remap Boot flash region to caching-inhibited
@@ -338,6 +342,20 @@ int board_early_init_r(void)
  set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
  0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
+
+#ifdef CONFIG_VSC7385_ENET
+ /* If a VSC7385 microcode image is present, then upload it. */
+ tmp = env_get("vscfw_addr");
+ if (tmp) {
+ vscfw_addr = simple_strtoul(tmp, NULL, 16);
+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+ if (vsc7385_upload_firmware((void *)vscfw_addr,
+    CONFIG_VSC7385_IMAGE_SIZE))
+ puts("Failure uploading VSC7385 microcode.\n");
+ } else {
+ puts("No address specified for VSC7385 microcode.\n");
+ }
+#endif
  return 0;
 }
 
@@ -348,10 +366,6 @@ int board_eth_init(struct bd_info *bis)
  ccsr_gur_t *gur __attribute__((unused)) =
  (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  int num = 0;
-#ifdef CONFIG_VSC7385_ENET
- char *tmp;
- unsigned int vscfw_addr;
-#endif
 
 #ifdef CONFIG_TSEC1
  SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -375,19 +389,6 @@ int board_eth_init(struct bd_info *bis)
  return 0;
  }
 
-#ifdef CONFIG_VSC7385_ENET
- /* If a VSC7385 microcode image is present, then upload it. */
- tmp = env_get("vscfw_addr");
- if (tmp) {
- vscfw_addr = simple_strtoul(tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
  mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  mdio_info.name = DEFAULT_MII_NAME;
 
--
2.17.1

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[PATCHv6 09/18] configs: p1_p2_rdb: Add the default address of vsc7385 firmware

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

Add the environment 'vscfw_addr' to assign a default address for
vsc7385 firmware uploading.

Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 include/configs/p1_p2_rdb_pc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 1b74177b2f..a159285c98 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -451,6 +451,7 @@
 
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
+#define __VSCFW_ADDR "vscfw_addr=ef000000"
 #define CONFIG_SYS_VSC7385_BASE 0xffb00000
 
 #ifdef CONFIG_PHYS_64BIT
@@ -809,6 +810,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset
 "ramdisk_size=120000\0" \
 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
+__stringify(__VSCFW_ADDR)"\0" \
 __stringify(__NOR_RST_CMD)"\0" \
 __stringify(__SPI_RST_CMD)"\0" \
 __stringify(__SD_RST_CMD)"\0" \
--
2.17.1

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[PATCHv6 10/18] dts: powerpc: p1020rdb: Add eTSEC DT nodes

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII switch VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 arch/powerpc/dts/p1020-post.dtsi        | 20 ++++++++-
 arch/powerpc/dts/p1020rdb-pc.dts        |  1 +
 arch/powerpc/dts/p1020rdb-pc.dtsi       | 55 +++++++++++++++++++++++++
 arch/powerpc/dts/p1020rdb-pc_36b.dts    |  1 +
 arch/powerpc/dts/p1020rdb-pd.dts        | 45 ++++++++++++++++++++
 arch/powerpc/dts/pq3-etsec2-0.dtsi      | 35 ++++++++++++++++
 arch/powerpc/dts/pq3-etsec2-1.dtsi      | 35 ++++++++++++++++
 arch/powerpc/dts/pq3-etsec2-2.dtsi      | 35 ++++++++++++++++
 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++++
 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++++
 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++++
 11 files changed, 273 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi

diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi
index 1dce8e86e9..c73539ad5c 100644
--- a/arch/powerpc/dts/p1020-post.dtsi
+++ b/arch/powerpc/dts/p1020-post.dtsi
@@ -44,10 +44,26 @@
  clock-frequency = <0>;
  };
 
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: enet0_grp2: ethernet@b0000 {
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: enet1_grp2: ethernet@b1000 {
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: enet2_grp2: ethernet@b2000 {
+ };
 };
 
+/include/ "pq3-etsec2-grp2-0.dtsi"
+/include/ "pq3-etsec2-grp2-1.dtsi"
+/include/ "pq3-etsec2-grp2-2.dtsi"
+
 /* PCIe controller base address 0x9000 */
 &pci1 {
  compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts
index 7ebaa619df..715330dc50 100644
--- a/arch/powerpc/dts/p1020rdb-pc.dts
+++ b/arch/powerpc/dts/p1020rdb-pc.dts
@@ -32,4 +32,5 @@
  };
 };
 
+/include/ "p1020rdb-pc.dtsi"
 /include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi
new file mode 100644
index 0000000000..6bf424fd3f
--- /dev/null
+++ b/arch/powerpc/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+
+ tbi0: tbi-phy@11 {
+ device_type = "tbi-phy";
+ reg = <0x11>;
+ };
+ };
+
+ mdio@25000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b0000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <&phy0>;
+ tbi-handle = <&tbi1>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts
index c0e5ef4cf4..7680b7c7e1 100644
--- a/arch/powerpc/dts/p1020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts
@@ -32,4 +32,5 @@
  };
 };
 
+/include/ "p1020rdb-pc.dtsi"
 /include/ "p1020-post.dtsi"
diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts
index 21174a09be..e0e8993dab 100644
--- a/arch/powerpc/dts/p1020rdb-pd.dts
+++ b/arch/powerpc/dts/p1020rdb-pd.dts
@@ -17,6 +17,51 @@
 
  soc: soc@ffe00000 {
  ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio@25000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26000 {
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b0000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <&phy0>;
+ tbi-handle = <&tbi1>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
  };
 
  pci1: pcie@ffe09000 {
diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi
new file mode 100644
index 0000000000..f9d3d04650
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x24000 0x1000 0xb0030 0x4>;
+};
+
+ethernet@b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0xb0000 0x1000>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb0000 0x1000>;
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi
new file mode 100644
index 0000000000..6c01481909
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x25000 0x1000 0xb1030 0x4>;
+};
+
+ethernet@b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0xb1000 0x1000>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1000 0x1000>;
+ interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi
new file mode 100644
index 0000000000..2a597c0db6
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+mdio@26000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x26000 0x1000 0xb1030 0x4>;
+};
+
+ethernet@b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ reg = <0xb2000 0x1000>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb2000 0x1000>;
+ interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
new file mode 100644
index 0000000000..16752a7c45
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet0_grp2 {
+ queue-group@b4000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb4000 0x1000>;
+ interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
new file mode 100644
index 0000000000..0464938424
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet1_grp2 {
+ queue-group@b5000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb5000 0x1000>;
+ interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
new file mode 100644
index 0000000000..fe8003c44a
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&enet2_grp2 {
+ queue-group@b6000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb6000 0x1000>;
+ interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
+ };
+};
--
2.17.1

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[PATCHv6 11/18] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index d0562ba95a..ba12bea92f 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -359,6 +359,7 @@ int board_early_init_r(void)
  return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
  struct fsl_pq_mdio_info mdio_info;
@@ -406,6 +407,7 @@ int board_eth_init(struct bd_info *bis)
 
  return pci_eth_init(bis);
 }
+#endif
 
 #if defined(CONFIG_QE) && \
  (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
--
2.17.1

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[PATCHv6 12/18] configs: P1020RDB: Enable DM_ETH config

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

Enable the DM_ETH and DM_MDIO config.

On P1020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.

Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 configs/P1020RDB-PC_36BIT_NAND_defconfig     | 3 +++
 configs/P1020RDB-PC_36BIT_SDCARD_defconfig   | 3 +++
 configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++
 configs/P1020RDB-PC_36BIT_defconfig          | 3 +++
 configs/P1020RDB-PC_NAND_defconfig           | 3 +++
 configs/P1020RDB-PC_SDCARD_defconfig         | 3 +++
 configs/P1020RDB-PC_SPIFLASH_defconfig       | 3 +++
 configs/P1020RDB-PC_defconfig                | 3 +++
 configs/P1020RDB-PD_NAND_defconfig           | 3 +++
 configs/P1020RDB-PD_SDCARD_defconfig         | 3 +++
 configs/P1020RDB-PD_SPIFLASH_defconfig       | 3 +++
 configs/P1020RDB-PD_defconfig                | 3 +++
 12 files changed, 36 insertions(+)

diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 6db4bd7d52..e69595102a 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index cacce4d5ec..974bcb15c7 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -68,8 +69,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index 3c9e491b08..f3e599869d 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -70,8 +71,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 5c68ea060a..445e796afb 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -46,6 +46,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -57,8 +58,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 9883204787..43fdbdffe4 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 22ba4f6501..282453a290 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -67,8 +68,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index 250b56d216..0a7fa606bf 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -58,6 +58,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -69,8 +70,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 329bd72e6b..cbe9c525dd 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -45,6 +45,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -56,8 +57,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 5d7f16aecb..8512e7a5ab 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -65,6 +65,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -76,8 +77,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 12d70e8ebe..80988c3d35 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -60,6 +60,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -71,8 +72,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 6da7157e1f..ea28116f4b 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index c39509e4ac..e7b97dbf4a 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -60,8 +61,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
--
2.17.1

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[PATCHv6 13/18] dts: powerpc: p1010rdb: Add eTSEC DT nodes

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII PHY AR8033
    eTSEC2: Connected to SGMII PHY AR8033
    eTSEC3: Connected to SGMII PHY AR8033

Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 arch/powerpc/dts/p1010rdb-pa.dts     |  1 +
 arch/powerpc/dts/p1010rdb-pa_36b.dts |  1 +
 arch/powerpc/dts/p1010rdb.dtsi       | 50 ++++++++++++++++++++++++++++
 arch/powerpc/dts/p1010si-post.dtsi   | 25 ++++++++++++++
 4 files changed, 77 insertions(+)

diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts
index c66c4923ac..360d254d91 100644
--- a/arch/powerpc/dts/p1010rdb-pa.dts
+++ b/arch/powerpc/dts/p1010rdb-pa.dts
@@ -15,3 +15,4 @@
 };
 
 /include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts
index b943de7cbb..062086a8c0 100644
--- a/arch/powerpc/dts/p1010rdb-pa_36b.dts
+++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts
@@ -15,3 +15,4 @@
 };
 
 /include/ "p1010si-post.dtsi"
+/include/ "p1010rdb.dtsi"
diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi
index 4f58ee2446..5964270878 100644
--- a/arch/powerpc/dts/p1010rdb.dtsi
+++ b/arch/powerpc/dts/p1010rdb.dtsi
@@ -5,6 +5,56 @@
  * Copyright 2020 NXP
  */
 &soc {
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ reg = <0x1>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0x0>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+
+ tbi-phy@3 {
+ device_type = "tbi-phy";
+ reg = <0x3>;
+ };
+ };
+
+ mdio@25000 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b0000 {
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ enet1: ethernet@b1000 {
+ phy-handle = <&phy1>;
+ tbi-handle = <&tbi0>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <&phy2>;
+ tbi-handle = <&tbi1>;
+ phy-connection-type = "sgmii";
+ };
+
  i2c@3000 {
  rtc@68 {
  compatible = "pericom,pt7c4338";
diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi
index 0289441381..f825208056 100644
--- a/arch/powerpc/dts/p1010si-post.dtsi
+++ b/arch/powerpc/dts/p1010si-post.dtsi
@@ -25,6 +25,31 @@
  };
 /include/ "pq3-i2c-0.dtsi"
 /include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec2-0.dtsi"
+ enet0: ethernet@b0000 {
+ queue-group@b0000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-1.dtsi"
+ enet1: ethernet@b1000 {
+ queue-group@b1000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+ };
+
+/include/ "pq3-etsec2-2.dtsi"
+ enet2: ethernet@b2000 {
+ queue-group@b2000 {
+ fsl,rx-bit-map = <0xff>;
+ fsl,tx-bit-map = <0xff>;
+ };
+
+ };
 };
 
 /* controller at 0x9000 */
--
2.17.1

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[PATCHv6 14/18] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 board/freescale/p1010rdb/p1010rdb.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index accf2f24e5..4c3a03e7cd 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -484,6 +484,7 @@ int checkboard(void)
  return 0;
 }
 
+#ifndef CONFIG_DM_ETH
 int board_eth_init(struct bd_info *bis)
 {
 #ifdef CONFIG_TSEC_ENET
@@ -524,6 +525,7 @@ int board_eth_init(struct bd_info *bis)
 
  return pci_eth_init(bis);
 }
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void fdt_del_flexcan(void *blob)
--
2.17.1

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[PATCHv6 15/18] configs: P1010RDB: Enable DM_ETH config

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

Enable the DM_ETH and DM_MDIO config.

Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 configs/P1010RDB-PA_36BIT_NAND_defconfig     | 2 ++
 configs/P1010RDB-PA_36BIT_NOR_defconfig      | 2 ++
 configs/P1010RDB-PA_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1010RDB-PA_NAND_defconfig           | 2 ++
 configs/P1010RDB-PA_NOR_defconfig            | 2 ++
 configs/P1010RDB-PA_SDCARD_defconfig         | 2 ++
 configs/P1010RDB-PA_SPIFLASH_defconfig       | 2 ++
 configs/P1010RDB-PB_36BIT_NAND_defconfig     | 2 ++
 configs/P1010RDB-PB_36BIT_NOR_defconfig      | 2 ++
 configs/P1010RDB-PB_36BIT_SDCARD_defconfig   | 2 ++
 configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++
 configs/P1010RDB-PB_NAND_defconfig           | 2 ++
 configs/P1010RDB-PB_NOR_defconfig            | 2 ++
 configs/P1010RDB-PB_SDCARD_defconfig         | 2 ++
 configs/P1010RDB-PB_SPIFLASH_defconfig       | 2 ++
 16 files changed, 32 insertions(+)

diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index b77a5d056c..8179992d93 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -73,8 +73,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 1ea7e3e641..fc011e3e6e 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -55,8 +55,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index 7b6b70f37b..5c5c24eb68 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 4bc60f148a..6a25c16d39 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -69,8 +69,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index ea9f905807..7464e123bb 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index f8093c17d7..4e928978d5 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index e0a75a1a82..36c7cf0c8e 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index c8212d7800..0855944b04 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index e109e9cf67..592c092031 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -73,8 +73,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 0e01e2b4e6..2d40a8e063 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -55,8 +55,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index c4f052be9f..7215cc177e 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -67,8 +67,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index 57d0687230..d07455ae9b 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -69,8 +69,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 37eddf6757..91817ab26a 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -72,8 +72,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 31e5157fa8..3d5972bf08 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -54,8 +54,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 2cf26ab626..28af0164fd 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -66,8 +66,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 5f578bd603..8eed913567 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -68,8 +68,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
--
2.17.1

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[PATCHv6 16/18] dts: powerpc: p2020rdb: Add eTSEC DT nodes

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
    eTSEC1: Connected to RGMII switch VSC7385
    eTSEC2: Connected to SGMII PHY VSC8221
    eTSEC3: Connected to SGMII PHY AR8021

Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No change.

 arch/powerpc/dts/p2020-post.dtsi     |  8 +++--
 arch/powerpc/dts/p2020rdb-pc.dts     |  1 +
 arch/powerpc/dts/p2020rdb-pc.dtsi    | 50 ++++++++++++++++++++++++++++
 arch/powerpc/dts/p2020rdb-pc_36b.dts |  1 +
 arch/powerpc/dts/pq3-etsec1-0.dtsi   | 28 ++++++++++++++++
 arch/powerpc/dts/pq3-etsec1-1.dtsi   | 28 ++++++++++++++++
 arch/powerpc/dts/pq3-etsec1-2.dtsi   | 28 ++++++++++++++++
 arch/powerpc/dts/pq3-etsec1-3.dtsi   | 28 ++++++++++++++++
 8 files changed, 170 insertions(+), 2 deletions(-)
 create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi
 create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi

diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index 4ed093dad4..11945295d1 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -38,8 +38,12 @@
  clock-frequency = <0>;
  };
 
- /include/ "pq3-i2c-0.dtsi"
- /include/ "pq3-i2c-1.dtsi"
+/include/ "pq3-i2c-0.dtsi"
+/include/ "pq3-i2c-1.dtsi"
+
+/include/ "pq3-etsec1-0.dtsi"
+/include/ "pq3-etsec1-1.dtsi"
+/include/ "pq3-etsec1-2.dtsi"
 };
 
 /* PCIe controller base address 0x8000 */
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 08befd4c59..f3f6be1080 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -37,4 +37,5 @@
  };
 };
 
+/include/ "p2020rdb-pc.dtsi"
 /include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi
new file mode 100644
index 0000000000..0d2acc746e
--- /dev/null
+++ b/arch/powerpc/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+&soc {
+ mdio@24520 {
+ phy0: ethernet-phy@0 {
+ interrupts = <3 1 0 0>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio@25520 {
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26520 {
+ status = "disabled";
+ };
+
+ enet0: ethernet@24000 {
+ phy-connection-type = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+ };
+
+ enet2: ethernet@26000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 04b2519e1a..6d983b7d71 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -37,4 +37,5 @@
  };
 };
 
+/include/ "p2020rdb-pc.dtsi"
 /include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi
new file mode 100644
index 0000000000..8800243f34
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
+};
+
+mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi
new file mode 100644
index 0000000000..2bc62d1a57
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
+};
+
+mdio@25520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x25520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi
new file mode 100644
index 0000000000..d45865fe03
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
+};
+
+mdio@26520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x26520 0x20>;
+};
diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi
new file mode 100644
index 0000000000..853a27359d
--- /dev/null
+++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ * Copyright 2020 NXP
+ */
+
+ethernet@27000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <3>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ ranges = <0x0 0x27000 0x1000>;
+ fsl,magic-packet;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
+};
+
+mdio@27520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x27520 0x20>;
+};
--
2.17.1

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[PATCHv6 17/18] configs: P2020RDB: Enable DM_ETH config

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Hou Zhiqiang <[hidden email]>

Enable the DM_ETH and DM_MDIO config.

On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.

Signed-off-by: Hou Zhiqiang <[hidden email]>
Reviewed-by: Vladimir Oltean <[hidden email]>
---
V6:
 - No change.

 configs/P2020RDB-PC_36BIT_NAND_defconfig     | 3 +++
 configs/P2020RDB-PC_36BIT_SDCARD_defconfig   | 3 +++
 configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 +++
 configs/P2020RDB-PC_36BIT_defconfig          | 3 +++
 configs/P2020RDB-PC_NAND_defconfig           | 3 +++
 configs/P2020RDB-PC_SDCARD_defconfig         | 3 +++
 configs/P2020RDB-PC_SPIFLASH_defconfig       | 3 +++
 configs/P2020RDB-PC_defconfig                | 3 +++
 8 files changed, 24 insertions(+)

diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 1e0bd202ea..ba4dd7fe1d 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -78,8 +79,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index df57340c7d..ef98374ea3 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -62,6 +62,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -73,8 +74,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 1b250214e7..e1ebb1f896 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -64,6 +64,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -75,8 +76,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index e5573cd22a..4a7d726e2f 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -51,6 +51,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -62,8 +63,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 6232b18aa9..5d8d531f69 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -66,6 +66,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -77,8 +78,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 4d3b872f72..61b1c1f8b4 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -61,6 +61,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -72,8 +73,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 7b97d9186a..f649c494e1 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -63,6 +63,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -74,8 +75,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 3a1f668716..b08adb7ffa 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -50,6 +50,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHY_FIXED=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_DAVICOM=y
@@ -61,8 +62,10 @@ CONFIG_PHY_SMSC=y
 CONFIG_PHY_VITESSE=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
+CONFIG_DM_ETH=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
+CONFIG_DM_MDIO=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
--
2.17.1

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[PATCHv6 18/18] configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN

Zhiqiang Hou-2
In reply to this post by Zhiqiang Hou-2
From: Vladimir Oltean <[hidden email]>

The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.

Signed-off-by: Vladimir Oltean <[hidden email]>
Signed-off-by: Hou Zhiqiang <[hidden email]>
---
V6:
 - No code change, just move it to the tail of this series.

 configs/ls1021atsn_qspi_defconfig                   | 1 +
 configs/ls1021atsn_sdcard_defconfig                 | 1 +
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        | 1 +
 configs/ls1021atwr_nor_defconfig                    | 1 +
 configs/ls1021atwr_nor_lpuart_defconfig             | 1 +
 configs/ls1021atwr_qspi_defconfig                   | 1 +
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
 configs/ls1021atwr_sdcard_ifc_defconfig             | 1 +
 configs/ls1021atwr_sdcard_qspi_defconfig            | 1 +
 9 files changed, 9 insertions(+)

diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 06a139be1a..43f9e511cc 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -44,6 +44,7 @@ CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 8046f6452f..49197eeed4 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -55,6 +55,7 @@ CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_MII=y
 CONFIG_TSEC_ENET=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 30511dd425..d62dcfa751 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 60622b1879..f49a882e0a 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -48,6 +48,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index fa0a118eb0..e75c7b43d2 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -50,6 +50,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 30c107924f..767c364b3e 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index 0911b9c151..5b3ac2a348 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -61,6 +61,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index eaf5b98f9f..5cc0b90aa7 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -63,6 +63,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 2743848ac9..e3e64f9790 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
--
2.17.1