[PATCH v4 00/59] dm: Add programatic generation of ACPI tables (part D)

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[PATCH v4 40/59] x86: fsp: Update the FSP API with the end-firmware method

Simon Glass-3
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.

Add a definition for this new method and update the comments a little.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

 arch/x86/include/asm/fsp/fsp_api.h | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h
index 4941e2d74f0..3a9b61903c0 100644
--- a/arch/x86/include/asm/fsp/fsp_api.h
+++ b/arch/x86/include/asm/fsp/fsp_api.h
@@ -10,9 +10,18 @@
 
 enum fsp_phase {
  /* Notification code for post PCI enuermation */
- INIT_PHASE_PCI = 0x20,
- /* Notification code before transferring control to the payload */
- INIT_PHASE_BOOT = 0x40
+ INIT_PHASE_PCI = 0x20,
+ /*
+ * Notification code before transferring control to the payload.
+ * This is issued at the end of init before starting main(), i.e.
+ * the command line / boot script.
+ */
+ INIT_PHASE_BOOT = 0x40,
+ /*
+ * Notification code before existing boot services. This is issued
+ * just before removing devices and booting the kernel.
+ */
+ INIT_PHASE_END_FIRMWARE = 0xf0,
 };
 
 struct fsp_notify_params {
--
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[PATCH v4 41/59] x86: cpu: Report address width from cpu_get_info()

Simon Glass-3
In reply to this post by Simon Glass-3
Add support for this new field in the common code used by most x86 CPU
drivers.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/cpu/i386/cpu.c         | 23 +++++++++++++++++++++++
 arch/x86/cpu/intel_common/cpu.c |  1 +
 arch/x86/cpu/x86_64/cpu.c       |  5 +++++
 arch/x86/include/asm/cpu.h      |  9 +++++++++
 4 files changed, 38 insertions(+)

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 8f342dd06e2..7517b756f43 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -34,6 +34,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CPUID_FEATURE_PAE BIT(6)
+#define CPUID_FEATURE_PSE36 BIT(17)
+#define CPUID_FEAURE_HTT BIT(28)
+
 /*
  * Constructor for a conventional segment GDT (or LDT) entry
  * This is a macro so it can be used in initialisers
@@ -388,6 +392,25 @@ static void setup_identity(void)
  }
 }
 
+static uint cpu_cpuid_extended_level(void)
+{
+ return cpuid_eax(0x80000000);
+}
+
+int cpu_phys_address_size(void)
+{
+ if (!has_cpuid())
+ return 32;
+
+ if (cpu_cpuid_extended_level() >= 0x80000008)
+ return cpuid_eax(0x80000008) & 0xff;
+
+ if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+ return 36;
+
+ return 32;
+}
+
 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
 static void setup_pci_ram_top(void)
 {
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index d8a3d60ae72..39aa0f63c65 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -127,6 +127,7 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk)
  info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000;
  info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
  1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+ info->address_width = cpu_phys_address_size();
 
  return 0;
 }
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 1b4d3971b04..90a766c3c57 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -70,3 +70,8 @@ int x86_cpu_reinit_f(void)
 {
  return 0;
 }
+
+int cpu_phys_address_size(void)
+{
+ return CONFIG_CPU_ADDR_BITS;
+}
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 21a05dab7de..5b001bbee21 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -288,4 +288,13 @@ u32 cpu_get_family_model(void);
  */
 u32 cpu_get_stepping(void);
 
+/**
+ * cpu_phys_address_size() - Get the physical address size in bits
+ *
+ * This is 32 for older CPUs but newer ones may support 36.
+ *
+ * @return address size (typically 32 or 36)
+ */
+int cpu_phys_address_size(void);
+
 #endif
--
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[PATCH v4 42/59] x86: Sort the MTRR table

Simon Glass-3
In reply to this post by Simon Glass-3
At present the MTRR registers are programmed with the list the U-Boot
builds up in the same order. In some cases this list may be out of order.
It looks better in Linux to have the registers in order, so sort them,

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/cpu/mtrr.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c
index 2468d88a80a..08fa80f8bc7 100644
--- a/arch/x86/cpu/mtrr.c
+++ b/arch/x86/cpu/mtrr.c
@@ -19,6 +19,7 @@
 #include <common.h>
 #include <cpu_func.h>
 #include <log.h>
+#include <sort.h>
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/mp.h>
@@ -124,6 +125,16 @@ static int mtrr_copy_to_aps(void)
  return 0;
 }
 
+static int h_comp_mtrr(const void *p1, const void *p2)
+{
+ const struct mtrr_request *req1 = p1;
+ const struct mtrr_request *req2 = p2;
+
+ s64 diff = req1->start - req2->start;
+
+ return diff < 0 ? -1 : diff > 0 ? 1 : 0;
+}
+
 int mtrr_commit(bool do_caches)
 {
  struct mtrr_request *req = gd->arch.mtrr_req;
@@ -139,6 +150,7 @@ int mtrr_commit(bool do_caches)
  debug("open\n");
  mtrr_open(&state, do_caches);
  debug("open done\n");
+ qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr);
  for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
  set_var_mtrr(i, req->type, req->start, req->size);
 
--
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[PATCH v4 43/59] x86: Notify the FSP of the 'end firmware' event

Simon Glass-3
In reply to this post by Simon Glass-3
Send this notification when U-Boot is about to boot into Linux, as
requested by the FSP.

Currently this causes a crash with the APL FSP, so leave it disabled for
now.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/cpu/cpu.c            | 15 +++++++++++++++
 arch/x86/lib/fsp/fsp_common.c | 16 ++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 69c14189d1f..f8692753963 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -189,6 +189,14 @@ __weak void board_final_init(void)
 {
 }
 
+/*
+ * Implement a weak default function for boards that need to do some final
+ * processing before booting the OS.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
 int last_stage_init(void)
 {
  struct acpi_fadt __maybe_unused *fadt;
@@ -218,6 +226,13 @@ int last_stage_init(void)
  }
  }
 
+ /*
+ * TODO([hidden email]): Move this to bootm_announce_and_cleanup()
+ * once APL FSP-S at 0x200000 does not overlap with the bzimage at
+ * 0x100000.
+ */
+ board_final_cleanup();
+
  return 0;
 }
 #endif
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index ea529547254..4061fa244c4 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -60,6 +60,22 @@ void board_final_init(void)
  debug("OK\n");
 }
 
+void board_final_cleanup(void)
+{
+ u32 status;
+
+ /* TODO([hidden email]): This causes Linux to crash */
+ return;
+
+ /* call into FspNotify */
+ debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): ");
+ status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE);
+ if (status)
+ debug("fail, error code %x\n", status);
+ else
+ debug("OK\n");
+}
+
 int fsp_save_s3_stack(void)
 {
  struct udevice *dev;
--
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[PATCH v4 44/59] x86: Correct the assembly guard in e820.h

Simon Glass-3
In reply to this post by Simon Glass-3
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

Changes in v1:
- Update commit message with a comma

 arch/x86/include/asm/e820.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index d7f8a4ba1df..a66c0d24891 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -22,10 +22,9 @@ struct e820_entry {
 #define ISA_START_ADDRESS 0xa0000
 #define ISA_END_ADDRESS 0x100000
 
-#endif /* __ASSEMBLY__ */
-
 /* Implementation defined function to install an e820 map */
 unsigned int install_e820_map(unsigned int max_entries,
       struct e820_entry *);
+#endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_X86_E820_H */
--
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[PATCH v4 45/59] x86: Add a header guard to asm/acpi_table.h

Simon Glass-3
In reply to this post by Simon Glass-3
This file cannot currently be included in ASL files. Add a header guard
to permit this.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

 arch/x86/include/asm/acpi_table.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index faf31730730..1b49ccadc0c 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_ACPI_TABLE_H__
 #define __ASM_ACPI_TABLE_H__
 
+#ifndef __ACPI__
+
 struct acpi_facs;
 struct acpi_fadt;
 struct acpi_global_nvs;
@@ -213,4 +215,6 @@ void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs,
  */
 void intel_acpi_fill_fadt(struct acpi_fadt *fadt);
 
+#endif /* !__ACPI__ */
+
 #endif /* __ASM_ACPI_TABLE_H__ */
--
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[PATCH v4 46/59] x86: Correct handling of MADT table CPUs

Simon Glass-3
In reply to this post by Simon Glass-3
At present if hyperthreading is disabled the CPU numbering is not
sequential. Fix this.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/lib/acpi_table.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 86a9a35cb25..5876355afe2 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -66,14 +66,17 @@ int acpi_create_madt_lapics(u32 current)
 {
  struct udevice *dev;
  int total_length = 0;
+ int cpu_num = 0;
 
  for (uclass_find_first_device(UCLASS_CPU, &dev);
      dev;
      uclass_find_next_device(&dev)) {
  struct cpu_platdata *plat = dev_get_parent_platdata(dev);
- int length = acpi_create_madt_lapic(
- (struct acpi_madt_lapic *)current,
- plat->cpu_id, plat->cpu_id);
+ int length;
+
+ length = acpi_create_madt_lapic(
+ (struct acpi_madt_lapic *)current, cpu_num++,
+ plat->cpu_id);
  current += length;
  total_length += length;
  }
--
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[PATCH v4 47/59] acpi: tpm: Add a TPM2 table

Simon Glass-3
In reply to this post by Simon Glass-3
This provides information about a v2 TPM in the system. Generate this
table if the TPM is present.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/lib/acpi_table.c | 74 +++++++++++++++++++++++++++++++++++++++
 include/acpi/acpi_table.h | 11 ++++++
 include/bloblist.h        |  1 +
 3 files changed, 86 insertions(+)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 5876355afe2..c31cc923c9c 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <bloblist.h>
 #include <cpu.h>
 #include <dm.h>
 #include <log.h>
@@ -214,6 +215,64 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
  header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
+static int get_tpm2_log(void **ptrp, int *sizep)
+{
+ const int tpm2_default_log_len = 0x10000;
+ int size;
+ int ret;
+
+ *sizep = 0;
+ size = tpm2_default_log_len;
+ ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp);
+ if (ret)
+ return log_msg_ret("blob", ret);
+ *sizep = size;
+
+ return 0;
+}
+
+static int acpi_create_tpm2(struct acpi_tpm2 *tpm2)
+{
+ struct acpi_table_header *header = &tpm2->header;
+ int tpm2_log_len;
+ void *lasa;
+ int ret;
+
+ memset((void *)tpm2, 0, sizeof(struct acpi_tpm2));
+
+ /*
+ * Some payloads like SeaBIOS depend on log area to use TPM2.
+ * Get the memory size and address of TPM2 log area or initialize it.
+ */
+ ret = get_tpm2_log(&lasa, &tpm2_log_len);
+ if (ret)
+ return ret;
+
+ /* Fill out header fields. */
+ acpi_fill_header(header, "TPM2");
+ memcpy(header->aslc_id, ASLC_ID, 4);
+
+ header->length = sizeof(struct acpi_tpm2);
+ header->revision = acpi_get_table_revision(ACPITAB_TPM2);
+
+ /* Hard to detect for coreboot. Just set it to 0 */
+ tpm2->platform_class = 0;
+
+ /* Must be set to 0 for FIFO-interface support */
+ tpm2->control_area = 0;
+ tpm2->start_method = 6;
+ memset(tpm2->msp, 0, sizeof(tpm2->msp));
+
+ /* Fill the log area size and start address fields. */
+ tpm2->laml = tpm2_log_len;
+ tpm2->lasa = (uintptr_t)lasa;
+
+ /* Calculate checksum. */
+ header->checksum = table_compute_checksum((void *)tpm2, header->length);
+
+ return 0;
+}
+
 __weak u32 acpi_fill_csrt(u32 current)
 {
  return 0;
@@ -499,6 +558,21 @@ ulong write_acpi_tables(ulong start_addr)
  acpi_inc_align(ctx, mcfg->header.length);
  acpi_add_table(ctx, mcfg);
 
+ if (IS_ENABLED(CONFIG_TPM_V2)) {
+ struct acpi_tpm2 *tpm2;
+ int ret;
+
+ debug("ACPI:    * TPM2\n");
+ tpm2 = (struct acpi_tpm2 *)ctx->current;
+ ret = acpi_create_tpm2(tpm2);
+ if (!ret) {
+ acpi_inc_align(ctx, tpm2->header.length);
+ acpi_add_table(ctx, tpm2);
+ } else {
+ log_warning("TPM2 table creation failed\n");
+ }
+ }
+
  debug("ACPI:    * MADT\n");
  madt = ctx->current;
  acpi_create_madt(madt);
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index a2e510cf56e..c7ee8b55da4 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -93,6 +93,17 @@ struct __packed acpi_hpet {
  u8 attributes;
 };
 
+struct __packed acpi_tpm2 {
+ struct acpi_table_header header;
+ u16 platform_class;
+ u8  reserved[2];
+ u64 control_area;
+ u32 start_method;
+ u8  msp[12];
+ u32 laml;
+ u64 lasa;
+};
+
 /* FADT Preferred Power Management Profile */
 enum acpi_pm_profile {
  ACPI_PM_UNSPECIFIED = 0,
diff --git a/include/bloblist.h b/include/bloblist.h
index 7d8480548e0..dc7d80bd851 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -33,6 +33,7 @@ enum bloblist_tag_t {
  */
  BLOBLISTT_ACPI_GNVS,
  BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */
+ BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */
 };
 
 /**
--
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[PATCH v4 48/59] acpi: tpm: Add a TPM1 table

Simon Glass-3
In reply to this post by Simon Glass-3
This provides information about a v1 TPM in the system. Generate this
table if the TPM is present.

Add a required new bloblist type and correct the header order of one
header file.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/lib/acpi_table.c | 54 ++++++++++++++++++++++++++++++++++++++-
 include/acpi/acpi_table.h |  7 +++++
 include/bloblist.h        |  1 +
 3 files changed, 61 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index c31cc923c9c..10cf3b70945 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -215,6 +215,47 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
  header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
+/**
+ * acpi_create_tcpa() - Create a TCPA table
+ *
+ * @tcpa: Pointer to place to put table
+ *
+ * Trusted Computing Platform Alliance Capabilities Table
+ * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI
+ * Firmware Specification 3.0
+ */
+static int acpi_create_tcpa(struct acpi_tcpa *tcpa)
+{
+ struct acpi_table_header *header = &tcpa->header;
+ u32 current = (u32)tcpa + sizeof(struct acpi_tcpa);
+ int size = 0x10000; /* Use this as the default size */
+ void *log;
+ int ret;
+
+ if (!CONFIG_IS_ENABLED(BLOBLIST))
+ return -ENXIO;
+ memset(tcpa, '\0', sizeof(struct acpi_tcpa));
+
+ /* Fill out header fields */
+ acpi_fill_header(header, "TCPA");
+ header->length = sizeof(struct acpi_tcpa);
+ header->revision = 1;
+
+ ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log);
+ if (ret)
+ return log_msg_ret("blob", ret);
+
+ tcpa->platform_class = 0;
+ tcpa->laml = size;
+ tcpa->lasa = (ulong)log;
+
+ /* (Re)calculate length and checksum */
+ header->length = current - (u32)tcpa;
+ header->checksum = table_compute_checksum((void *)tcpa, header->length);
+
+ return 0;
+}
+
 static int get_tpm2_log(void **ptrp, int *sizep)
 {
  const int tpm2_default_log_len = 0x10000;
@@ -457,11 +498,13 @@ ulong write_acpi_tables(ulong start_addr)
  struct acpi_fadt *fadt;
  struct acpi_table_header *ssdt;
  struct acpi_mcfg *mcfg;
+ struct acpi_tcpa *tcpa;
  struct acpi_madt *madt;
  struct acpi_csrt *csrt;
  struct acpi_spcr *spcr;
  void *start;
  ulong addr;
+ int ret;
  int i;
 
  start = map_sysmem(start_addr, 0);
@@ -560,7 +603,6 @@ ulong write_acpi_tables(ulong start_addr)
 
  if (IS_ENABLED(CONFIG_TPM_V2)) {
  struct acpi_tpm2 *tpm2;
- int ret;
 
  debug("ACPI:    * TPM2\n");
  tpm2 = (struct acpi_tpm2 *)ctx->current;
@@ -579,6 +621,16 @@ ulong write_acpi_tables(ulong start_addr)
  acpi_inc_align(ctx, madt->header.length);
  acpi_add_table(ctx, madt);
 
+ debug("ACPI:    * TCPA\n");
+ tcpa = (struct acpi_tcpa *)ctx->current;
+ ret = acpi_create_tcpa(tcpa);
+ if (ret) {
+ log_warning("Failed to create TCPA table (err=%d)\n", ret);
+ } else {
+ acpi_inc_align(ctx, tcpa->header.length);
+ acpi_add_table(ctx, tcpa);
+ }
+
  debug("ACPI:    * CSRT\n");
  csrt = ctx->current;
  if (!acpi_create_csrt(csrt)) {
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index c7ee8b55da4..9fba6536f50 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -104,6 +104,13 @@ struct __packed acpi_tpm2 {
  u64 lasa;
 };
 
+struct __packed acpi_tcpa {
+ struct acpi_table_header header;
+ u16 platform_class;
+ u32 laml;
+ u64 lasa;
+};
+
 /* FADT Preferred Power Management Profile */
 enum acpi_pm_profile {
  ACPI_PM_UNSPECIFIED = 0,
diff --git a/include/bloblist.h b/include/bloblist.h
index dc7d80bd851..5784c2226e7 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -34,6 +34,7 @@ enum bloblist_tag_t {
  BLOBLISTT_ACPI_GNVS,
  BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */
  BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */
+ BLOBLISTT_TCPA_LOG, /* TPM log space */
 };
 
 /**
--
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[PATCH v4 49/59] x86: acpi: Set the log category for x86 table generation

Simon Glass-3
In reply to this post by Simon Glass-3
This file doesn't currently have a log category. Add one so that items
are logged correctly.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

 arch/x86/lib/acpi_table.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 10cf3b70945..6d405b09fde 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -6,6 +6,8 @@
  * Copyright (C) 2016, Bin Meng <[hidden email]>
  */
 
+#define LOG_CATEGORY LOGC_ACPI
+
 #include <common.h>
 #include <bloblist.h>
 #include <cpu.h>
--
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[PATCH v4 50/59] x86: coral: Add audio descriptor files

Simon Glass-3
In reply to this post by Simon Glass-3
Add files describing the various audio configurations supported on coral.
These are passed to Linux in the ACPI tables.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

Changes in v1:
- Add new patch with coral audio descriptor files

 .../chromebook_coral/dialog-2ch-48khz-24b.dat    | Bin 0 -> 100 bytes
 .../chromebook_coral/dmic-1ch-48khz-16b.dat      | Bin 0 -> 3048 bytes
 .../chromebook_coral/dmic-2ch-48khz-16b.dat      | Bin 0 -> 3048 bytes
 .../chromebook_coral/dmic-4ch-48khz-16b.dat      | Bin 0 -> 3048 bytes
 .../max98357-render-2ch-48khz-24b.dat            | Bin 0 -> 116 bytes
 5 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
 create mode 100644 board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
 create mode 100644 board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
 create mode 100644 board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
 create mode 100644 board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat

diff --git a/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat b/board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..46c0efbd0adc0883564cf8404503fa1de7c4cc33
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
new file mode 100644
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literal 0
HcmV?d00001

diff --git a/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
new file mode 100644
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GIT binary patch
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literal 0
HcmV?d00001

diff --git a/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat b/board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..142ab353f3736f110f30e9befbd72f7e8ae4264b
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat b/board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..b0b5b9ba648c4546f98e15e42356a5fc4af6bb27
GIT binary patch
literal 116
zcmZQzU|?WnWOx?=qy_%}|BnyXGahJUU??~MR0;$VT+Bccgqa+G1PJi6vnv28CMf>T
R&%gk}Aix2{5<r{+!~hE!AMpSH

literal 0
HcmV?d00001

--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 51/59] x86: apl: Check low-level init in FSP-S pre-init

Simon Glass-3
In reply to this post by Simon Glass-3
If U-Boot is not running FSP-S it should not do the pre-init either. Add a
condition to handle this.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/cpu/apollolake/fsp_s.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index e54b0ac1047..715ceab6ac7 100644
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -157,6 +157,8 @@ int arch_fsps_preinit(void)
  struct udevice *itss;
  int ret;
 
+ if (!ll_boot_init())
+ return 0;
  ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  if (ret)
  return log_msg_ret("no itss", ret);
--
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[PATCH v4 52/59] x86: fsp: Add more debugging for silicon init

Simon Glass-3
In reply to this post by Simon Glass-3
If locating the FSP header hangs for whatever reason it is useful to see
where it got stuck. Add a debug print. Also show the address of the FSP-S
entry point as a sanity check.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

 arch/x86/lib/fsp2/fsp_silicon_init.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c
index 0f221a864fb..ead3493de82 100644
--- a/arch/x86/lib/fsp2/fsp_silicon_init.c
+++ b/arch/x86/lib/fsp2/fsp_silicon_init.c
@@ -26,8 +26,10 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash)
  struct binman_entry entry;
  struct udevice *dev;
  ulong rom_offset = 0;
+ u32 init_addr;
  int ret;
 
+ log_debug("Locating FSP\n");
  ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr,
      &rom_offset);
  if (ret)
@@ -44,7 +46,7 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash)
  ret = fsps_update_config(dev, rom_offset, &upd);
  if (ret)
  return log_msg_ret("Could not setup config", ret);
- log_debug("Silicon init...");
+ log_debug("Silicon init @ %x...", init_addr);
  bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s");
  func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init);
  ret = func(&upd);
--
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[PATCH v4 53/59] x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()

Simon Glass-3
In reply to this post by Simon Glass-3
At present this function only supports FSP-M but it is also used to read
FSP-S, in which case FSP-M may be zero. Add support for showing whichever
address is present in the FSP binary.

Also change the debug() statements to log_debug() while here.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

 arch/x86/lib/fsp2/fsp_support.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c
index 3f2ca840dc9..f220ef498b0 100644
--- a/arch/x86/lib/fsp2/fsp_support.c
+++ b/arch/x86/lib/fsp2/fsp_support.c
@@ -35,7 +35,8 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash,
  *
  * You are in a maze of twisty little headers all alike.
  */
- debug("offset=%x buf=%x\n", (uint)offset, (uint)buf);
+ log_debug("offset=%x buf=%x, use_spi_flash=%d\n", (uint)offset,
+  (uint)buf, use_spi_flash);
  if (use_spi_flash) {
  ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
  if (ret)
@@ -52,16 +53,16 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash,
  fv = ptr;
 
  /* Check the FV signature, _FVH */
- debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
+ log_debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign);
  if (fv->sign != EFI_FVH_SIGNATURE)
  return log_msg_ret("Base FV signature", -EINVAL);
 
  /* Go to the end of the FV header and align the address */
- debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
+ log_debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off);
  ptr += fv->ext_hdr_off;
  exhdr = ptr;
  ptr += ALIGN(exhdr->ext_hdr_size, 8);
- debug("ptr=%x\n", ptr - (void *)buf);
+ log_debug("ptr=%x\n", ptr - (void *)buf);
 
  /* Check the FFS GUID */
  file_hdr = ptr;
@@ -71,7 +72,7 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash,
  ptr = file_hdr + 1;
 
  raw = ptr;
- debug("raw->type = %x\n", raw->type);
+ log_debug("raw->type = %x\n", raw->type);
  if (raw->type != EFI_SECTION_RAW)
  return log_msg_ret("Section type not RAW", -ENOEXEC);
 
@@ -80,13 +81,18 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash,
  fsp = ptr;
 
  /* Check the FSPH header */
- debug("fsp %x\n", (uint)fsp);
+ log_debug("fsp %x, fsp-buf=%x, si=%x\n", (uint)fsp, ptr - (void *)buf,
+  (void *)&fsp->fsp_silicon_init - (void *)buf);
  if (fsp->sign != EFI_FSPH_SIGNATURE)
  return log_msg_ret("Base FSPH signature", -EACCES);
 
  base = (void *)fsp->img_base;
- debug("Image base %x\n", (uint)base);
- debug("Image addr %x\n", (uint)fsp->fsp_mem_init);
+ log_debug("image base %x\n", (uint)base);
+ if (fsp->fsp_mem_init)
+ log_debug("mem_init offset %x\n", (uint)fsp->fsp_mem_init);
+ else if (fsp->fsp_silicon_init)
+ log_debug("silicon_init offset %x\n",
+  (uint)fsp->fsp_silicon_init);
  if (use_spi_flash) {
  ret = spi_flash_read_dm(dev, offset, size, base);
  if (ret)
--
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[PATCH v4 54/59] acpi: Use defines for field lengths

Simon Glass-3
In reply to this post by Simon Glass-3
A few fields have an open-coded length. Use the defines for this purpose
instead.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

 include/acpi/acpi_table.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 9fba6536f50..3a243bf19ce 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -13,6 +13,7 @@
 #ifndef __ACPI_TABLE_H__
 #define __ACPI_TABLE_H__
 
+#include <dm/acpi.h>
 #include <linux/bitops.h>
 
 #define RSDP_SIG "RSD PTR " /* RSDP pointer signature */
@@ -48,7 +49,7 @@ struct acpi_rsdp {
 
 /* Generic ACPI header, provided by (almost) all tables */
 struct __packed acpi_table_header {
- char signature[4]; /* ACPI signature (4 ASCII characters) */
+ char signature[ACPI_NAME_LEN]; /* ACPI signature (4 ASCII chars) */
  u32 length; /* Table length in bytes (incl. header) */
  u8 revision; /* Table version (not ACPI version!) */
  volatile u8 checksum; /* To make sum of entire table == 0 */
@@ -263,7 +264,7 @@ struct __packed acpi_fadt {
 
 /* FACS (Firmware ACPI Control Structure) */
 struct acpi_facs {
- char signature[4]; /* "FACS" */
+ char signature[ACPI_NAME_LEN]; /* "FACS" */
  u32 length; /* Length in bytes (>= 64) */
  u32 hardware_signature; /* Hardware signature */
  u32 firmware_waking_vector; /* Firmware waking vector */
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 55/59] x86: Add a way to add to the e820 memory table

Simon Glass-3
In reply to this post by Simon Glass-3
Some boards want to reserve extra regions of memory. Add a 'chosen'
property to support this.

Reviewed-by: Bin Meng <[hidden email]>
Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/lib/fsp/fsp_dram.c         | 17 +++++++++++++++++
 doc/device-tree-bindings/chosen.txt | 18 ++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index faa819fab4b..a76497d4e01 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -12,6 +12,7 @@
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
+#include <dm/ofnode.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,6 +93,8 @@ unsigned int install_e820_map(unsigned int max_entries,
  unsigned int num_entries = 0;
  const struct hob_header *hdr;
  struct hob_res_desc *res_desc;
+ const fdt64_t *prop;
+ int size;
 
  hdr = gd->arch.hob_list;
 
@@ -133,6 +136,20 @@ unsigned int install_e820_map(unsigned int max_entries,
  num_entries++;
  }
 
+ prop = ofnode_read_chosen_prop("e820-entries", &size);
+ if (prop) {
+ int count = size / (sizeof(u64) * 3);
+ int i;
+
+ if (num_entries + count >= max_entries)
+ return -ENOSPC;
+ for (i = 0; i < count; i++, num_entries++, prop += 3) {
+ entries[num_entries].addr = fdt64_to_cpu(prop[0]);
+ entries[num_entries].size = fdt64_to_cpu(prop[1]);
+ entries[num_entries].type = fdt64_to_cpu(prop[2]);
+ }
+ }
+
  return num_entries;
 }
 
diff --git a/doc/device-tree-bindings/chosen.txt b/doc/device-tree-bindings/chosen.txt
index d4dfc05847b..e5ba6720ce1 100644
--- a/doc/device-tree-bindings/chosen.txt
+++ b/doc/device-tree-bindings/chosen.txt
@@ -143,3 +143,21 @@ This provides the ordering to use when writing device data to the ACPI SSDT
 node to add. The ACPI information is written in this order.
 
 If the ordering does not include all nodes, an error is generated.
+
+e820-entries
+------------
+
+This provides a way to add entries to the e820 table which tells the OS about
+the memory map. The property contains three sets of 64-bit values:
+
+   address   - Start address of region
+   size      - Size of region
+   flags     - Flags (E820_...)
+
+Example:
+
+chosen {
+ e820-entries = /bits/ 64 <
+ IOMAP_P2SB_BAR IOMAP P2SB_SIZE E820_RESERVED
+ MCH_BASE_ADDRESS     MCH_SIZE  E820_RESERVED>;
+};
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 56/59] x86: Move include of bitops out of ACPI region

Simon Glass-3
In reply to this post by Simon Glass-3
At present linux/bitops.h is included in ACPI code. This is not needed and
can cause a problem in fls64.h since BITS_PER_LONG is not defined. Move
the #include into the part not used by ACPI.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v2)

Changes in v2:
- Add new patch to move include of bitops out of ACPI region

 include/acpi/acpi_table.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h
index 3a243bf19ce..abbca6530db 100644
--- a/include/acpi/acpi_table.h
+++ b/include/acpi/acpi_table.h
@@ -14,7 +14,6 @@
 #define __ACPI_TABLE_H__
 
 #include <dm/acpi.h>
-#include <linux/bitops.h>
 
 #define RSDP_SIG "RSD PTR " /* RSDP pointer signature */
 #define OEM_ID "U-BOOT" /* U-Boot */
@@ -29,6 +28,8 @@
 
 #if !defined(__ACPI__)
 
+#include <linux/bitops.h>
+
 struct acpi_ctx;
 
 /*
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 57/59] x86: coral: Update config and device tree for ACPI

Simon Glass-3
In reply to this post by Simon Glass-3
Enable new features and provide require device-tree config so that U-Boot
produces the correct ACPI tables on Coral.

Signed-off-by: Simon Glass <[hidden email]>
---

Changes in v4:
- Correct DPTF enable property
- Correct compatible string for gma device

Changes in v3:
- Rebase to master

Changes in v2:
- Rebase to master

Changes in v1:
- Add NHLT information
- Fix i2c PCI addresses
- Rename acpi-probed to linux,probed
- Rename cpi,hid-desc-reg-offset to hid-desc-addr
- UIse hid-over-i2 compatible string
- Update ACPI ordering to include multiple CPUs
- Use acpi,ddn instead of acpi,desc

 arch/x86/dts/chromebook_coral.dts  | 226 +++++++++++++++++++++++++++--
 configs/chromebook_coral_defconfig |  11 +-
 2 files changed, 221 insertions(+), 16 deletions(-)

diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index a17a9c28003..893a59b1620 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -15,14 +15,20 @@
 #include "flashmap-16mb-rw.dtsi"
 #endif
 
+#include <dt-bindings/clock/intel-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/x86-irq.h>
+#include <asm/e820.h>
 #include <asm/intel_pinctrl_defs.h>
 #include <asm/arch-apollolake/cpu.h>
+#include <asm/arch-apollolake/gpe.h>
 #include <asm/arch-apollolake/gpio.h>
 #include <asm/arch-apollolake/iomap.h>
 #include <asm/arch-apollolake/pm.h>
 #include <dt-bindings/clock/intel-clock.h>
 #include <asm/arch-apollolake/fsp/fsp_m_upd.h>
 #include <asm/arch-apollolake/fsp/fsp_s_upd.h>
+#include <dt-bindings/sound/nhlt.h>
 
 / {
  model = "Google Coral";
@@ -40,6 +46,14 @@
  i2c5 = &i2c_5;
  i2c6 = &i2c_6;
  i2c7 = &i2c_7;
+ mmc1 = &sdmmc;
+ };
+
+ board: board {
+ compatible = "google,coral";
+ recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>;
+ write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>;
+ phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>;
  };
 
  config {
@@ -48,6 +62,15 @@
 
  chosen {
  stdout-path = &serial;
+ e820-entries = /bits/ 64 <
+ IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED
+ MCH_BASE_ADDRESS     MCH_SIZE  E820_RESERVED>;
+ u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3
+ &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5
+ &sdmmc &maxim_codec &wifi &da_codec &tpm
+ &elan_touchscreen &raydium_touchscreen
+ &elan_touchpad &synaptics_touchpad &wacom_digitizer>;
+ u-boot,acpi-dsdt-order = <&board &lpc>;
  };
 
  clk: clock {
@@ -60,7 +83,7 @@
  #address-cells = <1>;
  #size-cells = <0>;
 
- cpu@0 {
+ cpu_0: cpu@0 {
  u-boot,dm-pre-reloc;
  device_type = "cpu";
  compatible = "intel,apl-cpu";
@@ -68,21 +91,21 @@
  intel,apic-id = <0>;
  };
 
- cpu@1 {
+ cpu_1: cpu@1 {
  device_type = "cpu";
  compatible = "intel,apl-cpu";
  reg = <1>;
  intel,apic-id = <2>;
  };
 
- cpu@2 {
+ cpu_2: cpu@2 {
  device_type = "cpu";
  compatible = "intel,apl-cpu";
  reg = <2>;
  intel,apic-id = <4>;
  };
 
- cpu@3 {
+ cpu_3: cpu@3 {
  device_type = "cpu";
  compatible = "intel,apl-cpu";
  reg = <3>;
@@ -128,6 +151,10 @@
  */
  fsp_s: fsp-s {
  };
+
+ nhlt {
+ intel,dmic-channels = <4>;
+ };
  };
 
  punit@0,1 {
@@ -136,21 +163,29 @@
  compatible = "intel,apl-punit";
  };
 
+ gma@2,0 {
+ reg = <0x00001000 0 0 0 0>;
+ compatible = "fsp-fb";
+ };
+
  p2sb: p2sb@d,0 {
  u-boot,dm-pre-reloc;
  reg = <0x02006810 0 0 0 0>;
  compatible = "intel,p2sb";
  early-regs = <IOMAP_P2SB_BAR 0x100000>;
+ pci,no-autoconfig;
 
  n {
  compatible = "intel,apl-pinctrl";
  u-boot,dm-pre-reloc;
  intel,p2sb-port-id = <PID_GPIO_N>;
+ acpi,path = "\\_SB.GPO0";
  gpio_n: gpio-n {
  compatible = "intel,gpio";
  u-boot,dm-pre-reloc;
  gpio-controller;
  #gpio-cells = <2>;
+ linux-name = "INT3452:00";
  };
  };
 
@@ -159,11 +194,13 @@
  compatible = "intel,apl-pinctrl";
  intel,p2sb-port-id = <PID_GPIO_NW>;
  #gpio-cells = <2>;
+ acpi,path = "\\_SB.GPO1";
  gpio_nw: gpio-nw {
  compatible = "intel,gpio";
  u-boot,dm-pre-reloc;
  gpio-controller;
  #gpio-cells = <2>;
+ linux-name = "INT3452:01";
  };
  };
 
@@ -172,11 +209,13 @@
  compatible = "intel,apl-pinctrl";
  intel,p2sb-port-id = <PID_GPIO_W>;
  #gpio-cells = <2>;
+ acpi,path = "\\_SB.GPO2";
  gpio_w: gpio-w {
  compatible = "intel,gpio";
  u-boot,dm-pre-reloc;
  gpio-controller;
  #gpio-cells = <2>;
+ linux-name = "INT3452:02";
  };
  };
 
@@ -185,11 +224,13 @@
  compatible = "intel,apl-pinctrl";
  intel,p2sb-port-id = <PID_GPIO_SW>;
  #gpio-cells = <2>;
+ acpi,path = "\\_SB.GPO3";
  gpio_sw: gpio-sw {
  compatible = "intel,gpio";
  u-boot,dm-pre-reloc;
  gpio-controller;
  #gpio-cells = <2>;
+ linux-name = "INT3452:03";
  };
  };
 
@@ -238,6 +279,24 @@
  gpe0-en = <0x30>;
  };
 
+ audio@e,0 {
+ reg = <0x7000 0 0 0 0>;
+ compatible = "simple-bus";
+ acpi,name = "HDAS";
+ i2s {
+ compatible = "fred";
+ };
+ maxim_codec: maxim-codec {
+ compatible = "maxim,max98357a";
+ acpi,ddn = "Maxim Integrated 98357A Amplifier";
+ sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>;
+ sdmode-delay = <5>;
+ acpi,name = "MAXM";
+ acpi,hid = "MX98357A";
+ acpi,audio-link = <AUDIO_LINK_SSP5>;
+ };
+ };
+
  spi: fast-spi@d,2 {
  u-boot,dm-pre-reloc;
  reg = <0x02006a10 0 0 0 0>;
@@ -267,19 +326,63 @@
  };
  };
 
+ /* WiFi */
+ pcie-a0@14,0 {
+ reg = <0x0000a000 0 0 0 0>;
+ acpi,name = "RP01";
+ wifi: wifi {
+ compatible = "intel,generic-wifi";
+ acpi,ddn = "Intel WiFi";
+ acpi,name = "WF00";
+ acpi,wake = <GPE0_DW3_00>;
+ interrupts-extended = <&acpi_gpe 0x3c 0>;
+ };
+ };
+
  i2c_0: i2c2@16,0 {
  compatible = "intel,apl-i2c";
  reg = <0x0200b010 0 0 0 0>;
  clocks = <&clk CLK_I2C>;
  i2c-scl-rising-time-ns = <104>;
  i2c-scl-falling-time-ns = <52>;
+ clock-frequency = <400000>;
+ i2c,speeds = <100000 400000 1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ da_codec: da-codec {
+ reg = <0x1a>;
+ compatible = "dlg,da7219";
+ interrupts-extended = <&acpi_gpe GPIO_116_IRQ
+ (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
+ acpi,name = "DLG7";
+ acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec";
+ acpi,audio-link = <AUDIO_LINK_SSP1>;
+ dlg,micbias-lvl = <2600>;
+ dlg,mic-amp-in-sel = "diff";
+ da7219_aad {
+ dlg,btn-cfg = <50>;
+ dlg,mic-det-thr = <500>;
+ dlg,jack-ins-deb = <20>;
+ dlg,jack-det-rate = "32ms_64ms";
+ dlg,jack-rem-deb = <1>;
+ dlg,a-d-btn-thr = <0xa>;
+ dlg,d-b-btn-thr = <0x16>;
+ dlg,b-c-btn-thr = <0x21>;
+ dlg,c-mic-btn-thr = <0x3e>;
+ dlg,btn-avg = <4>;
+ dlg,adc-1bit-rpt = <1>;
+ };
+ };
  };
 
  i2c_1: i2c2@16,1 {
  compatible = "intel,apl-i2c";
  reg = <0x0200b110 0 0 0 0>;
  clocks = <&clk CLK_I2C>;
- status = "disabled";
+ clock-frequency = <400000>;
+ i2c,speeds = <100000 400000 1000000 3400000>;
+ i2c-scl-rising-time-ns = <52>;
+ i2c-scl-falling-time-ns = <52>;
  };
 
  i2c_2: i2c2@16,2 {
@@ -288,53 +391,130 @@
  #address-cells = <1>;
  #size-cells = <0>;
  clock-frequency = <400000>;
+ i2c,speeds = <100000 400000 1000000>;
  clocks = <&clk CLK_I2C>;
  i2c-scl-rising-time-ns = <57>;
  i2c-scl-falling-time-ns = <28>;
- tpm@50 {
+ tpm: tpm@50 {
  reg = <0x50>;
  compatible = "google,cr50";
  u-boot,i2c-offset-len = <0>;
  ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
- interrupts-extended = <&acpi_gpe 0x3c 0>;
+ interrupts-extended = <&acpi_gpe GPIO_28_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ acpi,hid = "GOOG0005";
+ acpi,ddn = "I2C TPM";
+ acpi,name = "TPMI";
  };
  };
 
  i2c_3: i2c2@16,3 {
  compatible = "intel,apl-i2c";
- reg = <0x0200b110 0 0 0 0>;
+ reg = <0x0200b310 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
  clocks = <&clk CLK_I2C>;
  i2c-scl-rising-time-ns = <76>;
  i2c-scl-falling-time-ns = <164>;
+ clock-frequency = <400000>;
+ i2c,speeds = <100000 400000>;
+ elan_touchscreen: elan-touchscreen@10 {
+ compatible = "i2c-chip";
+ reg = <0x10>;
+ acpi,hid = "ELAN0001";
+ acpi,ddn = "ELAN Touchscreen";
+ interrupts-extended = <&acpi_gpe GPIO_21_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ linux,probed;
+ reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
+ reset-delay-ms = <20>;
+ enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
+ enable-delay-ms = <1>;
+ acpi,has-power-resource;
+ };
+
+ raydium_touchscreen: raydium-touchscreen@39 {
+ compatible = "i2c-chip";
+ reg = <0x39>;
+ acpi,hid = "RAYD0001";
+ acpi,ddn = "Raydium Touchscreen";
+ interrupts-extended = <&acpi_gpe GPIO_21_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ linux,probed;
+ reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
+ reset-delay-ms = <1>;
+ enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
+ enable-delay-ms = <50>;
+ acpi,has-power-resource;
+ };
  };
 
  i2c_4: i2c2@17,0 {
  compatible = "intel,apl-i2c";
- reg = <0x0200b110 0 0 0 0>;
+ reg = <0x0200b810 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
  clocks = <&clk CLK_I2C>;
  i2c-sda-hold-time-ns = <350>;
  i2c-scl-rising-time-ns = <114>;
  i2c-scl-falling-time-ns = <164>;
+ clock-frequency = <400000>;
+ i2c,speeds = <100000 400000>;
+ elan_touchpad: elan-touchpad@15 {
+ compatible = "i2c-chip";
+ reg = <0x15>;
+ u-boot,i2c-offset-len = <0>;
+ acpi,hid = "ELAN0000";
+ acpi,ddn = "ELAN Touchpad";
+ interrupts-extended = <&acpi_gpe GPIO_18_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ acpi,wake = <GPE0_DW1_15>;
+ linux,probed;
+ };
+ synaptics_touchpad: synaptics-touchpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ acpi,hid = "PNP0C50";
+ acpi,ddn = "Synaptics Touchpad";
+ interrupts-extended = <&acpi_gpe GPIO_18_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ acpi,wake = <GPE0_DW1_15>;
+ linux,probed;
+ hid-descr-addr = <0x20>;
+ };
  };
 
  i2c_5: i2c2@17,1 {
  compatible = "intel,apl-i2c";
- reg = <0x0200b110 0 0 0 0>;
+ reg = <0x0200b910 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
  clocks = <&clk CLK_I2C>;
  i2c-scl-rising-time-ns = <76>;
  i2c-scl-falling-time-ns = <164>;
+ clock-frequency = <400000>;
+ i2c,speeds = <100000 400000 1000000>;
+ wacom_digitizer: wacom-digitizer@9 {
+ compatible = "hid-over-i2c";
+ reg = <0x9>;
+ acpi,hid = "WCOM50C1";
+ acpi,ddn = "WCOM Digitizer";
+ interrupts-extended = <&acpi_gpe GPIO_13_IRQ
+ (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
+ hid-descr-addr = <0x1>;
+ };
  };
 
  i2c_6: i2c2@17,2 {
  compatible = "intel,apl-i2c";
- reg = <0x0200b110 0 0 0 0>;
+ reg = <0x0200ba10 0 0 0 0>;
  clocks = <&clk CLK_I2C>;
  status = "disabled";
  };
 
  i2c_7: i2c2@17,3 {
  compatible = "intel,apl-i2c";
- reg = <0x0200b110 0 0 0 0>;
+ reg = <0x0200bb10 0 0 0 0>;
  clocks = <&clk CLK_I2C>;
  status = "disabled";
  };
@@ -347,6 +527,15 @@
  reg-shift = <2>;
  clock-frequency = <1843200>;
  current-speed = <115200>;
+ acpi,name = "URT3";
+ pci,no-autoconfig;
+ };
+
+ sdmmc: sdmmc@1b,0 {
+ reg = <0x0000d800 0 0 0 0>;
+ compatible = "intel,apl-sd";
+ cd-gpios = <&gpio_n GPIO_177 GPIO_ACTIVE_LOW>;
+ acpi,name = "SDCD";
  };
 
  pch: pch@1f,0 {
@@ -356,7 +545,7 @@
  #address-cells = <1>;
  #size-cells = <1>;
 
- lpc {
+ lpc: lpc {
  compatible = "intel,apl-lpc";
  #address-cells = <1>;
  #size-cells = <0>;
@@ -594,12 +783,17 @@
  * [6:0] steps of delay for HS200, each 125ps
  */
  /* Enable DPTF */
- dptf-enable;
+ fsps,dptf-enabled;
  fsps,emmc-tx-data-cntl1 = <0x0c16>;
  fsps,emmc-tx-data-cntl2 = <0x28162828>;
  fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
  fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
 
+ /* Enable Audio Clock and Power gating */
+ fsps,hd-audio-clk-gate = <1>;
+ fsps,hd-audio-pwr-gate = <1>;
+ fsps,bios-cfg-lock-down = <1>;
+
  /* Enable WiFi */
  fsps,pcie-root-port-en = [01 00 00 00 00 00];
  fsps,pcie-rp-hot-plug = [00 00 00 00 00 00];
@@ -611,6 +805,10 @@
  fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
  fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
 
+ fsps,lpss-s0ix-enable = <1>;
+ fsps,usb-otg = <0>;
+ fsps,monitor-mwait-enable = <0>;
+
  /*
  * TODO([hidden email]): Move this to the I2C nodes
  * Intel Common SoC Config
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index ef4dabbe26e..af0397ff1f4 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x3d00
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_SPL_DM_SPI=y
 CONFIG_SPL_TEXT_BASE=0xfef10000
+CONFIG_MAX_CPUS=8
 CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
 CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -14,9 +15,10 @@ CONFIG_VENDOR_GOOGLE=y
 CONFIG_TARGET_CHROMEBOOK_CORAL=y
 CONFIG_DEBUG_UART=y
 CONFIG_FSP_VERSION2=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_HAVE_ACPI_RESUME=y
 CONFIG_INTEL_CAR_CQOS=y
-CONFIG_X86_OFFSET_U_BOOT=0xffe00000
+CONFIG_X86_OFFSET_U_BOOT=0xffd00000
 CONFIG_X86_OFFSET_SPL=0xffe80000
 CONFIG_INTEL_GENERIC_WIFI=y
 CONFIG_BOOTSTAGE=y
@@ -26,13 +28,14 @@ CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10
 CONFIG_BOOTSTAGE_STASH=y
 CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200"
+CONFIG_BOOTARGS="console=ttyS2,115200n8 cros_legacy loglevel=9 init=/sbin/init oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw noinitrd vt.global_cursor_default=0 add_efi_memmap boot=local noresume noswap i915.modeset=1 nmi_watchdog=panic,lapic disablevmx=off"
 CONFIG_SYS_CONSOLE_INFO_QUIET=y
 CONFIG_SPL_LOG=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_LAST_STAGE_INIT=y
 CONFIG_BLOBLIST=y
 # CONFIG_TPL_BLOBLIST is not set
+CONFIG_BLOBLIST_SIZE=0x30000
 CONFIG_BLOBLIST_ADDR=0x100000
 CONFIG_HANDOFF=y
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
@@ -74,8 +77,10 @@ CONFIG_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_INTEL_ACPIGEN=y
 CONFIG_CPU=y
+CONFIG_BOARD=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
 CONFIG_TPL_MISC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
@@ -87,7 +92,9 @@ CONFIG_PINCTRL=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_SOUND=y
+CONFIG_SOUND_DA7219=y
 CONFIG_SOUND_I8254=y
+CONFIG_SOUND_MAX98357A=y
 CONFIG_SOUND_RT5677=y
 CONFIG_SPI=y
 CONFIG_ICH_SPI=y
--
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[PATCH v4 58/59] acpi: Add more documentation for struct acpi_gpio

Simon Glass-3
In reply to this post by Simon Glass-3
Add some documentation provided by Andy Shevchenko to describe how to
use struct acpi_gpio.

Signed-off-by: Simon Glass <[hidden email]>
---

Changes in v4:
- Add Andy's documentation to struct acpi_gpio

 include/acpi/acpi_device.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 1b838fcb857..007b7e7caf1 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -170,6 +170,28 @@ enum acpi_gpio_polarity {
  * @io_shared; true if GPIO is shared
  * @io_restrict: I/O restriction setting
  * @polarity: GPIO polarity
+ *
+ * Note that GpioIo doesn't have any means of Active Low / High setting, so a
+ * _DSD must be provided to mitigate this.
+ *
+ * GpioIo doesn't properly communicate the initial state of the output pin,
+ * thus Linux assumes the simple rule:
+ *
+ * Pull Bias       Polarity      Requested...
+ *
+ * Implicit        x             AS IS (assumed firmware configured for us)
+ * Explicit        x (no _DSD)   as Pull Bias (Up == High, Down == Low),
+ *                               assuming non-active (Polarity = !Pull Bias)
+ *
+ * Down            Low           as low, assuming active
+ * Down            High          as high, assuming non-active
+ * Up              Low           as high, assuming non-active
+ * Up              High          as high, assuming active
+ *
+ * GpioIo() can be used as interrupt and in this case the IoRestriction mustn't
+ * be OutputOnly. It also requires active_low flag from _DSD in cases where it's
+ * needed (better to always provide than rely on above assumption made on OS
+ * level).
  */
 struct acpi_gpio {
  int pin_count;
--
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[PATCH v4 59/59] acpi: Use I2cSerialBusV2() instead of I2cSerialBus()

Simon Glass-3
In reply to this post by Simon Glass-3
Use the correct name of the ACPI structure being created.

Signed-off-by: Simon Glass <[hidden email]>
---

Changes in v4:
- Add new patch to use I2cSerialBusV2() instead of I2cSerialBus()

 include/acpi/acpi_device.h | 2 +-
 lib/acpi/acpi_device.c     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 007b7e7caf1..ed4acd912a1 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -413,7 +413,7 @@ int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
 /**
  * acpi_device_write_i2c_dev() - Write an I2C device to ACPI
  *
- * This creates a I2cSerialBus descriptor for an I2C device, including
+ * This creates a I2cSerialBusV2 descriptor for an I2C device, including
  * information ACPI needs to use it.
  *
  * @ctx: ACPI context pointer
diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c
index 8248664a10a..95dfac583fc 100644
--- a/lib/acpi/acpi_device.c
+++ b/lib/acpi/acpi_device.c
@@ -530,7 +530,7 @@ int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
  return 0;
 }
 
-/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBus() */
+/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBusV2() */
 static void acpi_device_write_i2c(struct acpi_ctx *ctx,
   const struct acpi_i2c *i2c)
 {
--
2.28.0.681.g6f77f65b4e-goog

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