[PATCH v4 00/59] dm: Add programatic generation of ACPI tables (part D)

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[PATCH v4 00/59] dm: Add programatic generation of ACPI tables (part D)

Simon Glass-3
Note: This is part D of this effort. With this, Coral includes all
required ACPI tables.

At present on x86 U-Boot supports creating ACPI (Advanced Configuration
and Power Interface) tables using the Intel ACPI Source Language (ASL)
compiler.

This is good enough for basic operation but some devices need to add
their information dynamically at runtime. An example is a device that
needs to report its enable GPIO. This is described in the device tree,
so we want to add code in the driver to convert that device-tree
description into an ACPI description for use on Linux.

This series adds support for generation of ACPI tables and fragments by
devices. The core support is built into driver model.

Several files are brought over from coreboot to do the actual generation.

As an example of using this new feature, chromebook_coral is updated to
write out a wide array of ACPI tables including DSDT and SSDT.

This initial version of the series lays out the general approach. More
work is needed to figure out the difference between CONFIG_ACPIGEN and
CONFIG_GENERATE_ACPI_TABLE with respect to what is built.

Changes in v4:
- Add Andy's documentation to struct acpi_gpio
- Add logging when writinge NHLT
- Add new patch to use I2cSerialBusV2() instead of I2cSerialBus()
- Change table version to 3
- Correct DPTF enable property
- Correct comment for dm_test_acpi_write_prw()
- Correct compatible string for gma device
Drop extra acpi_align() in apl_acpi_hb_write_tables()

Changes in v3:
- Rebase to master

Changes in v2:
- Add new patch to allow more space for U-Boot on link
- Add new patch to move include of bitops out of ACPI region
- Fix incorrect space in enable-off-delay-ms
- Rebase to master
- add new patch to fix polarity type in acpi_dp_add_gpio()

Changes in v1:
- Add NHLT audio support
- Add NHLT information
- Add comments
- Add more comments and rename cpu_get_bus_clock to cpu_get_bus_clock_khz()
- Add new patch with coral audio descriptor files
- Add support for NHLT table
- Adjust implementation to match new ACPI GPIO generation
- Capitalise ACPI_OPS_PTR
- Don't build for SPL
- Drop unnecessary callbacks
- Fix i2c PCI addresses
- Handle table generation without callbacks
- Move ASL_REVISION define into this patch
- Move acpi_create_dbg2() into generic code
- Move the acpi.h header file to this commit
- Move this code into an x86-specific file
- Put this code in an x86-specific place and update commit message
- Rename acpi-probed to linux,probed
- Rename cpi,hid-desc-reg-offset to hid-desc-addr
- Split PCT and PTC tables into a separate patch
- Support hid-over-i2c separately as well
- UIse hid-over-i2 compatible string
- Update ACPI ordering to include multiple CPUs
- Update commit message
- Update commit message with a comma
- Update for acpi_device_write_i2c_dev() return-value change
- Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR
- Use SHIFT and MASK for defines
- Use acpi,ddn instead of acpi,desc
- Use this file in APL
- Use updated acpi_device_write_dsm_i2c_hid() function

Simon Glass (59):
  x86: acpi: Add cros_ec tables
  x86: acpi: Add base asl files for common x86 devices
  x86: acpi: apl: Add asl files for Apollo Lake
  x86: acpi: Add DPTF asl files
  x86: apl: Correct PCIE_ECAM_BASE
  x86: Add a config for the systemagent PCIEX regions size
  x86: Add a common global NVS structure
  x86: acpi: Support external GNVS tables
  x86: acpi: Expand the GNVS
  x86: coral: Add ACPI tables for coral
  acpi: Add support for writing a _PRW
  acpi: Add support for conditions and return values
  acpi: Support generating a multi-function _DSM for devices
  dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()
  x86: link: Allow more space for U-Boot
  i2c: Add a generic driver to generate ACPI info
  x86: Add wake sources for the acpi_gpe driver
  x86: apl: Support writing the IntelGraphicsMem table
  x86: acpi: Add a common routine to write WiFi info
  x86: Add some definitions for SMM
  x86: apl: Add power-management definitions
  x86: apl: Update iomap for ACPI
  x86: Add a few common Intel CPU functions
  x86: acpi: Support generation of the HPET table
  x86: acpi: Support generation of the DBG2 table
  acpi: Add support for generating processor tables
  x86: acpi: Add PCT and PTC tables
  acpi: Add more support for generating processor tables
  x86: acpi: Add common Intel ACPI tables
  x86: Support Atom SoCs using SWSMISCI rather than the SWSCI
  x86: acpi: Add support for additional Intel tables
  x86: apl: Allow reading hostbridge base addresses
  p2sb: Add some definitions used for ACPI
  x86: apl: Generate required ACPI tables
  x86: apl: Add support for hostbridge ACPI generation
  x86: apl: Generate CPU tables
  x86: apl: Generate ACPI table for LPC
  x86: apl: Drop unnecessary code in PMC driver
  tpm: cr50: Add ACPI support
  x86: fsp: Update the FSP API with the end-firmware method
  x86: cpu: Report address width from cpu_get_info()
  x86: Sort the MTRR table
  x86: Notify the FSP of the 'end firmware' event
  x86: Correct the assembly guard in e820.h
  x86: Add a header guard to asm/acpi_table.h
  x86: Correct handling of MADT table CPUs
  acpi: tpm: Add a TPM2 table
  acpi: tpm: Add a TPM1 table
  x86: acpi: Set the log category for x86 table generation
  x86: coral: Add audio descriptor files
  x86: apl: Check low-level init in FSP-S pre-init
  x86: fsp: Add more debugging for silicon init
  x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()
  acpi: Use defines for field lengths
  x86: Add a way to add to the e820 memory table
  x86: Move include of bitops out of ACPI region
  x86: coral: Update config and device tree for ACPI
  acpi: Add more documentation for struct acpi_gpio
  acpi: Use I2cSerialBusV2() instead of I2cSerialBus()

 arch/x86/Kconfig                              |  47 ++
 arch/x86/cpu/apollolake/Kconfig               |   4 +
 arch/x86/cpu/apollolake/Makefile              |   1 +
 arch/x86/cpu/apollolake/acpi.c                | 211 ++++++
 arch/x86/cpu/apollolake/cpu.c                 |  77 +++
 arch/x86/cpu/apollolake/fsp_s.c               |   2 +
 arch/x86/cpu/apollolake/hostbridge.c          | 243 ++++++-
 arch/x86/cpu/apollolake/lpc.c                 |  18 +
 arch/x86/cpu/apollolake/pmc.c                 |   8 +-
 arch/x86/cpu/cpu.c                            |  15 +
 arch/x86/cpu/i386/cpu.c                       |  23 +
 arch/x86/cpu/intel_common/Makefile            |   7 +
 arch/x86/cpu/intel_common/acpi.c              | 377 ++++++++++
 arch/x86/cpu/intel_common/cpu.c               |  79 +++
 arch/x86/cpu/intel_common/generic_wifi.c      | 120 ++++
 arch/x86/cpu/intel_common/intel_opregion.c    | 168 +++++
 arch/x86/cpu/mtrr.c                           |  12 +
 arch/x86/cpu/x86_64/cpu.c                     |   5 +
 arch/x86/dts/chromebook_coral.dts             | 226 +++++-
 arch/x86/include/asm/acpi/chromeos.asl        | 108 +++
 arch/x86/include/asm/acpi/cpu.asl             |  25 +
 arch/x86/include/asm/acpi/cros_ec/ac.asl      |  22 +
 arch/x86/include/asm/acpi/cros_ec/als.asl     |  56 ++
 arch/x86/include/asm/acpi/cros_ec/battery.asl | 411 +++++++++++
 arch/x86/include/asm/acpi/cros_ec/cros_ec.asl |  57 ++
 arch/x86/include/asm/acpi/cros_ec/ec.asl      | 557 +++++++++++++++
 arch/x86/include/asm/acpi/cros_ec/emem.asl    |  53 ++
 .../asm/acpi/cros_ec/keyboard_backlight.asl   |  52 ++
 arch/x86/include/asm/acpi/cros_ec/pd.asl      |  15 +
 arch/x86/include/asm/acpi/cros_ec/superio.asl | 159 +++++
 arch/x86/include/asm/acpi/cros_ec/tbmc.asl    |  23 +
 arch/x86/include/asm/acpi/cros_gnvs.asl       |  29 +
 arch/x86/include/asm/acpi/dptf/charger.asl    |  65 ++
 arch/x86/include/asm/acpi/dptf/cpu.asl        | 186 +++++
 arch/x86/include/asm/acpi/dptf/dptf.asl       | 121 ++++
 arch/x86/include/asm/acpi/dptf/fan.asl        |  57 ++
 arch/x86/include/asm/acpi/dptf/thermal.asl    | 521 ++++++++++++++
 arch/x86/include/asm/acpi/global_nvs.h        |   5 +-
 arch/x86/include/asm/acpi/lpc.asl             | 141 ++++
 arch/x86/include/asm/acpi/pci_osc.asl         |  21 +
 arch/x86/include/asm/acpi/pcr.asl             |  80 +++
 arch/x86/include/asm/acpi/ramoops.asl         |  32 +
 arch/x86/include/asm/acpi/sleepstates.asl     |  12 +-
 arch/x86/include/asm/acpi_table.h             | 162 +++++
 arch/x86/include/asm/acpigen.h                |  35 +
 arch/x86/include/asm/arch-apollolake/acpi.h   |  18 +
 .../include/asm/arch-apollolake/acpi/dptf.asl |  35 +
 .../asm/arch-apollolake/acpi/globalnvs.asl    |  41 ++
 .../include/asm/arch-apollolake/acpi/gpio.asl | 191 ++++++
 .../asm/arch-apollolake/acpi/gpiolib.asl      | 109 +++
 .../include/asm/arch-apollolake/acpi/lpss.asl | 105 +++
 .../asm/arch-apollolake/acpi/northbridge.asl  | 120 ++++
 .../asm/arch-apollolake/acpi/pch_hda.asl      |  77 +++
 .../asm/arch-apollolake/acpi/pci_irqs.asl     |  52 ++
 .../include/asm/arch-apollolake/acpi/pcie.asl |  22 +
 .../asm/arch-apollolake/acpi/pcie_port.asl    | 113 +++
 .../asm/arch-apollolake/acpi/platform.asl     |  10 +
 .../asm/arch-apollolake/acpi/pmc_ipc.asl      |  49 ++
 .../include/asm/arch-apollolake/acpi/scs.asl  | 173 +++++
 .../asm/arch-apollolake/acpi/soc_int.asl      |  50 ++
 .../asm/arch-apollolake/acpi/southbridge.asl  |  34 +
 .../include/asm/arch-apollolake/acpi/xhci.asl |  33 +
 .../arch-apollolake/acpi/xhci_apl_ports.asl   |  23 +
 .../arch-apollolake/acpi/xhci_glk_ports.asl   |  24 +
 .../include/asm/arch-apollolake/global_nvs.h  |  23 +-
 arch/x86/include/asm/arch-apollolake/gpe.h    | 135 ++++
 arch/x86/include/asm/arch-apollolake/gpio.h   |   3 +
 arch/x86/include/asm/arch-apollolake/iomap.h  |  16 +
 arch/x86/include/asm/arch-apollolake/pm.h     |  40 +-
 .../include/asm/arch-apollolake/systemagent.h |  31 +
 arch/x86/include/asm/cpu.h                    |   9 +
 arch/x86/include/asm/cpu_common.h             |  56 ++
 arch/x86/include/asm/e820.h                   |   3 +-
 arch/x86/include/asm/fsp/fsp_api.h            |  15 +-
 arch/x86/include/asm/intel_acpi.h             |  52 ++
 arch/x86/include/asm/intel_gnvs.h             |  44 ++
 arch/x86/include/asm/intel_opregion.h         | 247 +++++++
 arch/x86/include/asm/smm.h                    |  27 +
 arch/x86/lib/Makefile                         |   1 +
 arch/x86/lib/acpi_table.c                     | 383 ++++++++++-
 arch/x86/lib/acpigen.c                        |  96 +++
 arch/x86/lib/fsp/fsp_common.c                 |  16 +
 arch/x86/lib/fsp/fsp_dram.c                   |  17 +
 arch/x86/lib/fsp/fsp_graphics.c               |  32 +
 arch/x86/lib/fsp2/fsp_silicon_init.c          |   4 +-
 arch/x86/lib/fsp2/fsp_support.c               |  22 +-
 board/google/chromebook_coral/Kconfig         |   2 +-
 board/google/chromebook_coral/Makefile        |   1 +
 .../chromebook_coral/baseboard_dptf.asl       |  71 ++
 board/google/chromebook_coral/coral.c         | 136 ++++
 .../chromebook_coral/dialog-2ch-48khz-24b.dat | Bin 0 -> 100 bytes
 .../chromebook_coral/dmic-1ch-48khz-16b.dat   | Bin 0 -> 3048 bytes
 .../chromebook_coral/dmic-2ch-48khz-16b.dat   | Bin 0 -> 3048 bytes
 .../chromebook_coral/dmic-4ch-48khz-16b.dat   | Bin 0 -> 3048 bytes
 board/google/chromebook_coral/dsdt.asl        |  60 ++
 .../max98357-render-2ch-48khz-24b.dat         | Bin 0 -> 116 bytes
 .../google/chromebook_coral/variant_dptf.asl  |   6 +
 board/google/chromebook_coral/variant_ec.h    |  75 ++
 board/google/chromebook_coral/variant_gpio.h  |  63 ++
 configs/chromebook_coral_defconfig            |  13 +-
 configs/chromebook_link_defconfig             |   2 +-
 doc/device-tree-bindings/chosen.txt           |  18 +
 doc/device-tree-bindings/device.txt           |   3 +
 doc/device-tree-bindings/i2c/generic-acpi.txt |  42 ++
 drivers/core/Kconfig                          |   9 +
 drivers/i2c/Makefile                          |   3 +
 drivers/i2c/acpi_i2c.c                        | 226 ++++++
 drivers/i2c/acpi_i2c.h                        |  15 +
 drivers/i2c/i2c-uclass.c                      |  17 +
 drivers/sound/max98357a.c                     |   2 +-
 drivers/tpm/cr50_i2c.c                        |  55 ++
 include/acpi/acpi_device.h                    |  93 ++-
 include/acpi/acpi_dp.h                        |   2 +-
 include/acpi/acpi_s3.h                        |   4 +
 include/acpi/acpi_table.h                     | 140 +++-
 include/acpi/acpigen.h                        | 415 +++++++++++
 include/bloblist.h                            |   8 +
 include/i2c.h                                 |  23 +
 include/p2sb.h                                |   8 +
 include/power/acpi_pmc.h                      |   4 +-
 lib/acpi/acpi_device.c                        |  45 +-
 lib/acpi/acpi_dp.c                            |   4 +-
 lib/acpi/acpi_table.c                         |  64 ++
 lib/acpi/acpigen.c                            | 354 ++++++++++
 test/dm/acpi_dp.c                             |   4 +-
 test/dm/acpigen.c                             | 647 ++++++++++++++++++
 126 files changed, 9722 insertions(+), 111 deletions(-)
 create mode 100644 arch/x86/cpu/apollolake/acpi.c
 create mode 100644 arch/x86/cpu/intel_common/acpi.c
 create mode 100644 arch/x86/cpu/intel_common/generic_wifi.c
 create mode 100644 arch/x86/cpu/intel_common/intel_opregion.c
 create mode 100644 arch/x86/include/asm/acpi/chromeos.asl
 create mode 100644 arch/x86/include/asm/acpi/cpu.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/ac.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/als.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/battery.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/cros_ec.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/ec.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/emem.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/pd.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/superio.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/tbmc.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/charger.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/cpu.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/dptf.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/fan.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/thermal.asl
 create mode 100644 arch/x86/include/asm/acpi/lpc.asl
 create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl
 create mode 100644 arch/x86/include/asm/acpi/pcr.asl
 create mode 100644 arch/x86/include/asm/acpi/ramoops.asl
 create mode 100644 arch/x86/include/asm/acpigen.h
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi.h
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/platform.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/scs.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/gpe.h
 create mode 100644 arch/x86/include/asm/intel_acpi.h
 create mode 100644 arch/x86/include/asm/intel_gnvs.h
 create mode 100644 arch/x86/include/asm/intel_opregion.h
 create mode 100644 arch/x86/include/asm/smm.h
 create mode 100644 arch/x86/lib/acpigen.c
 create mode 100644 board/google/chromebook_coral/baseboard_dptf.asl
 create mode 100644 board/google/chromebook_coral/dialog-2ch-48khz-24b.dat
 create mode 100644 board/google/chromebook_coral/dmic-1ch-48khz-16b.dat
 create mode 100644 board/google/chromebook_coral/dmic-2ch-48khz-16b.dat
 create mode 100644 board/google/chromebook_coral/dmic-4ch-48khz-16b.dat
 create mode 100644 board/google/chromebook_coral/dsdt.asl
 create mode 100644 board/google/chromebook_coral/max98357-render-2ch-48khz-24b.dat
 create mode 100644 board/google/chromebook_coral/variant_dptf.asl
 create mode 100644 board/google/chromebook_coral/variant_ec.h
 create mode 100644 board/google/chromebook_coral/variant_gpio.h
 create mode 100644 doc/device-tree-bindings/i2c/generic-acpi.txt
 create mode 100644 drivers/i2c/acpi_i2c.c
 create mode 100644 drivers/i2c/acpi_i2c.h

--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 01/59] x86: acpi: Add cros_ec tables

Simon Glass-3
Add ASL files for the Chrome OS EC, taken from coreboot.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/include/asm/acpi/cros_ec/ac.asl      |  22 +
 arch/x86/include/asm/acpi/cros_ec/als.asl     |  56 ++
 arch/x86/include/asm/acpi/cros_ec/battery.asl | 411 +++++++++++++
 arch/x86/include/asm/acpi/cros_ec/cros_ec.asl |  57 ++
 arch/x86/include/asm/acpi/cros_ec/ec.asl      | 557 ++++++++++++++++++
 arch/x86/include/asm/acpi/cros_ec/emem.asl    |  53 ++
 .../asm/acpi/cros_ec/keyboard_backlight.asl   |  52 ++
 arch/x86/include/asm/acpi/cros_ec/pd.asl      |  15 +
 arch/x86/include/asm/acpi/cros_ec/superio.asl | 159 +++++
 arch/x86/include/asm/acpi/cros_ec/tbmc.asl    |  23 +
 10 files changed, 1405 insertions(+)
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/ac.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/als.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/battery.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/cros_ec.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/ec.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/emem.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/pd.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/superio.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_ec/tbmc.asl

diff --git a/arch/x86/include/asm/acpi/cros_ec/ac.asl b/arch/x86/include/asm/acpi/cros_ec/ac.asl
new file mode 100644
index 00000000000..80e0ebd3ad5
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/ac.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR)
+ {
+ Return (ACEX)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/als.asl b/arch/x86/include/asm/acpi/cros_ec/als.asl
new file mode 100644
index 00000000000..f3d40f889c8
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/als.asl
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ */
+
+Device (ALS)
+{
+ Name (_HID, "ACPI0008")
+ Name (_UID, 1)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+
+ /*
+ * Returns the current ambient light illuminance reading in lux
+ *
+ *  0: Reading is below the range of sensitivity of the sensor
+ * -1: Reading is above the range or sensitivity of the sensor
+ */
+ Method (_ALI, 0, NotSerialized)
+ {
+ Return (^^ALS0)
+ }
+
+ /*
+ * Returns a recommended polling frequency in tenths of seconds
+ *
+ *  0: No need to poll, async notifications will indicate changes
+ */
+ Name (_ALP, 10)
+
+ /*
+ * Returns a package of packages where each tuple consists of a pair
+ * of integers mapping ambient light illuminance to display brightness.
+ *
+ * {<display luminance adjustment>, <ambient light illuminance>}
+ *
+ * Ambient light illuminance values are specified in lux.
+ *
+ * Display luminance adjustment values are relative percentages where
+ * 100 is no (0%) display brightness adjustment.  Values <100 indicate
+ * negative adjustment (dimming) and values >100 indicate positive
+ * adjustment (brightening).
+ *
+ * This is currently unused by the Linux kernel ACPI ALS driver but
+ * is required by the ACPI specification so just define a basic two
+ * point response curve.
+ */
+ Name (_ALR, Package ()
+ {
+ Package () { 70, 30 },    // Min { -30% adjust at 30 lux }
+ Package () { 150, 1000 }  // Max { +50% adjust at 1000 lux }
+ })
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/battery.asl b/arch/x86/include/asm/acpi/cros_ec/battery.asl
new file mode 100644
index 00000000000..f106088231e
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/battery.asl
@@ -0,0 +1,411 @@
+/*/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ */
+
+// Scope (EC0)
+
+/* Mutex for EC battery index interface */
+Mutex (BATM, 0)
+
+// Wait for desired battery index to be presented in shared memory
+//   Arg0 = battery index
+//   Returns Zero on success, One on error.
+Method (BTSW, 1)
+{
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+ If (LEqual (BTIX, Arg0)) {
+ Return (Zero)
+ }
+ If (LGreaterEqual (Arg0, BTCN)) {
+ Return (One)
+ }
+ Store (Arg0, \_SB.PCI0.LPCB.EC0.BTID)
+ Store (5, Local0)      // Timeout 5 msec
+ While (LNotEqual (BTIX, Arg0))
+ {
+ Sleep (1)
+ Decrement (Local0)
+ If (LEqual (Local0, Zero))
+ {
+ Return (One)
+ }
+ }
+#else
+ If (LNotEqual (0, Arg0)) {
+ Return (One)
+ }
+#endif
+ Return (Zero)
+}
+
+// _STA implementation.
+//   Arg0 = battery index
+Method (BSTA, 1, Serialized)
+{
+ If (Acquire (^BATM, 1000)) {
+ Return (Zero)
+ }
+
+ If (And(Not(BTSW (Arg0)), BTEX)) {
+ Store (0x1F, Local0)
+ } Else {
+ Store (0x0F, Local0)
+ }
+
+ Release (^BATM)
+ Return (Local0)
+}
+
+// _BIF implementation.
+//   Arg0 = battery index
+//   Arg1 = PBIF
+Method (BBIF, 2, Serialized)
+{
+ If (Acquire (^BATM, 1000)) {
+ Return (Arg1)
+ }
+
+ If (BTSW (Arg0)) {
+ Release (^BATM)
+ Return (Arg1)
+ }
+ // Last Full Charge Capacity
+ Store (BTDF, Index (Arg1, 2))
+
+ // Design Voltage
+ Store (BTDV, Index (Arg1, 4))
+
+ // Design Capacity
+ Store (BTDA, Local0)
+ Store (Local0, Index (Arg1, 1))
+
+ // Design Capacity of Warning
+ Divide (Multiply (Local0, DWRN), 100, , Local2)
+ Store (Local2, Index (Arg1, 5))
+
+ // Design Capacity of Low
+ Divide (Multiply (Local0, DLOW), 100, , Local2)
+ Store (Local2, Index (Arg1, 6))
+
+ // Get battery info from mainboard
+ Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 9))
+ Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 10))
+ Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 12))
+
+ Release (^BATM)
+ Return (Arg1)
+}
+
+// _BIX implementation.
+//   Arg0 = battery index
+//   Arg1 = PBIX
+Method (BBIX, 2, Serialized)
+{
+ If (Acquire (^BATM, 1000)) {
+ Return (Arg1)
+ }
+
+ If (BTSW (Arg0)) {
+ Release (^BATM)
+ Return (Arg1)
+ }
+ // Last Full Charge Capacity
+ Store (BTDF, Index (Arg1, 3))
+
+ // Design Voltage
+ Store (BTDV, Index (Arg1, 5))
+
+ // Design Capacity
+ Store (BTDA, Local0)
+ Store (Local0, Index (Arg1, 2))
+
+ // Design Capacity of Warning
+ Divide (Multiply (Local0, DWRN), 100, , Local2)
+ Store (Local2, Index (Arg1, 6))
+
+ // Design Capacity of Low
+ Divide (Multiply (Local0, DLOW), 100, , Local2)
+ Store (Local2, Index (Arg1, 7))
+
+ // Cycle Count
+ Store (BTCC, Index (Arg1, 8))
+
+ // Get battery info from mainboard
+ Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 16))
+ Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 17))
+ Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 19))
+
+ Release (^BATM)
+ Return (Arg1)
+}
+
+// _BST implementation.
+//   Arg0 = battery index
+//   Arg1 = PBST
+//   Arg2 = BSTP
+//   Arg3 = BFWK
+Method (BBST, 4, Serialized)
+{
+ If (Acquire (^BATM, 1000)) {
+ Return (Arg1)
+ }
+
+ If (BTSW (Arg0)) {
+ Release (^BATM)
+ Return (Arg1)
+ }
+ //
+ // 0: BATTERY STATE
+ //
+ // bit 0 = discharging
+ // bit 1 = charging
+ // bit 2 = critical level
+ //
+ Store (Zero, Local1)
+
+ // Check if AC is present
+ If (ACEX) {
+ If (BFCG) {
+ Store (0x02, Local1)
+ } ElseIf (BFDC) {
+ Store (0x01, Local1)
+ }
+ } Else {
+ // Always discharging when on battery power
+ Store (0x01, Local1)
+ }
+
+ // Check for critical battery level
+ If (BFCR) {
+ Or (Local1, 0x04, Local1)
+ }
+ Store (Local1, Index (Arg1, 0))
+
+ // Notify if battery state has changed since last time
+ If (LNotEqual (Local1, DeRefOf (Arg2))) {
+ Store (Local1, Arg2)
+ If (LEqual(Arg0, 0)) {
+ Notify (BAT0, 0x80)
+ }
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+ Else {
+ Notify (BAT1, 0x80)
+ }
+#endif
+ }
+
+ //
+ // 1: BATTERY PRESENT RATE
+ //
+ Store (BTPR, Index (Arg1, 1))
+
+ //
+ // 2: BATTERY REMAINING CAPACITY
+ //
+ Store (BTRA, Local1)
+ If (LAnd (Arg3, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) {
+ // On AC power and battery is neither charging
+ // nor discharging.  Linux expects a full battery
+ // to report same capacity as last full charge.
+ // https://bugzilla.kernel.org/show_bug.cgi?id=12632
+ Store (BTDF, Local2)
+
+ // See if within ~6% of full
+ ShiftRight (Local2, 4, Local3)
+ If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+          LLess (Local1, Add (Local2, Local3))))
+ {
+ Store (Local2, Local1)
+ }
+ }
+ Store (Local1, Index (Arg1, 2))
+
+ //
+ // 3: BATTERY PRESENT VOLTAGE
+ //
+ Store (BTVO, Index (Arg1, 3))
+
+ Release (^BATM)
+ Return (Arg1)
+}
+
+Device (BAT0)
+{
+ Name (_HID, EISAID ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ Name (PBIF, Package () {
+ 0x00000001,  // 0x00: Power Unit: mAh
+ 0xFFFFFFFF,  // 0x01: Design Capacity
+ 0xFFFFFFFF,  // 0x02: Last Full Charge Capacity
+ 0x00000001,  // 0x03: Battery Technology: Rechargeable
+ 0xFFFFFFFF,  // 0x04: Design Voltage
+ 0x00000003,  // 0x05: Design Capacity of Warning
+ 0xFFFFFFFF,  // 0x06: Design Capacity of Low
+ 0x00000001,  // 0x07: Capacity Granularity 1
+ 0x00000001,  // 0x08: Capacity Granularity 2
+ "",          // 0x09: Model Number
+ "",          // 0x0a: Serial Number
+ "LION",      // 0x0b: Battery Type
+ ""           // 0x0c: OEM Information
+ })
+
+ Name (PBIX, Package () {
+ 0x00000000,  // 0x00: Revision
+ 0x00000001,  // 0x01: Power Unit: mAh
+ 0xFFFFFFFF,  // 0x02: Design Capacity
+ 0xFFFFFFFF,  // 0x03: Last Full Charge Capacity
+ 0x00000001,  // 0x04: Battery Technology: Rechargeable
+ 0xFFFFFFFF,  // 0x05: Design Voltage
+ 0x00000003,  // 0x06: Design Capacity of Warning
+ 0xFFFFFFFF,  // 0x07: Design Capacity of Low
+ 0x00000000,  // 0x08: Cycle Count
+ 0x00018000,  // 0x09: Measurement Accuracy (98.3%?)
+ 0x000001F4,  // 0x0a: Max Sampling Time (500ms)
+ 0x0000000a,  // 0x0b: Min Sampling Time (10ms)
+ 0xFFFFFFFF,  // 0x0c: Max Averaging Interval
+ 0xFFFFFFFF,  // 0x0d: Min Averaging Interval
+ 0x00000001,  // 0x0e: Capacity Granularity 1
+ 0x00000001,  // 0x0f: Capacity Granularity 2
+ "",          // 0x10 Model Number
+ "",          // 0x11: Serial Number
+ "LION",      // 0x12: Battery Type
+ ""           // 0x13: OEM Information
+ })
+
+ Name (PBST, Package () {
+ 0x00000000,  // 0x00: Battery State
+ 0xFFFFFFFF,  // 0x01: Battery Present Rate
+ 0xFFFFFFFF,  // 0x02: Battery Remaining Capacity
+ 0xFFFFFFFF,  // 0x03: Battery Present Voltage
+ })
+ Name (BSTP, Zero)
+
+ // Workaround for full battery status, disabled by default
+ Name (BFWK, Zero)
+
+ // Method to enable full battery workaround
+ Method (BFWE)
+ {
+ Store (One, BFWK)
+ }
+
+ // Method to disable full battery workaround
+ Method (BFWD)
+ {
+ Store (Zero, BFWK)
+ }
+
+ Method (_STA, 0, Serialized)
+ {
+ Return (BSTA (0))
+ }
+
+ Method (_BIF, 0, Serialized)
+ {
+ Return (BBIF (0, PBIF))
+ }
+
+ Method (_BIX, 0, Serialized)
+ {
+ Return (BBIX (0, PBIX))
+ }
+
+ Method (_BST, 0, Serialized)
+ {
+ Return (BBST (0, PBST, RefOf (BSTP), BFWK))
+ }
+}
+
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+Device (BAT1)
+{
+ Name (_HID, EISAID ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ Name (PBIF, Package () {
+ 0x00000001,  // 0x00: Power Unit: mAh
+ 0xFFFFFFFF,  // 0x01: Design Capacity
+ 0xFFFFFFFF,  // 0x02: Last Full Charge Capacity
+ 0x00000001,  // 0x03: Battery Technology: Rechargeable
+ 0xFFFFFFFF,  // 0x04: Design Voltage
+ 0x00000003,  // 0x05: Design Capacity of Warning
+ 0xFFFFFFFF,  // 0x06: Design Capacity of Low
+ 0x00000001,  // 0x07: Capacity Granularity 1
+ 0x00000001,  // 0x08: Capacity Granularity 2
+ "",          // 0x09: Model Number
+ "",          // 0x0a: Serial Number
+ "LION",      // 0x0b: Battery Type
+ ""           // 0x0c: OEM Information
+ })
+
+ Name (PBIX, Package () {
+ 0x00000000,  // 0x00: Revision
+ 0x00000001,  // 0x01: Power Unit: mAh
+ 0xFFFFFFFF,  // 0x02: Design Capacity
+ 0xFFFFFFFF,  // 0x03: Last Full Charge Capacity
+ 0x00000001,  // 0x04: Battery Technology: Rechargeable
+ 0xFFFFFFFF,  // 0x05: Design Voltage
+ 0x00000003,  // 0x06: Design Capacity of Warning
+ 0xFFFFFFFF,  // 0x07: Design Capacity of Low
+ 0x00000000,  // 0x08: Cycle Count
+ 0x00018000,  // 0x09: Measurement Accuracy (98.3%?)
+ 0x000001F4,  // 0x0a: Max Sampling Time (500ms)
+ 0x0000000a,  // 0x0b: Min Sampling Time (10ms)
+ 0xFFFFFFFF,  // 0x0c: Max Averaging Interval
+ 0xFFFFFFFF,  // 0x0d: Min Averaging Interval
+ 0x00000001,  // 0x0e: Capacity Granularity 1
+ 0x00000001,  // 0x0f: Capacity Granularity 2
+ "",          // 0x10 Model Number
+ "",          // 0x11: Serial Number
+ "LION",      // 0x12: Battery Type
+ ""           // 0x13: OEM Information
+ })
+
+ Name (PBST, Package () {
+ 0x00000000,  // 0x00: Battery State
+ 0xFFFFFFFF,  // 0x01: Battery Present Rate
+ 0xFFFFFFFF,  // 0x02: Battery Remaining Capacity
+ 0xFFFFFFFF,  // 0x03: Battery Present Voltage
+ })
+ Name (BSTP, Zero)
+
+ // Workaround for full battery status, disabled by default
+ Name (BFWK, Zero)
+
+ // Method to enable full battery workaround
+ Method (BFWE)
+ {
+ Store (One, BFWK)
+ }
+
+ // Method to disable full battery workaround
+ Method (BFWD)
+ {
+ Store (Zero, BFWK)
+ }
+
+ Method (_STA, 0, Serialized)
+ {
+ Return (BSTA (1))
+ }
+
+ Method (_BIF, 0, Serialized)
+ {
+ Return (BBIF (1, PBIF))
+ }
+
+ Method (_BIX, 0, Serialized)
+ {
+ Return (BBIX (1, PBIX))
+ }
+
+ Method (_BST, 0, Serialized)
+ {
+ Return (BBST (1, PBST, RefOf (BSTP), BFWK))
+ }
+}
+#endif
diff --git a/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl
new file mode 100644
index 00000000000..9f50185b70f
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+Device (CREC)
+{
+ Name (_HID, "GOOG0004")
+ Name (_UID, 1)
+ Name (_DDN, "EC Command Device")
+#ifdef EC_ENABLE_WAKE_PIN
+ Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 })
+#endif
+
+#ifdef EC_ENABLE_SYNC_IRQ
+ Name (_CRS, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive)
+ {
+ EC_SYNC_IRQ
+ }
+ })
+#endif
+
+#ifdef EC_ENABLE_SYNC_IRQ_GPIO
+ Name (_CRS, ResourceTemplate ()
+ {
+ GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000,
+         "\\_SB.GPIO", 0x00, ResourceConsumer, ,)
+ {
+ EC_SYNC_IRQ
+ }
+ })
+#endif
+
+#ifdef EC_ENABLE_MKBP_DEVICE
+ Device (CKSC)
+ {
+ Name (_HID, "GOOG0007")
+ Name (_UID, 1)
+ Name (_DDN, "EC MKBP Device")
+ }
+#endif
+
+#ifdef EC_ENABLE_CBAS_DEVICE
+ Device (CBAS)
+ {
+ Name (_HID, "GOOG000B")
+ Name (_UID, 1)
+ Name (_DDN, "EC Base Switch Device")
+ }
+#endif
+ Method(_STA, 0)
+ {
+ Return (0xB)
+ }
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/ec.asl b/arch/x86/include/asm/acpi/cros_ec/ec.asl
new file mode 100644
index 00000000000..03f57f25a29
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/ec.asl
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+// Mainboard specific throttle handler
+#ifdef DPTF_ENABLE_CHARGER
+External (\_SB.DPTF.TCHG, DeviceObj)
+#endif
+
+
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 1)
+ Name (_GPE, EC_SCI_GPI)
+ Name (TOFS, EC_TEMP_SENSOR_OFFSET)
+ Name (TNCA, EC_TEMP_SENSOR_NOT_CALIBRATED)
+ Name (TNOP, EC_TEMP_SENSOR_NOT_POWERED)
+ Name (TBAD, EC_TEMP_SENSOR_ERROR)
+ Name (TNPR, EC_TEMP_SENSOR_NOT_PRESENT)
+ Name (DWRN, 15) // Battery capacity warning at 15%
+ Name (DLOW, 10) // Battery capacity low at 10%
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x00),
+ RAMV, 8, // EC RAM Version
+ TSTB, 8, // Test Byte
+ TSTC, 8, // Complement of Test Byte
+ KBLV, 8, // Keyboard Backlight value
+ FAND, 8, // Set Fan Duty Cycle
+ PATI, 8, // Programmable Auxiliary Trip Sensor ID
+ PATT, 8, // Programmable Auxiliary Trip Threshold
+ PATC, 8, // Programmable Auxiliary Trip Commit
+ CHGL, 8, // Charger Current Limit
+ TBMD, 1, // Tablet mode
+ DDPN, 3, // Device DPTF Profile Number
+ // DFUD must be 0 for the other 31 values to be valid
+ Offset (0x0a),
+ DFUD, 1, // Device Features Undefined
+ FLSH, 1, // Flash commands present
+ PFAN, 1, // PWM Fan control present
+ KBLE, 1, // Keyboard Backlight present
+ LTBR, 1, // Lightbar present
+ LEDC, 1, // LED control
+ MTNS, 1, // Motion sensors present
+ KEYB, 1, // EC is keyboard controller
+ PSTR, 1, // Persistent storage
+ P80P, 1, // EC serves I/O Port 80h
+ THRM, 1, // EC supports thermal management
+ SBKL, 1, // Screen backlight switch present
+ WIFI, 1, // WIFI switch present
+ HOST, 1, // EC monitors host events (eg SCI, SMI)
+ GPIO, 1, // EC provides GPIO commands
+ I2CB, 1, // EC provides I2C controller access
+ CHRG, 1, // EC provides commands for charger control
+ BATT, 1, // Simply Battery support
+ SBAT, 1, // Smart Battery support
+ HANG, 1, // EC can detect host hang
+ PMUI, 1, // Power Information
+ DSEC, 1, // another EC exists downstream
+ UPDC, 1, // supports USB Power Delivery
+ UMUX, 1, // supports USB Mux
+ MSFF, 1, // Motion Sense has FIFO
+ TVST, 1, // supports temporary secure vstore
+ TCMV, 1, // USB Type C Muxing is virtual (host assisted)
+ RTCD, 1, // EC provides an RTC device
+ FPRD, 1, // EC provides a fingerprint reader device
+ TPAD, 1, // EC provides a touchpad device
+ RWSG, 1, // EC has RWSIG task enabled
+ DEVE, 1, // EC supports device events
+ // make sure we're within our space envelope
+ Offset (0x0e),
+ Offset (0x12),
+ BTID, 8, // Battery index that host wants to read
+ USPP, 8, // USB Port Power
+}
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
+ OperationRegion (EMEM, EmbeddedControl,
+ EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE)
+ Field (EMEM, ByteAcc, Lock, Preserve)
+#else
+ OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+ Field (EMEM, ByteAcc, NoLock, Preserve)
+#endif
+ {
+ #include "emem.asl"
+ }
+
+#ifdef EC_ENABLE_LID_SWITCH
+ /* LID Switch */
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Return (^^LIDS)
+ }
+
+#ifdef EC_ENABLE_WAKE_PIN
+ Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 })
+#endif
+ }
+#endif
+
+ Method (TINS, 1, Serialized)
+ {
+ Switch (ToInteger (Arg0))
+ {
+ Case (0) { Return (TIN0) }
+ Case (1) { Return (TIN1) }
+ Case (2) { Return (TIN2) }
+ Case (3) { Return (TIN3) }
+ Case (4) { Return (TIN4) }
+ Case (5) { Return (TIN5) }
+ Case (6) { Return (TIN6) }
+ Case (7) { Return (TIN7) }
+ Case (8) { Return (TIN8) }
+ Case (9) { Return (TIN9) }
+ Default  { Return (TIN0) }
+ }
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16,
+    EC_LPC_ADDR_ACPI_DATA,
+    EC_LPC_ADDR_ACPI_DATA,
+    0, 1)
+ IO (Decode16,
+    EC_LPC_ADDR_ACPI_CMD,
+    EC_LPC_ADDR_ACPI_CMD,
+    0, 1)
+ })
+ Return (ECMD)
+ }
+
+ Method (_REG, 2, NotSerialized)
+ {
+ // Initialize AC power state
+ Store (ACEX, \PWRS)
+
+ // Initialize LID switch state
+ Store (LIDS, \LIDS)
+ }
+
+ /* Read requested temperature and check against EC error values */
+ Method (TSRD, 1, Serialized)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0)
+
+ /* Check for sensor not calibrated */
+ If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
+ Return (Zero)
+ }
+
+ /* Check for sensor not present */
+ If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
+ Return (Zero)
+ }
+
+ /* Check for sensor not powered */
+ If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
+ Return (Zero)
+ }
+
+ /* Check for sensor bad reading */
+ If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
+ Return (Zero)
+ }
+
+ /* Adjust by offset to get Kelvin */
+ Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
+
+ /* Convert to 1/10 Kelvin */
+ Multiply (Local0, 10, Local0)
+
+ Return (Local0)
+ }
+
+ // Lid Closed Event
+ Method (_Q01, 0, NotSerialized)
+ {
+ Store ("EC: LID CLOSE", Debug)
+ Store (LIDS, \LIDS)
+#ifdef EC_ENABLE_LID_SWITCH
+ Notify (LID0, 0x80)
+#endif
+ }
+
+ // Lid Open Event
+ Method (_Q02, 0, NotSerialized)
+ {
+ Store ("EC: LID OPEN", Debug)
+ Store (LIDS, \LIDS)
+ Notify (CREC, 0x2)
+#ifdef EC_ENABLE_LID_SWITCH
+ Notify (LID0, 0x80)
+#endif
+ }
+
+ // Power Button
+ Method (_Q03, 0, NotSerialized)
+ {
+ Store ("EC: POWER BUTTON", Debug)
+ }
+
+ // AC Connected
+ Method (_Q04, 0, NotSerialized)
+ {
+ Store ("EC: AC CONNECTED", Debug)
+ Store (ACEX, \PWRS)
+ Notify (AC, 0x80)
+#ifdef DPTF_ENABLE_CHARGER
+ If (CondRefOf (\_SB.DPTF.TCHG)) {
+ Notify (\_SB.DPTF.TCHG, 0x80)
+ }
+#endif
+ \PNOT ()
+ }
+
+ // AC Disconnected
+ Method (_Q05, 0, NotSerialized)
+ {
+ Store ("EC: AC DISCONNECTED", Debug)
+ Store (ACEX, \PWRS)
+ Notify (AC, 0x80)
+#ifdef DPTF_ENABLE_CHARGER
+ If (CondRefOf (\_SB.DPTF.TCHG)) {
+ Notify (\_SB.DPTF.TCHG, 0x80)
+ }
+#endif
+ \PNOT ()
+ }
+
+ // Battery Low Event
+ Method (_Q06, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY LOW", Debug)
+ Notify (BAT0, 0x80)
+ }
+
+ // Battery Critical Event
+ Method (_Q07, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY CRITICAL", Debug)
+ Notify (BAT0, 0x80)
+ }
+
+ // Battery Info Event
+ Method (_Q08, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY INFO", Debug)
+ Notify (BAT0, 0x81)
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+ If (CondRefOf (BAT1)) {
+ Notify (BAT1, 0x81)
+ }
+#endif
+ }
+
+ // Thermal Overload Event
+ Method (_Q0A, 0, NotSerialized)
+ {
+ Store ("EC: THERMAL OVERLOAD", Debug)
+ Notify (\_TZ, 0x80)
+ }
+
+ // Thermal Event
+ Method (_Q0B, 0, NotSerialized)
+ {
+ Store ("EC: THERMAL", Debug)
+ Notify (\_TZ, 0x80)
+ }
+
+ // USB Charger
+ Method (_Q0C, 0, NotSerialized)
+ {
+ Store ("EC: USB CHARGER", Debug)
+ }
+
+ // Key Pressed
+ Method (_Q0D, 0, NotSerialized)
+ {
+ Store ("EC: KEY PRESSED", Debug)
+ Notify (CREC, 0x2)
+ }
+
+ // Thermal Shutdown Imminent
+ Method (_Q10, 0, NotSerialized)
+ {
+ Store ("EC: THERMAL SHUTDOWN", Debug)
+ Notify (\_TZ, 0x80)
+ }
+
+ // Battery Shutdown Imminent
+ Method (_Q11, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY SHUTDOWN", Debug)
+ Notify (BAT0, 0x80)
+ }
+
+ // Throttle Start
+ Method (_Q12, 0, NotSerialized)
+ {
+#ifdef EC_ENABLE_THROTTLING_HANDLER
+ Store ("EC: THROTTLE START", Debug)
+ \_TZ.THRT (1)
+#endif
+ }
+
+ // Throttle Stop
+ Method (_Q13, 0, NotSerialized)
+ {
+#ifdef EC_ENABLE_THROTTLING_HANDLER
+ Store ("EC: THROTTLE STOP", Debug)
+ \_TZ.THRT (0)
+#endif
+ }
+
+#ifdef EC_ENABLE_PD_MCU_DEVICE
+ // PD event
+ Method (_Q16, 0, NotSerialized)
+ {
+ Store ("EC: GOT PD EVENT", Debug)
+ Notify (ECPD, 0x80)
+ }
+#endif
+
+ // Battery Status
+ Method (_Q17, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY STATUS", Debug)
+ Notify (BAT0, 0x80)
+#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE
+ If (CondRefOf (BAT1)) {
+ Notify (BAT1, 0x80)
+ }
+#endif
+ }
+
+ // MKBP interrupt.
+ Method (_Q1B, 0, NotSerialized)
+ {
+ Store ("EC: MKBP", Debug)
+ Notify (CREC, 0x80)
+ }
+
+ // TABLET mode switch Event
+ Method (_Q1D, 0, NotSerialized)
+ {
+ Store ("EC: TABLET mode switch Event", Debug)
+ Notify (CREC, 0x2)
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+ \_SB.DPTF.TPET()
+#endif
+#ifdef EC_ENABLE_TBMC_DEVICE
+ Notify (TBMC, 0x80)
+#endif
+ }
+
+ /*
+ * Dynamic Platform Thermal Framework support
+ */
+
+ /* Mutex for EC PAT interface */
+ Mutex (PATM, 1)
+
+ /*
+ * Set Aux Trip Point 0
+ *   Arg0 = Temp Sensor ID
+ *   Arg1 = Value to set
+ */
+ Method (PAT0, 2, Serialized)
+ {
+ If (Acquire (^PATM, 1000)) {
+ Return (0)
+ }
+
+ /* Set sensor ID */
+ Store (ToInteger (Arg0), ^PATI)
+
+ /* Temperature is passed in 1/10 Kelvin */
+ Divide (ToInteger (Arg1), 10, , Local1)
+
+ /* Adjust by EC temperature offset */
+ Subtract (Local1, ^TOFS, ^PATT)
+
+ /* Set commit value with SELECT=0 and ENABLE=1 */
+ Store (0x02, ^PATC)
+
+ Release (^PATM)
+ Return (1)
+ }
+
+ /*
+ * Set Aux Trip Point 1
+ *   Arg0 = Temp Sensor ID
+ *   Arg1 = Value to set
+ */
+ Method (PAT1, 2, Serialized)
+ {
+ If (Acquire (^PATM, 1000)) {
+ Return (0)
+ }
+
+ /* Set sensor ID */
+ Store (ToInteger (Arg0), ^PATI)
+
+ /* Temperature is passed in 1/10 Kelvin */
+ Divide (ToInteger (Arg1), 10, , Local1)
+
+ /* Adjust by EC temperature offset */
+ Subtract (Local1, ^TOFS, ^PATT)
+
+ /* Set commit value with SELECT=1 and ENABLE=1 */
+ Store (0x03, ^PATC)
+
+ Release (^PATM)
+ Return (1)
+ }
+
+ /* Disable Aux Trip Points
+ *   Arg0 = Temp Sensor ID
+ */
+ Method (PATD, 1, Serialized)
+ {
+ If (Acquire (^PATM, 1000)) {
+ Return (0)
+ }
+
+ Store (ToInteger (Arg0), ^PATI)
+ Store (0x00, ^PATT)
+
+ /* Disable PAT0 */
+ Store (0x00, ^PATC)
+
+ /* Disable PAT1 */
+ Store (0x01, ^PATC)
+
+ Release (^PATM)
+ Return (1)
+ }
+
+ /*
+ * Thermal Threshold Event
+ */
+ Method (_Q09, 0, NotSerialized)
+ {
+ If (LNot(Acquire (^PATM, 1000))) {
+ /* Read sensor ID for event */
+ Store (^PATI, Local0)
+
+ /* When sensor ID returns 0xFF then no more events */
+ While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT))
+ {
+#ifdef HAVE_THERM_EVENT_HANDLER
+ \_SB.DPTF.TEVT (Local0)
+#endif
+
+ /* Keep reaading sensor ID for event */
+ Store (^PATI, Local0)
+ }
+
+ Release (^PATM)
+ }
+ }
+
+ /*
+ * Set Charger Current Limit
+ *   Arg0 = Current Limit in 64mA steps
+ */
+ Method (CHGS, 1, Serialized)
+ {
+ Store (ToInteger (Arg0), ^CHGL)
+ }
+
+ /*
+ * Disable Charger Current Limit
+ */
+ Method (CHGD, 0, Serialized)
+ {
+ Store (0xFF, ^CHGL)
+ }
+
+ /* Read current Tablet mode */
+ Method (RCTM, 0, NotSerialized)
+ {
+ Return (^TBMD)
+ }
+
+ /* Read current Device DPTF Profile Number */
+ Method (RCDP, 0, NotSerialized)
+ {
+ /*
+ * DDPN = 0 is reserved for backwards compatibility.
+ * If DDPN == 0 use TBMD to load appropriate DPTF table.
+ */
+ If (LEqual (^DDPN, 0)) {
+ Return (^TBMD)
+ } Else {
+ Subtract (^DDPN, 1, Local0)
+ Return (Local0)
+ }
+ }
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER)
+ /*
+ * Enable USB Port Power
+ *   Arg0 = USB port ID
+ */
+ Method (UPPS, 1, Serialized)
+ {
+ Or (USPP, ShiftLeft (1, Arg0), USPP)
+ }
+
+ /*
+ * Disable USB Port Power
+ *   Arg0 = USB port ID
+ */
+ Method (UPPC, 1, Serialized)
+ {
+ And (USPP, Not (ShiftLeft (1, Arg0)), USPP)
+ }
+#endif
+
+ #include "ac.asl"
+ #include "battery.asl"
+ #include "cros_ec.asl"
+
+#ifdef EC_ENABLE_ALS_DEVICE
+ #include "als.asl"
+#endif
+
+#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
+ #include "keyboard_backlight.asl"
+#endif
+
+#ifdef EC_ENABLE_PD_MCU_DEVICE
+ #include "pd.asl"
+#endif
+
+#ifdef EC_ENABLE_TBMC_DEVICE
+ #include "tbmc.asl"
+#endif
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/emem.asl b/arch/x86/include/asm/acpi/cros_ec/emem.asl
new file mode 100644
index 00000000000..681ca1c9ded
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/emem.asl
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ */
+
+/*
+ * EMEM data may be accessed through port 62/66 or through LPC at 900h.
+ */
+
+Offset (0x00),
+TIN0, 8, // Temperature 0
+TIN1, 8, // Temperature 1
+TIN2, 8, // Temperature 2
+TIN3, 8, // Temperature 3
+TIN4, 8, // Temperature 4
+TIN5, 8, // Temperature 5
+TIN6, 8, // Temperature 6
+TIN7, 8, // Temperature 7
+TIN8, 8, // Temperature 8
+TIN9, 8, // Temperature 9
+Offset (0x10),
+FAN0, 16, // Fan Speed 0
+Offset (0x24),
+BTVR, 8, // Battery structure version
+Offset (0x30),
+LIDS, 1, // Lid Switch State
+PBTN, 1, // Power Button Pressed
+WPDI, 1, // Write Protect Disabled
+RECK, 1, // Keyboard Initiated Recovery
+RECD, 1, // Dedicated Recovery Mode
+Offset (0x40),
+BTVO, 32, // Battery Present Voltage
+BTPR, 32, // Battery Present Rate
+BTRA, 32, // Battery Remaining Capacity
+ACEX, 1, // AC Present
+BTEX, 1, // Battery Present
+BFDC, 1, // Battery Discharging
+BFCG, 1, // Battery Charging
+BFCR, 1, // Battery Level Critical
+Offset (0x4d),
+BTCN, 8, // Battery Count
+BTIX, 8, // Battery index
+Offset (0x50),
+BTDA, 32, // Battery Design Capacity
+BTDV, 32, // Battery Design Voltage
+BTDF, 32, // Battery Last Full Charge Capacity
+BTCC, 32, // Battery Cycle Count
+BMFG, 64, // Battery Manufacturer String
+BMOD, 64, // Battery Model String
+BSER, 64, // Battery Serial String
+BTYP, 64, // Battery Type String
+Offset (0x80),
+ALS0, 16, // ALS reading 0 in lux
diff --git a/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl
new file mode 100644
index 00000000000..e6edd9680c2
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Google Inc.
+ */
+
+Scope (\_SB)
+{
+ /*
+ * Chrome EC Keyboard Backlight interface
+ */
+ Device (KBLT)
+ {
+ Name (_HID, "GOOG0002")
+ Name (_UID, 1)
+
+ /* Ask EC if we even have a backlight
+ * Return 0xf (present, enabled, show in UI, functioning) or 0
+ *
+ * With older EC codebases that don't support the Device
+ * Features bitfield, this reports the keyboard backlight as
+ * enabled since reads to undefined addresses in EC address
+ * space return 0xff and so KBLE will be 1.
+ */
+ Method (_STA, 0, NotSerialized)
+ {
+ /* If query is unsupported, but this code is compiled
+ * in, assume the backlight exists physically.
+ */
+ If (LEqual (1, \_SB.PCI0.LPCB.EC0.DFUD)) {
+ Return (0xf)
+ }
+ /* If EC reports that backlight exists, trust it */
+ If (LEqual (1, \_SB.PCI0.LPCB.EC0.KBLE)) {
+ Return (0xf)
+ }
+ /* Otherwise: no device -> disable */
+ Return (0)
+ }
+
+ /* Read current backlight value */
+ Method (KBQC, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.KBLV)
+ }
+
+ /* Write new backlight value */
+ Method (KBCM, 1, NotSerialized)
+ {
+ Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/pd.asl b/arch/x86/include/asm/acpi/cros_ec/pd.asl
new file mode 100644
index 00000000000..e55fde347c2
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/pd.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ */
+
+Device (ECPD)
+{
+ Name (_HID, "GOOG0003")
+ Name (_UID, 1)
+ Name (_DDN, "EC PD Device")
+ Method(_STA, 0)
+ {
+ Return (0xB)
+ }
+}
diff --git a/arch/x86/include/asm/acpi/cros_ec/superio.asl b/arch/x86/include/asm/acpi/cros_ec/superio.asl
new file mode 100644
index 00000000000..7ddab1e3cf1
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/superio.asl
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ */
+
+/*
+ * Chrome OS Embedded Controller interface
+ *
+ * Constants that should be defined:
+ *
+ * SIO_EC_MEMMAP_ENABLE     : Enable EC LPC memory map resources
+ * EC_LPC_ADDR_MEMMAP       : Base address of memory map range
+ * EC_MEMMAP_SIZE           : Size of memory map range
+ *
+ * SIO_EC_HOST_ENABLE       : Enable EC host command interface resources
+ * EC_LPC_ADDR_HOST_DATA    : EC host command interface data port
+ * EC_LPC_ADDR_HOST_CMD     : EC host command interface command port
+ * EC_HOST_CMD_REGION0      : EC host command buffer
+ * EC_HOST_CMD_REGION1      : EC host command buffer
+ * EC_HOST_CMD_REGION_SIZE  : EC host command buffer size
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+#ifdef SIO_EC_MEMMAP_ENABLE
+ Device (ECMM) {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 4)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP,
+    0x08, EC_MEMMAP_SIZE)
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP,
+    0x08, EC_MEMMAP_SIZE)
+ })
+ }
+#endif
+
+#ifdef SIO_EC_HOST_ENABLE
+ Device (ECUI) {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 3)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,
+    EC_LPC_ADDR_HOST_DATA, EC_LPC_ADDR_HOST_DATA,
+    0x01, 0x01)
+ IO (Decode16,
+    EC_LPC_ADDR_HOST_CMD, EC_LPC_ADDR_HOST_CMD,
+    0x01, 0x01)
+ IO (Decode16,
+    EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, 0x08,
+    EC_HOST_CMD_REGION_SIZE)
+ IO (Decode16,
+    EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, 0x08,
+    EC_HOST_CMD_REGION_SIZE)
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0, 0) {
+ IO (Decode16, EC_LPC_ADDR_HOST_DATA,
+    EC_LPC_ADDR_HOST_DATA, 0x01, 0x01)
+ IO (Decode16, EC_LPC_ADDR_HOST_CMD,
+    EC_LPC_ADDR_HOST_CMD, 0x01, 0x01)
+ IO (Decode16,
+    EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0,
+    0x08, EC_HOST_CMD_REGION_SIZE)
+ IO (Decode16,
+    EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1,
+    0x08, EC_HOST_CMD_REGION_SIZE)
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+#ifdef SIO_EC_ENABLE_COM1
+ Device (COM1) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 1)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+ IRQNoFlags () {4}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0, 0) {
+ IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
+ IRQNoFlags () {4}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+}
+
+#ifdef SIO_EC_ENABLE_PS2K
+Device (PS2K) // Keyboard
+{
+ Name (_UID, 0)
+ Name (_HID, "GOOG000A")
+ Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } )
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+ IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+#ifdef SIO_EC_PS2K_IRQ
+ SIO_EC_PS2K_IRQ
+#else
+ IRQ (Edge, ActiveHigh, Exclusive) {1}
+#endif
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0) {
+ IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+ IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+#ifdef SIO_EC_PS2K_IRQ
+ SIO_EC_PS2K_IRQ
+#else
+ IRQ (Edge, ActiveHigh, Exclusive) {1}
+#endif
+ }
+ EndDependentFn ()
+ })
+}
+#endif
diff --git a/arch/x86/include/asm/acpi/cros_ec/tbmc.asl b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl
new file mode 100644
index 00000000000..bfe38d668ed
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 Google Inc.
+ */
+
+Device (TBMC)
+{
+ Name (_HID, "GOOG0006")
+ Name (_UID, 1)
+ Name (_DDN, "Tablet Motion Control")
+ Method (TBMC)
+ {
+ If (LEqual (^^RCTM, One)) {
+ Return (0x1)
+ } Else {
+ Return (0x0)
+ }
+ }
+ Method(_STA, 0)
+ {
+ Return (0xB)
+ }
+}
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 02/59] x86: acpi: Add base asl files for common x86 devices

Simon Glass-3
In reply to this post by Simon Glass-3
Add common x86 ASL files, taken from coreboot.

Signed-off-by: Simon Glass <[hidden email]>
Tested-by: Wolfgang Wallner <[hidden email]>
---

(no changes since v1)

 arch/x86/include/asm/acpi/chromeos.asl    | 108 +++++++++++++++++
 arch/x86/include/asm/acpi/cpu.asl         |  25 ++++
 arch/x86/include/asm/acpi/cros_gnvs.asl   |  29 +++++
 arch/x86/include/asm/acpi/lpc.asl         | 141 ++++++++++++++++++++++
 arch/x86/include/asm/acpi/pci_osc.asl     |  21 ++++
 arch/x86/include/asm/acpi/pcr.asl         |  80 ++++++++++++
 arch/x86/include/asm/acpi/ramoops.asl     |  32 +++++
 arch/x86/include/asm/acpi/sleepstates.asl |  12 +-
 8 files changed, 443 insertions(+), 5 deletions(-)
 create mode 100644 arch/x86/include/asm/acpi/chromeos.asl
 create mode 100644 arch/x86/include/asm/acpi/cpu.asl
 create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl
 create mode 100644 arch/x86/include/asm/acpi/lpc.asl
 create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl
 create mode 100644 arch/x86/include/asm/acpi/pcr.asl
 create mode 100644 arch/x86/include/asm/acpi/ramoops.asl

diff --git a/arch/x86/include/asm/acpi/chromeos.asl b/arch/x86/include/asm/acpi/chromeos.asl
new file mode 100644
index 00000000000..2a0fd33265d
--- /dev/null
+++ b/arch/x86/include/asm/acpi/chromeos.asl
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ */
+
+#ifdef CONFIG_CHROMEOS
+
+#define CONFIG_VBOOT_VBNV_OFFSET 0x26
+
+#include <asm/acpi/vbnv_layout.h>
+
+/* GPIO package generated at run time. */
+External (OIPG)
+
+Device (CRHW)
+{
+ Name(_HID, EISAID("GGL0001"))
+
+ Method(_STA, 0, Serialized)
+ {
+ Return (0xb)
+ }
+
+ Method(CHSW, 0, Serialized)
+ {
+ Name (WSHC, Package() { VBT3 })
+ Return (WSHC)
+ }
+
+ Method(FWID, 0, Serialized)
+ {
+ Name (DIW1, "")
+ ToString(VBT5, 63, DIW1)
+ Name (DIWF, Package() { DIW1 })
+ Return(DIWF)
+ }
+
+ Method(FRID, 0, Serialized)
+ {
+ Name (DIR1, "")
+ ToString(VBT6, 63, DIR1)
+ Name (DIRF, Package() { DIR1 })
+ Return (DIRF)
+ }
+
+ Method(HWID, 0, Serialized)
+ {
+ Name (DIW0, "")
+ ToString(VBT4, 255, DIW0)
+ Name (DIWH, Package() { DIW0 })
+ Return (DIWH)
+ }
+
+ Method(BINF, 0, Serialized)
+ {
+ Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+ Return (FNIB)
+ }
+
+ Method(GPIO, 0, Serialized)
+ {
+ Return (OIPG)
+
+ }
+
+ Method(VBNV, 0, Serialized)
+ {
+ Name(VNBV, Package() {
+ // See src/vendorcode/google/chromeos/Kconfig
+ // for the definition of these:
+ CONFIG_VBOOT_VBNV_OFFSET,
+ VBOOT_VBNV_BLOCK_SIZE
+ })
+ Return(VNBV)
+ }
+
+ Method(VDAT, 0, Serialized)
+ {
+ Name(TAD0,"")
+ ToBuffer(CHVD, TAD0)
+ Name (TADV, Package() { TAD0 })
+ Return (TADV)
+ }
+
+ Method(FMAP, 0, Serialized)
+ {
+ Name(PAMF, Package() { VBT9 })
+ Return(PAMF)
+ }
+
+ Method(MECK, 0, Serialized)
+ {
+ Name(HASH, Package() { MEHH })
+ Return(HASH)
+ }
+
+ Method(MLST, 0, Serialized)
+ {
+ Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+ })
+ Return (TSLM)
+ }
+}
+
+#include "ramoops.asl"
+
+#endif
diff --git a/arch/x86/include/asm/acpi/cpu.asl b/arch/x86/include/asm/acpi/cpu.asl
new file mode 100644
index 00000000000..b20b3572f2b
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cpu.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External (\_PR.CNOT, MethodObj)
+
+/* Notify OS to re-read CPU tables */
+Method (PNOT)
+{
+ \_PR.CNOT (0x81)
+}
+
+/* Notify OS to re-read CPU _PPC limit */
+Method (PPCN)
+{
+ \_PR.CNOT (0x80)
+}
+
+/* Notify OS to re-read Throttle Limit tables */
+Method (TNOT)
+{
+ \_PR.CNOT (0x82)
+}
diff --git a/arch/x86/include/asm/acpi/cros_gnvs.asl b/arch/x86/include/asm/acpi/cros_gnvs.asl
new file mode 100644
index 00000000000..c20b64565e0
--- /dev/null
+++ b/arch/x86/include/asm/acpi/cros_gnvs.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+/* This is the ChromeOS specific ACPI information needed by
+ * the mainboard's chromeos.asl
+ */
+
+VBT0,   32, // 0x000 - Boot Reason
+VBT1,   32, // 0x004 - Active Main Firmware
+VBT2,   32, // 0x008 - Active EC Firmware
+VBT3,   16, // 0x00c - CHSW
+VBT4, 2048, // 0x00e - HWID
+VBT5,  512, // 0x10e - FWID
+VBT6,  512, // 0x14e - FRID
+VBT7,   32, // 0x18e - active main firmware type
+VBT8,   32, // 0x192 - Recovery Reason
+VBT9,   32, // 0x196 - FMAP base address
+CHVD, 24576, // 0x19a - VDAT space filled by verified boot
+VBTA, 32, // 0xd9a - pointer to smbios FWID
+MEHH,  256, // 0xd9e - Management Engine Hash
+RMOB,   32, // 0xdbe - RAM oops base address
+RMOL,   32, // 0xdc2 - RAM oops length
+ROVP, 32, // 0xdc6 - pointer to RO_VPD
+ROVL, 32, // 0xdca - size of RO_VPD
+RWVP, 32, // 0xdce - pointer to RW_VPD
+RWVL, 32, // 0xdd2 - size of RW_VPD
+ // 0xdd6
diff --git a/arch/x86/include/asm/acpi/lpc.asl b/arch/x86/include/asm/acpi/lpc.asl
new file mode 100644
index 00000000000..18cc78b3e14
--- /dev/null
+++ b/arch/x86/include/asm/acpi/lpc.asl
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+/* Intel LPC/eSPI Bus Device  - 0:1f.0 */
+#include <asm/arch/iomap.h>
+
+Device (LPCB)
+{
+ Name (_ADR, 0x001f0000)
+ Name (_DDN, "LPC Bus Device")
+
+ /* DMA Controller */
+ Device (DMAC)
+ {
+ Name (_HID, EISAID("PNP0200"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x00, 0x00, 0x01, 0x20)
+ IO (Decode16, 0x81, 0x81, 0x01, 0x11)
+ IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
+ IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
+ })
+ }
+
+ /* Firmware Hub */
+ Device (FWH)
+ {
+ Name (_HID, EISAID ("INT0800"))
+ Name (_DDN, "Firmware Hub")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly, 0xff000000, 0x01000000)
+ })
+ }
+
+ /* High Precision Event Timer */
+ Device (HPET)
+ {
+ Name (_HID, EISAID ("PNP0103"))
+ Name (_CID, 0x010CD041)
+ Name (_DDN, "High Precision Event Timer")
+ Name (_CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+ })
+ Method (_STA, 0)
+ {
+ Return (0xF)
+ }
+ }
+
+ /* FPU */
+ Device(MATH)
+ {
+ Name (_HID, EISAID("PNP0C04"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
+ IRQNoFlags() { 13 }
+ })
+ }
+
+ /* AT Interrupt Controller */
+ Device (PIC)
+ {
+ Name (_HID, EISAID ("PNP0000"))
+ Name (_DDN, "8259 Interrupt Controller")
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x20, 0x20, 0x01, 0x02)
+ IO (Decode16, 0x24, 0x24, 0x01, 0x02)
+ IO (Decode16, 0x28, 0x28, 0x01, 0x02)
+ IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
+ IO (Decode16, 0x30, 0x30, 0x01, 0x02)
+ IO (Decode16, 0x34, 0x34, 0x01, 0x02)
+ IO (Decode16, 0x38, 0x38, 0x01, 0x02)
+ IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
+ IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
+ IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
+ IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
+ IO (Decode16, 0xac, 0xac, 0x01, 0x02)
+ IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
+ IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
+ IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
+ IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
+ IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+ IRQNoFlags () { 2 }
+ })
+ }
+
+ /* LPC device: Resource consumption */
+ Device (LDRC)
+ {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 2)
+ Name (_DDN, "Legacy Device Resources")
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO
+ IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO
+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+ IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,
+    0x1, 0xff)
+ })
+ }
+
+ /* Real Time Clock Device */
+ Device (RTC)
+ {
+ Name (_HID, EISAID ("PNP0B00"))
+ Name (_DDN, "Real Time Clock")
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x70, 0x70, 1, 8)
+ })
+ }
+
+ /* Timer */
+ Device (TIMR)
+ {
+ Name (_HID, EISAID ("PNP0100"))
+ Name (_DDN, "8254 Timer")
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+ IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+ IRQNoFlags () {0}
+ })
+ }
+}
diff --git a/arch/x86/include/asm/acpi/pci_osc.asl b/arch/x86/include/asm/acpi/pci_osc.asl
new file mode 100644
index 00000000000..864556fa831
--- /dev/null
+++ b/arch/x86/include/asm/acpi/pci_osc.asl
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ */
+
+#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766"
+
+Scope (\_SB.PCI0) {
+ Method (_OSC, 4) {
+ /* Check for proper GUID */
+ If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ /* Unrecognized UUID */
+ CreateDWordField (Arg3, 0, CDW1)
+ Or (CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/acpi/pcr.asl b/arch/x86/include/asm/acpi/pcr.asl
new file mode 100644
index 00000000000..f66737b89c1
--- /dev/null
+++ b/arch/x86/include/asm/acpi/pcr.asl
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ */
+
+#include <intelblocks/pcr.h>
+
+/*
+ * Calculate PCR register base at specified PID
+ * Arg0 - PCR Port ID
+ */
+Method (PCRB, 1, NotSerialized)
+{
+ Return (Add (IOMAP_P2SB_BAR,
+ ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
+}
+
+/*
+ * Read a PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ */
+Method (PCRR, 2, Serialized)
+{
+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+ Field (PCRD, DWordAcc, NoLock, Preserve)
+ {
+ DATA, 32
+ }
+ Return (DATA)
+}
+
+/*
+ * AND a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to AND
+ */
+Method (PCRA, 3, Serialized)
+{
+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+ Field (PCRD, DWordAcc, NoLock, Preserve)
+ {
+ DATA, 32
+ }
+ And (DATA, Arg2, DATA)
+
+ /*
+ * After every write one needs to read an innocuous register
+ * to ensure the writes are completed for certain ports. This is done
+ * for all ports so that the callers don't need the per-port knowledge
+ * for each transaction.
+ */
+ PCRR (Arg0, Arg1)
+}
+
+/*
+ * OR a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to OR
+ */
+Method (PCRO, 3, Serialized)
+{
+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+ Field (PCRD, DWordAcc, NoLock, Preserve)
+ {
+ DATA, 32
+ }
+ Or (DATA, Arg2, DATA)
+
+ /*
+ * After every write one needs to read an innocuous register
+ * to ensure the writes are completed for certain ports. This is done
+ * for all ports so that the callers don't need the per-port knowledge
+ * for each transaction.
+ */
+ PCRR (Arg0, Arg1)
+}
diff --git a/arch/x86/include/asm/acpi/ramoops.asl b/arch/x86/include/asm/acpi/ramoops.asl
new file mode 100644
index 00000000000..55939e1aa33
--- /dev/null
+++ b/arch/x86/include/asm/acpi/ramoops.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ */
+
+Scope (\_SB)
+{
+ Device(RMOP)
+ {
+ Name (_HID, "GOOG9999")
+ Name (_CID, "GOOG9999")
+ Name (_UID, 1)
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0, MRES)
+ })
+
+ Method (_CRS)
+ {
+ CreateDwordField (^RBUF, ^MRES._BAS, RBAS)
+ CreateDwordField (^RBUF, ^MRES._LEN, RLEN)
+ Store (\RMOB, RBAS)
+ Store (\RMOL, RLEN)
+ Return (^RBUF)
+ }
+ Method(_STA, 0)
+ {
+ Return (0xB)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl
index 32e16a2c2f5..31aa69a5704 100644
--- a/arch/x86/include/asm/acpi/sleepstates.asl
+++ b/arch/x86/include/asm/acpi/sleepstates.asl
@@ -6,9 +6,11 @@
  * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
  */
 
-Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
-#ifdef CONFIG_HAVE_ACPI_RESUME
-Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S0, Package(){0x0,0x0,0x0,0x0})
+#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+Name(\_S1, Package(){0x1,0x0,0x0,0x0})
+#else
+Name(\_S3, Package(){0x5,0x0,0x0,0x0})
 #endif
-Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
-Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
+Name(\_S4, Package(){0x6,0x0,0x0,0x0})
+Name(\_S5, Package(){0x7,0x0,0x0,0x0})
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 03/59] x86: acpi: apl: Add asl files for Apollo Lake

Simon Glass-3
In reply to this post by Simon Glass-3
Add Apollo Lake ASL files, taken from coreboot.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 .../include/asm/arch-apollolake/acpi/dptf.asl |  35 ++++
 .../asm/arch-apollolake/acpi/globalnvs.asl    |  41 ++++
 .../include/asm/arch-apollolake/acpi/gpio.asl | 191 ++++++++++++++++++
 .../asm/arch-apollolake/acpi/gpiolib.asl      | 109 ++++++++++
 .../include/asm/arch-apollolake/acpi/lpss.asl | 105 ++++++++++
 .../asm/arch-apollolake/acpi/northbridge.asl  | 120 +++++++++++
 .../asm/arch-apollolake/acpi/pch_hda.asl      |  77 +++++++
 .../asm/arch-apollolake/acpi/pci_irqs.asl     |  52 +++++
 .../include/asm/arch-apollolake/acpi/pcie.asl |  22 ++
 .../asm/arch-apollolake/acpi/pcie_port.asl    | 113 +++++++++++
 .../asm/arch-apollolake/acpi/platform.asl     |  10 +
 .../asm/arch-apollolake/acpi/pmc_ipc.asl      |  49 +++++
 .../include/asm/arch-apollolake/acpi/scs.asl  | 173 ++++++++++++++++
 .../asm/arch-apollolake/acpi/soc_int.asl      |  50 +++++
 .../asm/arch-apollolake/acpi/southbridge.asl  |  34 ++++
 .../include/asm/arch-apollolake/acpi/xhci.asl |  33 +++
 .../arch-apollolake/acpi/xhci_apl_ports.asl   |  23 +++
 .../arch-apollolake/acpi/xhci_glk_ports.asl   |  24 +++
 18 files changed, 1261 insertions(+)
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/platform.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/scs.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
 create mode 100644 arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl

diff --git a/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
new file mode 100644
index 00000000000..4c50bb45c0f
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+#define DPTF_CPU_DEVICE TCPU
+#define DPTF_CPU_ADDR 0x00000001
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE 80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC0 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC1 80
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC2 70
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC3 60
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC4 50
+#endif
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
new file mode 100644
index 00000000000..7854f7e1c5d
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Alexandru Gagniuc <[hidden email]> for Intel Corp.)
+ */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/intel/apollolake/include/soc/nvs.h !!!
+ *
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ Offset (0x00),
+ PCNT, 8,      // 0x00 - Processor Count
+ PPCM, 8,      // 0x01 - Max PPC State
+ LIDS, 8,      // 0x02 - LID State
+ PWRS, 8,      // 0x03 - AC Power State
+ DPTE, 8,      // 0x04 - Enable DPTF
+ CBMC, 32,     // 0x05 - 0x08 - coreboot Memory Console
+ PM1I, 64,     // 0x09 - 0x10 - System Wake Source - PM1 Index
+ GPEI, 64,     // 0x11 - 0x18 - GPE Wake Source
+ NHLA, 64,     // 0x19 - 0x20 - NHLT Address
+ NHLL, 32,     // 0x21 - 0x24 - NHLT Length
+ PRT0, 32,     // 0x25 - 0x28 - PERST_0 Address
+ SCDP, 8,      // 0x29 - SD_CD GPIO portid
+ SCDO, 8,      // 0x2A - GPIO pad offset relative to the community
+ UIOR, 8,      // 0x2B - UART debug controller init on S3 resume
+ EPCS,   8,      // 0x2C - SGX Enabled status
+ EMNA,   64,     // 0x2D - 0x34 EPC base address
+ ELNG,   64,     // 0x35 - 0x3C EPC Length
+
+ /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
+ Offset (0x100),
+ #include <asm/acpi/cros_gnvs.asl>
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
new file mode 100644
index 00000000000..b0f892166b5
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <[hidden email]> for Intel Corp.)
+ */
+#include <asm/arch/gpio.h>
+#include <asm/intel_pinctrl_defs.h>
+// #include <intelblocks/pcr.h>
+// #include <soc/pcr_ids.h>
+#include <asm/arch/iomap.h>
+#include <p2sb.h>
+#include "gpiolib.asl"
+
+scope (\_SB) {
+
+ Device (GPO0)
+ {
+ Name (_HID, GPIO_COMM_NAME)
+ Name (_CID, GPIO_COMM_NAME)
+ Name (_DDN, GPIO_COMM_0_DESC)
+ Name (_UID, 1)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0)
+ Or (IOMAP_P2SB_BAR, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
+ Device (GPO1)
+ {
+ Name (_HID, GPIO_COMM_NAME)
+ Name (_CID, GPIO_COMM_NAME)
+ Name (_DDN, GPIO_COMM_1_DESC)
+ Name (_UID, 2)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0)
+ Or (IOMAP_P2SB_BAR, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
+ Device (GPO2)
+ {
+ Name (_HID, GPIO_COMM_NAME)
+ Name (_CID, GPIO_COMM_NAME)
+ Name (_DDN, GPIO_COMM_2_DESC)
+ Name (_UID, 3)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0)
+ Or (IOMAP_P2SB_BAR, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
+ Device (GPO3)
+ {
+ Name (_HID, GPIO_COMM_NAME)
+ Name (_CID, GPIO_COMM_NAME)
+ Name (_DDN, GPIO_COMM_3_DESC)
+ Name (_UID, 4)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x4000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
+ {
+ GPIO_BANK_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0)
+ Or (IOMAP_P2SB_BAR, Local0, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return(0xf)
+ }
+ }
+
+ Scope(\_SB.PCI0) {
+ /* PERST Assertion
+ * Note: PERST is Active High
+ */
+ Method (PRAS, 0x1, Serialized)
+ {
+ /*
+ * Assert PERST
+ * local1 - to toggle Tx pin of Dw0
+ * local2 - Address of PERST
+ */
+ Store (Arg0, Local2)
+ Store (\_SB.GPC0 (Local2), Local1)
+ Or (Local1, PAD_CFG0_TX_STATE, Local1)
+ \_SB.SPC0 (Local2, Local1)
+ }
+
+ /* PERST DE-Assertion */
+ Method (PRDA, 0x1, Serialized)
+ {
+ /*
+ * De-assert PERST
+ * local1 - to toggle Tx pin of Dw0
+ * local2 - Address of PERST
+ */
+ Store (Arg0, Local2)
+ Store (\_SB.GPC0 (Local2), Local1)
+ And (Local1, Not (PAD_CFG0_TX_STATE), Local1)
+ \_SB.SPC0 (Local2, Local1)
+ }
+ }
+
+ /*
+ * Sleep button device ASL code. We are using this device to
+ * add the _PRW method for a dummy wake event to kernel so that
+ * before going to sleep kernel does not clear bit 15 in ACPI
+ * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit.
+ */
+ Device (SLP)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+
+ Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 })
+ }
+}
+
+Scope(\_GPE)
+{
+ /*
+ * Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
+ * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
+ * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
+ * GPE0a_EN at 0x430 is reserved.
+ */
+ Method(_L0F, 0) {}
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
new file mode 100644
index 00000000000..0eb808dc195
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Scope (\_SB)
+{
+ /* Get Pad Configuration DW0 register value */
+ Method (GPC0, 0x1, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ Store (Arg0, Local0)
+ OperationRegion (PDW0, SystemMemory, Local0, 4)
+ Field (PDW0, AnyAcc, NoLock, Preserve) {
+ TEMP, 32
+ }
+ Return (TEMP)
+ }
+
+ /* Set Pad Configuration DW0 register value */
+ Method (SPC0, 0x2, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ /* Arg1 - Value for DW0 register */
+ Store (Arg0, Local0)
+ OperationRegion (PDW0, SystemMemory, Local0, 4)
+ Field (PDW0, AnyAcc, NoLock, Preserve) {
+ TEMP,32
+ }
+ Store (Arg1, TEMP)
+ }
+
+ /* Get Pad Configuration DW1 register value */
+ Method (GPC1, 0x1, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ Store (Add (Arg0, 0x4), Local0)
+ OperationRegion (PDW1, SystemMemory, Local0, 4)
+ Field (PDW1, AnyAcc, NoLock, Preserve) {
+ TEMP, 32
+ }
+ Return (TEMP)
+ }
+
+ /* Set Pad Configuration DW1 register value */
+ Method (SPC1, 0x2, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ /* Arg1 - Value for DW1 register */
+ Store (Add (Arg0, 0x4), Local0)
+ OperationRegion (PDW1, SystemMemory, Local0, 4)
+ Field(PDW1, AnyAcc, NoLock, Preserve) {
+ TEMP,32
+ }
+ Store (Arg1, TEMP)
+ }
+
+ /* Get DW0 address of a given pad */
+ Method (GDW0, 0x2, Serialized)
+ {
+ /* Arg0 - GPIO portid */
+ /* Arg1 - GPIO pad offset relative to the community */
+ Store (0, Local1)
+ Or( Or (ShiftLeft (Arg0, 16), IOMAP_P2SB_BAR),
+ Local1, Local1)
+ Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply (
+ GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1)
+ Return (Local1)
+ }
+
+ /* Calculate HOSTSW_REG address */
+ Method (CHSA, 0x1, Serialized)
+ {
+ /* Arg0 - GPIO pad offset relative to the community */
+ Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1)
+ Return (Local1)
+ }
+
+ /* Get Host ownership register of GPIO Community */
+ Method (GHO, 0x2, Serialized)
+ {
+ /* Arg0 - GPIO portid */
+ /* Arg1 - GPIO pad offset relative to the community */
+ Store (CHSA (Arg1), Local1)
+
+ OperationRegion (SHO0, SystemMemory, Or ( Or
+ (IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4)
+ Field (SHO0, AnyAcc, NoLock, Preserve) {
+ TEMP, 32
+ }
+ Return (TEMP)
+ }
+
+ /* Set Host ownership register of GPIO Community */
+ Method (SHO, 0x3, Serialized)
+ {
+ /* Arg0 - GPIO portid */
+ /* Arg1 - GPIO pad offset relative to the community */
+ /* Arg2 - Value for Host own register */
+ Store (CHSA (Arg1), Local1)
+
+ OperationRegion (SHO0, SystemMemory, Or ( Or
+ (IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4)
+ Field (SHO0, AnyAcc, NoLock, Preserve) {
+ TEMP, 32
+ }
+ Store (Arg2, TEMP)
+ }
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
new file mode 100644
index 00000000000..bc3eabba603
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <[hidden email]> for Intel Corp.)
+ */
+
+scope (\_SB.PCI0) {
+
+ /* LPIO1 PWM */
+ Device(PWM) {
+ Name (_ADR, 0x001A0000)
+ Name (_DDN, "Intel(R) PWM Controller")
+ }
+
+ /* LPIO1 HS-UART #1 */
+ Device(URT1) {
+ Name (_ADR, 0x00180000)
+ Name (_DDN, "Intel(R) HS-UART Controller #1")
+ }
+
+ /* LPIO1 HS-UART #2 */
+ Device(URT2) {
+ Name (_ADR, 0x00180001)
+ Name (_DDN, "Intel(R) HS-UART Controller #2")
+ }
+
+ /* LPIO1 HS-UART #3 */
+ Device(URT3) {
+ Name (_ADR, 0x00180002)
+ Name (_DDN, "Intel(R) HS-UART Controller #3")
+ }
+
+ /* LPIO1 HS-UART #4 */
+ Device(URT4) {
+ Name (_ADR, 0x00180003)
+ Name (_DDN, "Intel(R) HS-UART Controller #4")
+ }
+
+ /* LPIO1 SPI */
+ Device(SPI1) {
+ Name (_ADR, 0x00190000)
+ Name (_DDN, "Intel(R) SPI Controller #1")
+ }
+
+ /* LPIO1 SPI #2 */
+ Device(SPI2) {
+ Name (_ADR, 0x00190001)
+ Name (_DDN, "Intel(R) SPI Controller #2")
+ }
+
+ /* LPIO1 SPI #3 */
+ Device(SPI3) {
+ Name (_ADR, 0x00190002)
+ Name (_DDN, "Intel(R) SPI Controller #3")
+ }
+
+
+ /* LPIO2 I2C #0 */
+ Device(I2C0) {
+ Name (_ADR, 0x00160000)
+ Name (_DDN, "Intel(R) I2C Controller #0")
+ }
+
+ /* LPIO2 I2C #1 */
+ Device(I2C1) {
+ Name (_ADR, 0x00160001)
+ Name (_DDN, "Intel(R) I2C Controller #1")
+ }
+
+ /* LPIO2 I2C #2 */
+ Device(I2C2) {
+ Name (_ADR, 0x00160002)
+ Name (_DDN, "Intel(R) I2C Controller #2")
+ }
+
+ /* LPIO2 I2C #3 */
+ Device(I2C3) {
+ Name (_ADR, 0x00160003)
+ Name (_DDN, "Intel(R) I2C Controller #3")
+ }
+
+ /* LPIO2 I2C #4 */
+ Device(I2C4) {
+ Name (_ADR, 0x00170000)
+ Name (_DDN, "Intel(R) I2C Controller #4")
+ }
+
+ /* LPIO2 I2C #5 */
+ Device(I2C5) {
+ Name (_ADR, 0x00170001)
+ Name (_DDN, "Intel(R) I2C Controller #5")
+ }
+
+ /* LPIO2 I2C #6 */
+ Device(I2C6) {
+ Name (_ADR, 0x00170002)
+ Name (_DDN, "Intel(R) I2C Controller #6")
+ }
+
+ /* LPIO2 I2C #7 */
+ Device(I2C7) {
+ Name (_ADR, 0x00170003)
+ Name (_DDN, "Intel(R) I2C Controller #7")
+ }
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
new file mode 100644
index 00000000000..ff5657abd06
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <[hidden email]> for Intel Corp.)
+ */
+
+ Name(_HID, EISAID("PNP0A08")) /* PCIe */
+ Name(_CID, EISAID("PNP0A03")) /* PCI */
+ Name(_BBN, 0)
+
+Device (MCHC)
+{
+ Name (_ADR, 0x00000000) /*Dev0 Func0 */
+
+ OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
+ Field (MCHP, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x60),
+ MCNF, 32, /* PCI MMCONF base */
+ Offset (0xA8),
+ TUUD, 64, /* Top of Upper Used Memory */
+ Offset(0xB4),
+ BGSM,   32, /* Base of Graphics Stolen Memory */
+ Offset(0xBC),
+ TLUD,   32, /* Top of Low Useable DRAM */
+ }
+}
+Name (MCRS, ResourceTemplate()
+{
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000,,,)
+
+ /* Data and GFX stolen memory */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000,
+ 0x04200000,,, STOM)
+
+ /*
+ * PCI MMIO Region (TOLUD - PCI extended base MMCONF)
+ * This assumes that MMCONF is placed after PCI config space,
+ * and that no resources are allocated after the MMCONF region.
+ * This works, sicne MMCONF is hardcoded to 0xe00000000.
+ */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000,,, PM01)
+
+ /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,
+ 0x10000,,, PM02)
+})
+
+/* Current Resource Settings */
+Method (_CRS, 0, Serialized)
+{
+
+ /* Find PCI resource area in MCRS */
+ CreateDwordField (MCRS, ^PM01._MIN, PMIN)
+ CreateDwordField (MCRS, ^PM01._MAX, PMAX)
+ CreateDwordField (MCRS, ^PM01._LEN, PLEN)
+
+ /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
+ And(^MCHC.TLUD, 0xFFF00000, PMIN)
+ /* Read MMCONF base */
+ And(^MCHC.MCNF, 0xF0000000, PMAX)
+
+ /* Calculate PCI MMIO Length */
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+ /* Find GFX resource area in GCRS */
+ CreateDwordField(MCRS, ^STOM._MIN, GMIN)
+ CreateDwordField(MCRS, ^STOM._MAX, GMAX)
+ CreateDwordField(MCRS, ^STOM._LEN, GLEN)
+
+ /* Read BGSM */
+ And(^MCHC.BGSM, 0xFFF00000, GMIN)
+
+ /* Read TOLUD */
+ And(^MCHC.TLUD, 0xFFF00000, GMAX)
+ Decrement(GMAX)
+ Add(Subtract(GMAX, GMIN), 1, GLEN)
+
+ /* Patch PM02 range based on Memory Size */
+ CreateQwordField (MCRS, ^PM02._MIN, MMIN)
+ CreateQwordField (MCRS, ^PM02._MAX, MMAX)
+ CreateQwordField (MCRS, ^PM02._LEN, MLEN)
+
+ Store (^MCHC.TUUD, Local0)
+
+ If (LLessEqual (Local0, 0x1000000000))
+ {
+ Store (0, MMIN)
+ Store (0, MLEN)
+ }
+ Subtract (Add (MMIN, MLEN), 1, MMAX)
+
+ Return (MCRS)
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
new file mode 100644
index 00000000000..cc3b7a769da
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2016 Google Inc.
+ *
+ */
+
+/* Audio Controller - Device 14, Function 0 */
+
+Device (HDAS)
+{
+ Name (_ADR, 0x000E0000)
+ Name (_DDN, "Audio Controller")
+ Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+ /* Device is D3 wake capable */
+ Name (_S0W, 3)
+
+ /* NHLT Table Address populated from GNVS values */
+ Name (NBUF, ResourceTemplate() {
+ QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+ MaxFixed, Cacheable, ReadOnly,
+ 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+ }
+ )
+
+ /* can wake up from S3 state */
+ Name (_PRW, Package() { GPE0A_AVS_PME_STS, 3 })
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4) {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 0: Function Support Query
+ * Returns a bitmask of functions supported.
+ */
+ If (LEqual (Arg2, Zero)) {
+ /*
+ * NHLT Query only supported for revision 1 and
+ * if NHLT address and length are set in NVS.
+ */
+ If (LAnd (LEqual (Arg1, One),
+ LAnd (LNotEqual (NHLA, Zero),
+     LNotEqual (NHLL, Zero)))) {
+ Return (Buffer (One) { 0x03 })
+ }
+ Else {
+ Return (Buffer (One) { 0x01 })
+ }
+ }
+
+ /*
+ * Function 1: Query NHLT memory address used by
+ * Intel Offload Engine Driver to discover any non-HDA
+ * devices that are supported by the DSP.
+ *
+ * Returns a pointer to NHLT table in memory.
+ */
+ If (LEqual (Arg2, One)) {
+ CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+ CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+ CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+ Store (NHLA, NBAS)
+ Store (NHLA, NMAS)
+ Store (NHLL, NLEN)
+ Return (NBUF)
+ }
+ }
+
+ Return (Buffer (One) { 0x00 })
+ }
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
new file mode 100644
index 00000000000..21a1ca9ff9c
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <[hidden email]> for Intel Corp.)
+ */
+
+#include "soc_int.asl"
+
+Method(_PRT)
+{
+ Return(Package() {
+
+ Package(){0x0000FFFF, 0, 0, NPK_INT},
+ Package(){0x0000FFFF, 1, 0, PUNIT_INT},
+ Package(){0x0002FFFF, 0, 0, GEN_INT},
+ Package(){0x0003FFFF, 0, 0, IUNIT_INT},
+ Package(){0x000DFFFF, 1, 0, PMC_INT},
+ Package(){0x000EFFFF, 0, 0, AUDIO_INT},
+ Package(){0x000FFFFF, 0, 0, CSE_INT},
+ Package(){0x0011FFFF, 0, 0, ISH_INT},
+ Package(){0x0012FFFF, 0, 0, SATA_INT},
+ Package(){0x0013FFFF, 0, 0, PIRQA_INT},
+ Package(){0x0013FFFF, 1, 0, PIRQB_INT},
+ Package(){0x0013FFFF, 2, 0, PIRQC_INT},
+ Package(){0x0013FFFF, 3, 0, PIRQD_INT},
+ Package(){0x0014FFFF, 0, 0, PIRQB_INT},
+ Package(){0x0014FFFF, 1, 0, PIRQC_INT},
+ Package(){0x0014FFFF, 2, 0, PIRQD_INT},
+ Package(){0x0014FFFF, 3, 0, PIRQA_INT},
+ Package(){0x0015FFFF, 0, 0, XHCI_INT},
+ Package(){0x0015FFFF, 1, 0, XDCI_INT},
+ Package(){0x0016FFFF, 0, 0, I2C0_INT},
+ Package(){0x0016FFFF, 1, 0, I2C1_INT},
+ Package(){0x0016FFFF, 2, 0, I2C2_INT},
+ Package(){0x0016FFFF, 3, 0, I2C3_INT},
+ Package(){0x0017FFFF, 0, 0, I2C4_INT},
+ Package(){0x0017FFFF, 1, 0, I2C5_INT},
+ Package(){0x0017FFFF, 2, 0, I2C6_INT},
+ Package(){0x0017FFFF, 3, 0, I2C7_INT},
+ Package(){0x0018FFFF, 0, 0, UART0_INT},
+ Package(){0x0018FFFF, 1, 0, UART1_INT},
+ Package(){0x0018FFFF, 2, 0, UART2_INT},
+ Package(){0x0018FFFF, 3, 0, UART3_INT},
+ Package(){0x0019FFFF, 0, 0, SPI0_INT},
+ Package(){0x0019FFFF, 1, 0, SPI1_INT},
+ Package(){0x0019FFFF, 2, 0, SPI2_INT},
+ Package(){0x001BFFFF, 0, 0, SDCARD_INT},
+ Package(){0x001CFFFF, 0, 0, EMMC_INT},
+ Package(){0x001EFFFF, 0, 0, SDIO_INT},
+ Package(){0x001FFFFF, 1, 0, SMBUS_INT},
+ })
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
new file mode 100644
index 00000000000..ecff59ab1c7
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation
+ */
+
+/* PCIe Ports */
+
+Device (RP01)
+{
+ Name (_ADR, 0x00140000)
+ Name (_DDN, "PCIe-B 0")
+
+ #include "pcie_port.asl"
+}
+
+Device (RP03)
+{
+ Name (_ADR, 0x00130000)
+ Name (_DDN, "PCIe-A 0")
+
+ #include "pcie_port.asl"
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
new file mode 100644
index 00000000000..12a08b4aa89
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation
+ */
+
+/* Include in each PCIe Root Port device */
+
+/* lowest D-state supported by
+ * PCIe root port during S0 state
+ */
+Name (_S0W, 4)
+
+Name (PDST, 0) /* present Detect status */
+
+/* Dynamic Opregion needed to access registers
+ * when the controller is in D3 cold
+ */
+OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
+Field (PX01, AnyAcc, NoLock, Preserve)
+{
+ Offset(0x5A),
+ , 6,
+ PDS, 1, /* 6, Presence detect Change */
+ Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
+ , 2,
+ L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
+ L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
+ Offset(0xF4), /* BLKPLLEN */
+ , 10,
+ BPLL, 1,
+}
+
+OperationRegion (PX02, PCI_Config, 0x338, 0x4)
+Field (PX02, AnyAcc, NoLock, Preserve)
+{
+ , 26,
+ BDQA, 1 /* BLKDQDA */
+}
+
+PowerResource (PXP, 0, 0)
+{
+ /* Define the PowerResource for PCIe slot */
+ Method (_STA, 0, Serialized)
+ {
+ Store (PDS, PDST)
+ If (LEqual (PDS, 1)) {
+ Return (0xf)
+ } Else {
+ Return (0)
+ }
+ }
+
+ Method (_ON, 0, Serialized)
+ {
+ If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+ /* Enter this condition if device
+ * is connected
+ */
+
+ /* De-assert PERST */
+ \_SB.PCI0.PRDA (\PRT0)
+
+ Store (0, BDQA) /* Set BLKDQDA to 0 */
+ Store (0, BPLL) /* Set BLKPLLEN to 0 */
+
+ /* Set L23_Rdy to Detect Transition
+ * (L23R2DT)
+ */
+ Store (1, L23R)
+ Sleep (16)
+ Store (0, Local0)
+
+ /* Delay for transition Detect
+ * and link to train
+ */
+ While (L23R) {
+ If (Lgreater (Local0, 4)) {
+ Break
+ }
+ Sleep (16)
+ Increment (Local0)
+ }
+ } /* End PDS condition check */
+ }
+
+ Method (_OFF, 0, Serialized)
+ {
+ /* Set L23_Rdy Entry Request (L23ER) */
+ If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+ /* enter this condition if device
+ * is connected
+ */
+ Store (1, L23E)
+ Sleep (16)
+ Store (0, Local0)
+ While (L23E) {
+ If (Lgreater (Local0, 4)) {
+ Break
+ }
+ Sleep (16)
+ Increment (Local0)
+ }
+ Store (1, BDQA) /* Set BLKDQDA to 1 */
+ Store (1, BPLL) /* Set BLKPLLEN to 1 */
+
+ /* Assert PERST */
+ \_SB.PCI0.PRAS (\PRT0)
+ } /* End PDS condition check */
+ } /* End of Method_OFF */
+} /* End PXP */
+
+Name(_PR0, Package() { PXP })
+Name(_PR3, Package() { PXP })
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/platform.asl b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl
new file mode 100644
index 00000000000..b631a9fb38a
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ * Copyright (C) 2016 Intel Corp
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <soc/intel/common/acpi/platform.asl>
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 00000000000..4a592833cc0
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ */
+
+#include <asm/arch/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+#define PMIO_LIMIT 0x480
+
+scope (\_SB) {
+ Device (IPC1)
+ {
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR)
+ Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT)
+ Memory32Fixed (ReadWrite, 0x0, 0x4, MINF)
+ IO (Decode16, IOMAP_ACPI_BASE, PMIO_LIMIT,
+      0x04, PMIO_LENGTH)
+ Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+      PMC_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store (PMC_BAR0, IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store (SRAM_BASE_0, SBAS)
+
+ Return (^RBUF)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/scs.asl b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl
new file mode 100644
index 00000000000..7d61861ea1f
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Scope (\_SB.PCI0) {
+ /* 0xD6- is the port address */
+ /* 0x600- is the dynamic clock gating control register offset (GENR) */
+ OperationRegion (SBMM, SystemMemory,
+ Or ( Or (IOMAP_P2SB_BAR,
+ ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
+ Field (SBMM, DWordAcc, NoLock, Preserve)
+ {
+ GENR, 32,
+ Offset (0x08),
+ ,  5, /* bit[5] represents Force Card Detect SD Card */
+ GRR3,  1, /* GPPRVRW3 for SD Card detect Bypass. It's active high */
+ }
+
+ /* SCC power gate control method, this method must be serialized as
+ * multiple device will control the GENR register
+ *
+ * Arguments: (2)
+ * Arg0: 0-AND  1-OR
+ * Arg1: Value
+ */
+ Method (SCPG, 2, Serialized)
+ {
+ if (LEqual(Arg0, 0x1)) {
+ Or (^GENR, Arg1, ^GENR)
+ } ElseIf (LEqual(Arg0, 0x0)){
+ And (^GENR, Arg1, ^GENR)
+ }
+ }
+
+ /* eMMC */
+ Device (SDHA) {
+ Name (_ADR, 0x001C0000)
+ Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+ Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
+
+ /*
+ * Device Specific Method
+ * Arg0 - UUID
+ * Arg1 - Revision
+ * Arg2 - Function Index
+ */
+ Method (_DSM, 4)
+ {
+ If (LEqual (Arg0, ^UUID)) {
+ /*
+ * Function 9: Device Readiness Durations
+ * Returns a package of five integers covering
+ * various device related delays in PCIe Base Spec.
+ */
+ If (LEqual (Arg2, 9)) {
+ /*
+ * Function 9 support for revision 3.
+ * ECN link for function definitions
+ * [https://pcisig.com/sites/default/files/
+ * specification_documents/
+ * ECN_fw_latency_optimization_final.pdf]
+ */
+ If (LEqual (Arg1, 3)) {
+ /*
+ * Integer 0: FW reset time.
+ * Integer 1: FW data link up time.
+ * Integer 2: FW functional level reset
+ * time.
+ * Integer 3: FW D3 hot to D0 time.
+ * Integer 4: FW VF enable time.
+ * set ACPI constant Ones for elements
+ * where overriding the default value
+ * is not desired.
+ */
+ Return (Package (5) {0, Ones, Ones,
+    Ones, Ones})
+ }
+ }
+ }
+ Return (Buffer() { 0x00 })
+ }
+
+ Method (_PS0, 0, NotSerialized)
+ {
+ /* Clear clock gate
+ * Clear bit 6 and 0
+ */
+ ^^SCPG(0,0xFFFFFFBE)
+ /* Sleep 2 ms */
+ Sleep (2)
+ }
+
+ Method (_PS3, 0, NotSerialized)
+ {
+ /* Enable power gate
+ * Restore clock gate
+ * Restore bit 6 and 0
+ */
+ ^^SCPG(1,0x00000041)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0)
+ }
+ }
+ } /* Device (SDHA) */
+
+ /* SD CARD */
+ Device (SDCD)
+ {
+ Name (_ADR, 0x001B0000)
+ Name (_S0W, 4) /* _S0W: S0 Device Wake State */
+ Name (SCD0, 0) /* Store SD_CD DW0 address */
+
+ /* Set the host ownership of sdcard cd during kernel boot */
+ Method (_INI, 0)
+ {
+ /* Check SDCard CD port is valid */
+ If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
+ {
+ /* Store DW0 address of SD_CD */
+ Store (GDW0 (\SCDP, \SCDO), SCD0)
+ /* Get the current SD_CD ownership */
+ Store (\_SB.GHO (\SCDP, \SCDO), Local0)
+ /* Set host ownership as GPIO in HOSTSW_OWN reg */
+ Or (Local0, ShiftLeft (1,  Mod (\SCDO, 32)), Local0)
+ \_SB.SHO (\SCDP, \SCDO, Local0)
+ }
+ }
+
+ Method (_PS0, 0, NotSerialized)
+ {
+ /* Check SDCard CD port is valid */
+ If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) ))
+ {
+ /* Store DW0 into local0 to get rxstate of GPIO */
+ Store (\_SB.GPC0 (SCD0), Local0)
+ /* Extract rxstate [bit 1] of sdcard card detect pin */
+ And (Local0, PAD_CFG0_RX_STATE, Local0)
+ /* If the sdcard is present, rxstate is low.
+ * If sdcard is not present, rxstate is High.
+ * Write the inverted value of rxstate to GRR3.
+ */
+ If (LEqual (Local0, 0)) {
+ Store (1, ^^GRR3)
+ } Else {
+ Store (0, ^^GRR3)
+ }
+ Sleep (2)
+ }
+ }
+
+ Method (_PS3, 0, NotSerialized)
+ {
+ /* Clear GRR3 to Power Gate SD Controller */
+ Store (0, ^^GRR3)
+ }
+
+ Device (CARD)
+ {
+ Name (_ADR, 0x00000008)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (1)
+ }
+ }
+ } /* Device (SDCD) */
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
new file mode 100644
index 00000000000..df2fafb7f67
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <[hidden email]> for Intel Corp.)
+ */
+
+#ifndef _SOC_INT_DEFINE_ASL_
+#define _SOC_INT_DEFINE_ASL_
+
+#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/
+#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/
+#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/
+#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/
+#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/
+#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/
+#define GPIO_BANK_INT 14
+#define NPK_INT 16
+#define PIRQA_INT 16
+#define PIRQB_INT 17
+#define PIRQC_INT 18
+#define SATA_INT 19
+#define GEN_INT 19
+#define PIRQD_INT 19
+#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/
+#define SMBUS_INT 20 /* PIRQE */
+#define CSE_INT 20 /* PIRQE */
+#define IUNIT_INT 21 /* PIRQF */
+#define PIRQF_INT 21
+#define PIRQG_INT 22
+#define PUNIT_INT 24
+#define AUDIO_INT 25
+#define ISH_INT 26
+#define I2C0_INT 27
+#define I2C1_INT 28
+#define I2C2_INT 29
+#define I2C3_INT 30
+#define I2C4_INT 31
+#define I2C5_INT 32
+#define I2C6_INT 33
+#define I2C7_INT 34
+#define SPI0_INT 35
+#define SPI1_INT 36
+#define SPI2_INT 37
+#define UFS_INT 38
+#define EMMC_INT 39
+#define PMC_INT 40
+#define SDIO_INT 42
+#define CNVI_INT 44
+
+#endif /* _SOC_INT_DEFINE_ASL_ */
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
new file mode 100644
index 00000000000..08290194f60
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <[hidden email]> for Intel Corp.)
+ */
+
+#include <p2sb.h>
+#include <asm/arch/gpe.h>
+
+/* PCIE device */
+#include "pcie.asl"
+
+/* LPSS device */
+#include "lpss.asl"
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
+/* GPIO controller */
+#include "gpio.asl"
+
+#include "xhci.asl"
+
+/* LPC */
+#include <asm/acpi/lpc.asl>
+
+/* eMMC */
+#include "scs.asl"
+
+/* PMC IPC controller */
+#include "pmc_ipc.asl"
+
+/* PCI _OSC */
+#include <asm/acpi/pci_osc.asl>
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
new file mode 100644
index 00000000000..6333126c3fd
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+/* XHCI Controller 0:15.0 */
+Device (XHCI) {
+ Name (_ADR, 0x00150000)  /* Device 21, Function 0 */
+
+ Name (_S3D, 3)  /* D3 supported in S3 */
+ Name (_S0W, 3)  /* D3 can wake device in S0 */
+ Name (_S3W, 3)  /* D3 can wake system from S3 */
+
+ /* Declare XHCI GPE status and enable bits are bit 13 */
+ Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 })
+
+ Method (_STA, 0)
+ {
+ Return (0xF)
+ }
+
+ Device (RHUB)
+ {
+ /* Root Hub */
+ Name (_ADR, Zero)
+
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include "xhci_glk_ports.asl"
+#else
+#include "xhci_apl_ports.asl"
+#endif
+ }
+}
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
new file mode 100644
index 00000000000..3ab7d18fc84
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 9) }
+Device (SS02) { Name (_ADR, 10) }
+Device (SS03) { Name (_ADR, 11) }
+Device (SS04) { Name (_ADR, 12) }
+Device (SS05) { Name (_ADR, 13) }
+Device (SS06) { Name (_ADR, 14) }
diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
new file mode 100644
index 00000000000..192267221fc
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC.
+ * Copyright 2019 Intel Corp.
+ */
+
+/* USB2 */
+Device (HS01) { Name (_ADR, 1) }
+Device (HS02) { Name (_ADR, 2) }
+Device (HS03) { Name (_ADR, 3) }
+Device (HS04) { Name (_ADR, 4) }
+Device (HS05) { Name (_ADR, 5) }
+Device (HS06) { Name (_ADR, 6) }
+Device (HS07) { Name (_ADR, 7) }
+Device (HS08) { Name (_ADR, 8) }
+Device (HS09) { Name (_ADR, 9) }
+
+/* USB3 */
+Device (SS01) { Name (_ADR, 10) }
+Device (SS02) { Name (_ADR, 11) }
+Device (SS03) { Name (_ADR, 12) }
+Device (SS04) { Name (_ADR, 13) }
+Device (SS05) { Name (_ADR, 14) }
+Device (SS06) { Name (_ADR, 15) }
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 04/59] x86: acpi: Add DPTF asl files

Simon Glass-3
In reply to this post by Simon Glass-3
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files,
taken from coreboot.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/include/asm/acpi/dptf/charger.asl |  65 +++
 arch/x86/include/asm/acpi/dptf/cpu.asl     | 186 ++++++++
 arch/x86/include/asm/acpi/dptf/dptf.asl    | 121 +++++
 arch/x86/include/asm/acpi/dptf/fan.asl     |  57 +++
 arch/x86/include/asm/acpi/dptf/thermal.asl | 521 +++++++++++++++++++++
 5 files changed, 950 insertions(+)
 create mode 100644 arch/x86/include/asm/acpi/dptf/charger.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/cpu.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/dptf.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/fan.asl
 create mode 100644 arch/x86/include/asm/acpi/dptf/thermal.asl

diff --git a/arch/x86/include/asm/acpi/dptf/charger.asl b/arch/x86/include/asm/acpi/dptf/charger.asl
new file mode 100644
index 00000000000..7f4a7ecd36e
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/charger.asl
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (TCHG)
+{
+ Name (_HID, "INT3403")
+ Name (_UID, 0)
+ Name (PTYP, 0x0B)
+ Name (_STR, Unicode("Battery Charger"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Return charger performance states defined by mainboard */
+ Method (PPSS)
+ {
+ Return (\_SB.CHPS)
+ }
+
+ /* Return maximum charger current limit */
+ Method (PPPC)
+ {
+ /* Convert size of PPSS table to index */
+ Store (SizeOf (\_SB.CHPS), Local0)
+ Decrement (Local0)
+
+ /* Check if charging is disabled (AC removed) */
+ If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) {
+ /* Return last power state */
+ Return (Local0)
+ } Else {
+ /* Return highest power state */
+ Return (0)
+ }
+
+ Return (0)
+ }
+
+ /* Set charger current limit */
+ Method (SPPC, 1)
+ {
+ /* Retrieve Control (index 4) for specified PPSS level */
+ Store (DeRefOf (Index (DeRefOf (Index
+ (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0)
+
+ /* Pass Control value to EC to limit charging */
+ \_SB.PCI0.LPCB.EC0.CHGS (Local0)
+ }
+
+ /* Initialize charger participant */
+ Method (INIT)
+ {
+ /* Disable charge limit */
+ \_SB.PCI0.LPCB.EC0.CHGD ()
+ }
+}
diff --git a/arch/x86/include/asm/acpi/dptf/cpu.asl b/arch/x86/include/asm/acpi/dptf/cpu.asl
new file mode 100644
index 00000000000..f77d3538386
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/cpu.asl
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+External (\_PR.CP00._PSS, PkgObj)
+External (\_PR.CP00._TSS, PkgObj)
+External (\_PR.CP00._TPC, MethodObj)
+External (\_PR.CP00._PTC, PkgObj)
+External (\_PR.CP00._TSD, PkgObj)
+External (\_SB.MPDL, IntObj)
+
+Device (DPTF_CPU_DEVICE)
+{
+ Name(_ADR, DPTF_CPU_ADDR)
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /*
+ * Processor Throttling Controls
+ */
+
+ Method (_TSS)
+ {
+ If (CondRefOf (\_PR.CP00._TSS)) {
+ Return (\_PR.CP00._TSS)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 0, 0, 0, 0, 0 }
+ })
+ }
+ }
+
+ Method (_TPC)
+ {
+ If (CondRefOf (\_PR.CP00._TPC)) {
+ Return (\_PR.CP00._TPC)
+ } Else {
+ Return (0)
+ }
+ }
+
+ Method (_PTC)
+ {
+ If (CondRefOf (\_PR.CP00._PTC)) {
+ Return (\_PR.CP00._PTC)
+ } Else {
+ Return (Package ()
+ {
+ Buffer () { 0 },
+ Buffer () { 0 }
+ })
+ }
+ }
+
+ Method (_TSD)
+ {
+ If (CondRefOf (\_PR.CP00._TSD)) {
+ Return (\_PR.CP00._TSD)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 5, 0, 0, 0, 0 }
+ })
+ }
+ }
+
+ Method (_TDL)
+ {
+ If (CondRefOf (\_PR.CP00._TSS)) {
+ Store (SizeOf (\_PR.CP00._TSS), Local0)
+ Decrement (Local0)
+ Return (Local0)
+ } Else {
+ Return (0)
+ }
+ }
+
+ /*
+ * Processor Performance Control
+ */
+
+ Method (_PPC)
+ {
+ Return (0)
+ }
+
+ Method (SPPC, 1)
+ {
+ Store (Arg0, \PPCM)
+
+ /* Notify OS to re-read _PPC limit on each CPU */
+ \PPCN ()
+ }
+
+ Method (_PSS)
+ {
+ If (CondRefOf (\_PR.CP00._PSS)) {
+ Return (\_PR.CP00._PSS)
+ } Else {
+ Return (Package ()
+ {
+ Package () { 0, 0, 0, 0, 0, 0 }
+ })
+ }
+ }
+
+
+ Method (_PDL)
+ {
+ /* Check for mainboard specific _PDL override */
+ If (CondRefOf (\_SB.MPDL)) {
+ Return (\_SB.MPDL)
+ } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
+ Store (SizeOf (\_PR.CP00._PSS), Local0)
+ Decrement (Local0)
+ Return (Local0)
+ } Else {
+ Return (0)
+ }
+ }
+
+ /* Return PPCC table defined by mainboard */
+ Method (PPCC)
+ {
+ Return (\_SB.MPPC)
+ }
+
+#ifdef DPTF_CPU_CRITICAL
+ Method (_CRT)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL))
+ }
+#endif
+
+#ifdef DPTF_CPU_PASSIVE
+ Method (_PSV)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4))
+ }
+#endif
+}
diff --git a/arch/x86/include/asm/acpi/dptf/dptf.asl b/arch/x86/include/asm/acpi/dptf/dptf.asl
new file mode 100644
index 00000000000..5f958d200b7
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/dptf.asl
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (DPTF)
+{
+ Name (_HID, EISAID ("INT3400"))
+ Name (_UID, 0)
+
+ Name (IDSP, Package()
+ {
+ /* DPPM Passive Policy 1.0 */
+ ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"),
+
+ /* DPPM Critical Policy */
+ ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"),
+
+ /* DPPM Cooling Policy */
+ ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"),
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+ /* DPPM Active Policy */
+ ToUUID ("3A95C389-E4B8-4629-A526-C52C88626BAE"),
+#endif
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /*
+ * Arg0: Buffer containing UUID
+ * Arg1: Integer containing Revision ID of buffer format
+ * Arg2: Integer containing count of entries in Arg3
+ * Arg3: Buffer containing list of DWORD capabilities
+ * Return: Buffer containing list of DWORD capabilities
+ */
+ Method (_OSC, 4, Serialized)
+ {
+ /* Check for Passive Policy UUID */
+ If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) {
+ /* Initialize Thermal Devices */
+ ^TINI ()
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Initialize Charger Device */
+ ^TCHG.INIT ()
+#endif
+ }
+
+ Return (Arg3)
+ }
+
+ /* Priority based _TRT */
+ Name (TRTR, 1)
+
+ Method (_TRT)
+ {
+ Return (\_SB.DTRT)
+ }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+ /* _ART : Active Cooling Relationship Table */
+ Method (_ART)
+ {
+ Return (\_SB.DART)
+ }
+#endif
+
+ /* Convert from Degrees C to 1/10 Kelvin for ACPI */
+ Method (CTOK, 1) {
+ /* 10th of Degrees C */
+ Multiply (Arg0, 10, Local0)
+
+ /* Convert to Kelvin */
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ /* Convert from 1/10 Kelvin to Degrees C for ACPI */
+ Method (KTOC, 1) {
+ If (LLessEqual (Arg0, 2732)) {
+ Return (0)
+ }
+
+ /* Convert to Celsius */
+ Subtract (Arg0, 2732, Local0)
+
+ /* Convert from 10th of degrees */
+ Divide (Local0, 10,, Local0)
+
+ Return (Local0)
+ }
+
+ /* Include Thermal Participants */
+ #include "thermal.asl"
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Include Charger Participant */
+ #include "charger.asl"
+#endif
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+ /* Include Fan Participant */
+ #include "fan.asl"
+#endif
+
+}
+
+Scope (\_SB.PCI0)
+{
+ #include "cpu.asl"
+}
diff --git a/arch/x86/include/asm/acpi/dptf/fan.asl b/arch/x86/include/asm/acpi/dptf/fan.asl
new file mode 100644
index 00000000000..aa4aa129119
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/fan.asl
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+Device (TFN1)
+{
+ Name (_HID, "INT3404")
+ Name (_UID, 0)
+ Name (_STR, Unicode("Fan Control"))
+
+ /* _FIF: Fan Information */
+ Name (_FIF, Package ()
+ {
+ 0, // Revision
+ 1, // Fine Grained Control
+ 2, // Step Size
+ 0 // No Low Speed Notification
+ })
+
+ /* Return Fan Performance States defined by mainboard */
+ Method (_FPS)
+ {
+ Return (\_SB.DFPS)
+ }
+
+ Name (TFST, Package ()
+ {
+ 0, // Revision
+ 0x00, // Control
+ 0x00 // Speed
+ })
+
+ /* _FST: Fan current Status */
+ Method (_FST, 0, Serialized,,PkgObj)
+ {
+ /* Fill in TFST with current control. */
+ Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1))
+ Return (TFST)
+ }
+
+ /* _FSL: Fan Speed Level */
+ Method (_FSL, 1, Serialized)
+ {
+ Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND)
+ }
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One))
+ {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+}
diff --git a/arch/x86/include/asm/acpi/dptf/thermal.asl b/arch/x86/include/asm/acpi/dptf/thermal.asl
new file mode 100644
index 00000000000..4c3c8db8f23
--- /dev/null
+++ b/arch/x86/include/asm/acpi/dptf/thermal.asl
@@ -0,0 +1,521 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ */
+
+/* Thermal Threshold Event Handler */
+#define HAVE_THERM_EVENT_HANDLER
+Method (TEVT, 1, NotSerialized)
+{
+ Store (ToInteger (Arg0), Local0)
+
+#ifdef DPTF_TSR0_SENSOR_ID
+ If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) {
+ Notify (^TSR0, 0x90)
+ }
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+ If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) {
+ Notify (^TSR1, 0x90)
+ }
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+ If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) {
+ Notify (^TSR2, 0x90)
+ }
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+ If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) {
+ Notify (^TSR3, 0x90)
+ }
+#endif
+}
+
+/* Thermal device initialization - Disable Aux Trip Points */
+Method (TINI)
+{
+#ifdef DPTF_TSR0_SENSOR_ID
+ ^TSR0.PATD ()
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+ ^TSR1.PATD ()
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+ ^TSR2.PATD ()
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+ ^TSR3.PATD ()
+#endif
+}
+
+/* Thermal Trip Points Change Event Handler */
+Method (TPET)
+{
+#ifdef DPTF_TSR0_SENSOR_ID
+ Notify (^TSR0, 0x81)
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+ Notify (^TSR1, 0x81)
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+ Notify (^TSR2, 0x81)
+#endif
+#ifdef DPTF_TSR3_SENSOR_ID
+ Notify (^TSR3, 0x81)
+#endif
+}
+
+/*
+ * Method to return trip temperature value depending upon the device mode.
+ * Arg0 --> Value to return when device is in tablet mode
+ * Arg1 --> Value to return when device is not in tablet mode.
+ */
+Method (DTRP, 2, Serialized)
+{
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+ If (LEqual (\_SB.PCI0.LPCB.EC0.RCDP, One)) {
+ Return (CTOK (Arg0))
+ } Else {
+#endif
+ Return (CTOK (Arg1))
+#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES
+ }
+#endif
+}
+
+#ifdef DPTF_TSR0_SENSOR_ID
+
+#ifndef DPTF_TSR0_TABLET_PASSIVE
+#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE
+#endif
+#ifndef DPTF_TSR0_TABLET_CRITICAL
+#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL
+#endif
+
+Device (TSR0)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 1)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR0_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME))
+ Name (GTSH, 20) /* 2 degree hysteresis */
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Method (_PSV)
+ {
+ Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE))
+ }
+
+ Method (_CRT)
+ {
+ Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+
+ /* Disable Aux Trip Point */
+ Method (PATD, 0, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+ }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR0_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC5
+ Method (_AC5)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5))
+ }
+#endif
+#ifdef DPTF_TSR0_ACTIVE_AC6
+ Method (_AC6)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6))
+ }
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR1_SENSOR_ID
+
+#ifndef DPTF_TSR1_TABLET_PASSIVE
+#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE
+#endif
+#ifndef DPTF_TSR1_TABLET_CRITICAL
+#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL
+#endif
+
+Device (TSR1)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 2)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR1_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME))
+ Name (GTSH, 20) /* 2 degree hysteresis */
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Method (_PSV)
+ {
+ Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE))
+ }
+
+ Method (_CRT)
+ {
+ Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+
+ /* Disable Aux Trip Point */
+ Method (PATD, 0, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+ }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC5
+ Method (_AC5)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC5))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC6
+ Method (_AC6)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC6))
+ }
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR2_SENSOR_ID
+
+#ifndef DPTF_TSR2_TABLET_PASSIVE
+#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE
+#endif
+#ifndef DPTF_TSR2_TABLET_CRITICAL
+#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL
+#endif
+
+Device (TSR2)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 3)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR2_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME))
+ Name (GTSH, 20) /* 2 degree hysteresis */
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Method (_PSV)
+ {
+ Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE))
+ }
+
+ Method (_CRT)
+ {
+ Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+
+ /* Disable Aux Trip Point */
+ Method (PATD, 0, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+ }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR2_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC0))
+ }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC1))
+ }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC2))
+ }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC3))
+ }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC4))
+ }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC5
+ Method (_AC5)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC5))
+ }
+#endif
+#ifdef DPTF_TSR2_ACTIVE_AC6
+ Method (_AC6)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC6))
+ }
+#endif
+#endif
+}
+#endif
+
+#ifdef DPTF_TSR3_SENSOR_ID
+
+#ifndef DPTF_TSR3_TABLET_PASSIVE
+#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE
+#endif
+#ifndef DPTF_TSR3_TABLET_CRITICAL
+#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL
+#endif
+
+Device (TSR3)
+{
+ Name (_HID, EISAID ("INT3403"))
+ Name (_UID, 4)
+ Name (PTYP, 0x03)
+ Name (TMPI, DPTF_TSR3_SENSOR_ID)
+ Name (_STR, Unicode (DPTF_TSR3_SENSOR_NAME))
+ Name (GTSH, 20) /* 2 degree hysteresis */
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+ }
+
+ Method (_PSV)
+ {
+ Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE))
+ }
+
+ Method (_CRT)
+ {
+ Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL))
+ }
+
+ Name (PATC, 2)
+
+ /* Set Aux Trip Point */
+ Method (PAT0, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+ }
+
+ /* Set Aux Trip Point */
+ Method (PAT1, 1, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+ }
+
+ /* Disable Aux Trip Point */
+ Method (PATD, 0, Serialized)
+ {
+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)
+ }
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR3_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC0))
+ }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC1))
+ }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC2))
+ }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC3))
+ }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC4))
+ }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC5
+ Method (_AC5)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC5))
+ }
+#endif
+#ifdef DPTF_TSR3_ACTIVE_AC6
+ Method (_AC6)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC6))
+ }
+#endif
+#endif
+}
+#endif
--
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[PATCH v4 05/59] x86: apl: Correct PCIE_ECAM_BASE

Simon Glass-3
In reply to this post by Simon Glass-3
This value is incorrect and causes problems booting Linux. Fix it.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v1)

 board/google/chromebook_coral/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/google/chromebook_coral/Kconfig b/board/google/chromebook_coral/Kconfig
index 27671958e14..53c651c3f9e 100644
--- a/board/google/chromebook_coral/Kconfig
+++ b/board/google/chromebook_coral/Kconfig
@@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
  select BOARD_ROMSIZE_KB_16384
 
 config PCIE_ECAM_BASE
- default 0xf0000000
+ default 0xe0000000
 
 config EARLY_POST_CROS_EC
  bool "Enable early post to Chrome OS EC"
--
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[PATCH v4 06/59] x86: Add a config for the systemagent PCIEX regions size

Simon Glass-3
In reply to this post by Simon Glass-3
Add a way to specify the required size for this region. This is used when
generating ACPI tables.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/Kconfig                | 18 ++++++++++++++++++
 arch/x86/cpu/apollolake/Kconfig |  1 +
 2 files changed, 19 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 76276c60274..256a1100bd3 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -976,4 +976,22 @@ config TPL_ACPI_GPE
 
   See https://queue.acm.org/blogposting.cfm?id=18977 for more info
 
+config SA_PCIEX_LENGTH
+ hex
+ default 0x10000000 if (PCIEX_LENGTH_256MB)
+ default 0x8000000 if (PCIEX_LENGTH_128MB)
+ default 0x4000000 if (PCIEX_LENGTH_64MB)
+ default 0x10000000
+ help
+  This option allows you to select length of PCIEX region.
+
+config PCIEX_LENGTH_256MB
+ bool
+
+config PCIEX_LENGTH_128MB
+ bool
+
+config PCIEX_LENGTH_64MB
+ bool
+
 endmenu
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 99d4e105c25..37d6289ee41 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -13,6 +13,7 @@ config INTEL_APOLLOLAKE
  select TPL_X86_TSC_TIMER_NATIVE
  select SPL_PCH_SUPPORT
  select TPL_PCH_SUPPORT
+ select PCIEX_LENGTH_256MB
  select PCH_SUPPORT
  select P2SB
  select SMP_AP_WORK
--
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[PATCH v4 07/59] x86: Add a common global NVS structure

Simon Glass-3
In reply to this post by Simon Glass-3
Add the definition of this structure common to Intel devices. It includes
some optional Chrome OS pieces which are used when vboot is integrated.

Drop the APL version as it is basically the same.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

Changes in v1:
- Use this file in APL

 .../include/asm/arch-apollolake/global_nvs.h  | 23 +---------
 arch/x86/include/asm/intel_gnvs.h             | 43 +++++++++++++++++++
 2 files changed, 44 insertions(+), 22 deletions(-)
 create mode 100644 arch/x86/include/asm/intel_gnvs.h

diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h
index fe62194b02e..ef8eb228dbe 100644
--- a/arch/x86/include/asm/arch-apollolake/global_nvs.h
+++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h
@@ -10,27 +10,6 @@
 #ifndef _GLOBAL_NVS_H_
 #define _GLOBAL_NVS_H_
 
-struct __packed acpi_global_nvs {
- /* Miscellaneous */
- u8 pcnt; /* 0x00 - Processor Count */
- u8 ppcm; /* 0x01 - Max PPC State */
- u8 lids; /* 0x02 - LID State */
- u8 pwrs; /* 0x03 - AC Power State */
- u8 dpte; /* 0x04 - Enable DPTF */
- u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */
- u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
- u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
- u64 nhla; /* 0x19 - 0x20 - NHLT Address */
- u32 nhll; /* 0x21 - 0x24 - NHLT Length */
- u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
- u8 scdp; /* 0x29 - SD_CD GPIO portid */
- u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
- u8 uior; /* 0x2b - UART debug controller init on S3 resume */
- u8 ecps; /* 0x2c - SGX Enabled status */
- u64 emna; /* 0x2d - 0x34 EPC base address */
- u64 elng; /* 0x35 - 0x3c EPC Length */
- u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
- u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
-};
+#include <asm/intel_gnvs.h>
 
 #endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h
new file mode 100644
index 00000000000..e2d479d4f32
--- /dev/null
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * Taken from coreboot intelblocks/nvs.h
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _INTEL_GNVS_H_
+#define _INTEL_GNVS_H_
+
+struct __packed acpi_global_nvs {
+ /* Miscellaneous */
+ u8 pcnt; /* 0x00 - Processor Count */
+ u8 ppcm; /* 0x01 - Max PPC State */
+ u8 lids; /* 0x02 - LID State */
+ u8 pwrs; /* 0x03 - AC Power State */
+ u8 dpte; /* 0x04 - Enable DPTF */
+ u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
+ u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
+ u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
+ u64 nhla; /* 0x19 - 0x20 - NHLT Address */
+ u32 nhll; /* 0x21 - 0x24 - NHLT Length */
+ u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
+ u8 scdp; /* 0x29 - SD_CD GPIO portid */
+ u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
+ u8 uior; /* 0x2b - UART debug controller init on S3 resume */
+ u8 ecps; /* 0x2c - SGX Enabled status */
+ u64 emna; /* 0x2d - 0x34 EPC base address */
+ u64 elng; /* 0x35 - 0x3C EPC Length */
+ u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
+#ifdef CONFIG_CHROMEOS
+ /* ChromeOS-specific (0x100 - 0xfff) */
+ struct chromeos_acpi chromeos;
+#else
+ u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
+#endif
+};
+#ifdef CONFIG_CHROMEOS
+check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+#endif
+
+#endif /* _INTEL_GNVS_H_ */
--
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[PATCH v4 08/59] x86: acpi: Support external GNVS tables

Simon Glass-3
In reply to this post by Simon Glass-3
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.

Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/Kconfig                       |  7 ++++++
 arch/x86/cpu/apollolake/Kconfig        |  1 +
 arch/x86/include/asm/acpi/global_nvs.h |  3 +++
 arch/x86/lib/acpi_table.c              | 35 +++++++++++++++++---------
 4 files changed, 34 insertions(+), 12 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 256a1100bd3..680f26f1b8e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -788,6 +788,13 @@ config GENERATE_ACPI_TABLE
   by the operating system. It defines platform-independent interfaces
   for configuration and power management monitoring.
 
+config ACPI_GNVS_EXTERNAL
+ bool
+ help
+  Put the GNVS (Global Non-Volatile Sleeping) table separate from the
+  DSDT and add a pointer to the table from the DSDT. This allows
+  U-Boot to better control the address of the GNVS.
+
 endmenu
 
 config HAVE_ACPI_RESUME
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 37d6289ee41..16ac2b3f504 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -17,6 +17,7 @@ config INTEL_APOLLOLAKE
  select PCH_SUPPORT
  select P2SB
  select SMP_AP_WORK
+ select ACPI_GNVS_EXTERNAL
  imply ENABLE_MRC_CACHE
  imply AHCI_PCI
  imply SCSI
diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h
index d56d35ca533..a552cf6374f 100644
--- a/arch/x86/include/asm/acpi/global_nvs.h
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -11,6 +11,9 @@
  * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
  * to declare the GNVS OperationRegion, as well as write_acpi_tables()
  * for the GNVS address runtime fix up.
+ *
+ * If using CONFIG_ACPI_GNVS_EXTERNAL, we don't need to locate the GNVS in
+ * DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused.
  */
 #define ACPI_GNVS_ADDR 0xdeadbeef
 #define ACPI_GNVS_SIZE 0x100
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index c445aa68703..36ef3e5f0b7 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -430,17 +430,31 @@ ulong write_acpi_tables(ulong start_addr)
        dsdt->length - sizeof(struct acpi_table_header));
 
  acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header));
+ dsdt->length = ctx->current - (void *)dsdt;
+ acpi_align(ctx);
 
- /* Pack GNVS into the ACPI table area */
- for (i = 0; i < dsdt->length; i++) {
- u32 *gnvs = (u32 *)((u32)dsdt + i);
- if (*gnvs == ACPI_GNVS_ADDR) {
- ulong addr = (ulong)map_to_sysmem(ctx->current);
-
- debug("Fix up global NVS in DSDT to %#08lx\n", addr);
- *gnvs = addr;
- break;
+ if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
+ /* Pack GNVS into the ACPI table area */
+ for (i = 0; i < dsdt->length; i++) {
+ u32 *gnvs = (u32 *)((u32)dsdt + i);
+
+ if (*gnvs == ACPI_GNVS_ADDR) {
+ *gnvs = map_to_sysmem(ctx->current);
+ debug("Fix up global NVS in DSDT to %#08x\n",
+      *gnvs);
+ break;
+ }
  }
+
+ /*
+ * Fill in platform-specific global NVS variables. If this fails
+ * we cannot return the error but this should only happen while
+ * debugging.
+ */
+ addr = acpi_create_gnvs(ctx->current);
+ if (IS_ERR_VALUE(addr))
+ printf("Error: Gailed to create GNVS\n");
+ acpi_inc_align(ctx, sizeof(struct acpi_global_nvs));
  }
 
  /*
@@ -448,12 +462,9 @@ ulong write_acpi_tables(ulong start_addr)
  * the GNVS address. Set the checksum to zero since it is part of the
  * region being checksummed.
  */
- dsdt->length = ctx->current - (void *)dsdt;
  dsdt->checksum = 0;
  dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length);
 
- acpi_align(ctx);
-
  /*
  * Fill in platform-specific global NVS variables. If this fails we
  * cannot return the error but this should only happen while debugging.
--
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[PATCH v4 09/59] x86: acpi: Expand the GNVS

Simon Glass-3
In reply to this post by Simon Glass-3
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/include/asm/acpi/global_nvs.h | 2 +-
 arch/x86/include/asm/intel_gnvs.h      | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h
index a552cf6374f..46383629cc5 100644
--- a/arch/x86/include/asm/acpi/global_nvs.h
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -16,6 +16,6 @@
  * DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused.
  */
 #define ACPI_GNVS_ADDR 0xdeadbeef
-#define ACPI_GNVS_SIZE 0x100
+#define ACPI_GNVS_SIZE 0x1000
 
 #endif /* _ACPI_GNVS_H_ */
diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h
index e2d479d4f32..c1e9d65779f 100644
--- a/arch/x86/include/asm/intel_gnvs.h
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -36,6 +36,7 @@ struct __packed acpi_global_nvs {
  u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
 #endif
 };
+
 #ifdef CONFIG_CHROMEOS
 check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 #endif
--
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[PATCH v4 10/59] x86: coral: Add ACPI tables for coral

Simon Glass-3
In reply to this post by Simon Glass-3
This device has a large set of ACPI tables. Bring these in from coreboot
so that full functionality is available (apart from SMI).

Signed-off-by: Simon Glass <[hidden email]>
---

Changes in v4:
- Add logging when writinge NHLT
- Change table version to 3

Changes in v1:
- Add NHLT audio support
- Capitalise ACPI_OPS_PTR
- Use OEM_TABLE_ID instead of ACPI_TABLE_CREATOR

 board/google/chromebook_coral/Makefile        |   1 +
 .../chromebook_coral/baseboard_dptf.asl       |  71 +++++++++
 board/google/chromebook_coral/coral.c         | 136 ++++++++++++++++++
 board/google/chromebook_coral/dsdt.asl        |  60 ++++++++
 .../google/chromebook_coral/variant_dptf.asl  |   6 +
 board/google/chromebook_coral/variant_ec.h    |  75 ++++++++++
 board/google/chromebook_coral/variant_gpio.h  |  63 ++++++++
 include/bloblist.h                            |   5 +
 8 files changed, 417 insertions(+)
 create mode 100644 board/google/chromebook_coral/baseboard_dptf.asl
 create mode 100644 board/google/chromebook_coral/dsdt.asl
 create mode 100644 board/google/chromebook_coral/variant_dptf.asl
 create mode 100644 board/google/chromebook_coral/variant_ec.h
 create mode 100644 board/google/chromebook_coral/variant_gpio.h

diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile
index 6a27ce3da1b..f7a0ca6cc0a 100644
--- a/board/google/chromebook_coral/Makefile
+++ b/board/google/chromebook_coral/Makefile
@@ -3,3 +3,4 @@
 # Copyright 2019 Google LLC
 
 obj-y += coral.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/google/chromebook_coral/baseboard_dptf.asl b/board/google/chromebook_coral/baseboard_dptf.asl
new file mode 100644
index 00000000000..5da963a6705
--- /dev/null
+++ b/board/google/chromebook_coral/baseboard_dptf.asl
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ */
+
+#define DPTF_CPU_PASSIVE 95
+#define DPTF_CPU_CRITICAL 105
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 120
+#define DPTF_TSR0_CRITICAL 125
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 46
+#define DPTF_TSR1_CRITICAL 75
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 58
+#define DPTF_TSR2_CRITICAL 90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c
index 12d4fe63cb0..f5ae48290f4 100644
--- a/board/google/chromebook_coral/coral.c
+++ b/board/google/chromebook_coral/coral.c
@@ -4,7 +4,24 @@
  */
 
 #include <common.h>
+#include <bloblist.h>
 #include <command.h>
+#include <dm.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <asm-generic/gpio.h>
+#include <asm/acpi_nhlt.h>
+#include <asm/intel_gnvs.h>
+#include <asm/intel_pinctrl.h>
+#include <dm/acpi.h>
+#include "variant_gpio.h"
+
+struct cros_gpio_info {
+ const char *linux_name;
+ enum cros_gpio_t type;
+ int gpio_num;
+ int flags;
+};
 
 int arch_misc_init(void)
 {
@@ -18,3 +35,122 @@ int board_run_command(const char *cmdline)
 
  return 0;
 }
+
+int chromeos_get_gpio(const struct udevice *dev, const char *prop,
+      enum cros_gpio_t type, struct cros_gpio_info *info)
+{
+ struct udevice *pinctrl;
+ struct gpio_desc desc;
+ int ret;
+
+ ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0);
+ if (ret == -ENOTBLK)
+ info->gpio_num = CROS_GPIO_VIRTUAL;
+ else if (ret)
+ return log_msg_ret("gpio", ret);
+ else
+ info->gpio_num = desc.offset;
+ info->linux_name = dev_read_string(desc.dev, "linux-name");
+ if (!info->linux_name)
+ return log_msg_ret("linux-name", -ENOENT);
+ info->type = type;
+ /* Get ACPI pin from GPIO library if available */
+ if (info->gpio_num != CROS_GPIO_VIRTUAL) {
+ pinctrl = dev_get_parent(desc.dev);
+ info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl,
+    info->gpio_num);
+ }
+ info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW :
+ CROS_GPIO_ACTIVE_HIGH;
+
+ return 0;
+}
+
+static int chromeos_acpi_gpio_generate(const struct udevice *dev,
+       struct acpi_ctx *ctx)
+{
+ struct cros_gpio_info info[3];
+ int count, i;
+ int ret;
+
+ count = 3;
+ ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]);
+ if (ret)
+ return log_msg_ret("rec", ret);
+ ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP,
+ &info[1]);
+ if (ret)
+ return log_msg_ret("rec", ret);
+ ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE,
+ &info[2]);
+ if (ret)
+ return log_msg_ret("rec", ret);
+ acpigen_write_scope(ctx, "\\");
+ acpigen_write_name(ctx, "OIPG");
+ acpigen_write_package(ctx, count);
+ for (i = 0; i < count; i++) {
+ acpigen_write_package(ctx, 4);
+ acpigen_write_integer(ctx, info[i].type);
+ acpigen_write_integer(ctx, info[i].flags);
+ acpigen_write_integer(ctx, info[i].gpio_num);
+ acpigen_write_string(ctx, info[i].linux_name);
+ acpigen_pop_len(ctx);
+ }
+
+ acpigen_pop_len(ctx);
+ acpigen_pop_len(ctx);
+
+ return 0;
+}
+
+static int coral_write_acpi_tables(const struct udevice *dev,
+   struct acpi_ctx *ctx)
+{
+ struct acpi_global_nvs *gnvs;
+ struct nhlt *nhlt;
+ const char *oem_id = "coral";
+ const char *oem_table_id = "coral";
+ u32 oem_revision = 3;
+ int ret;
+
+ gnvs = bloblist_find(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs));
+ if (!gnvs)
+ return log_msg_ret("bloblist", -ENOENT);
+
+ nhlt = nhlt_init();
+ if (!nhlt)
+ return -ENOMEM;
+
+ log_debug("Setting up NHLT\n");
+ ret = acpi_setup_nhlt(ctx, nhlt);
+ if (ret)
+ return log_msg_ret("setup", ret);
+
+ /* Update NHLT GNVS Data */
+ gnvs->nhla = (uintptr_t)ctx->current;
+ gnvs->nhll = nhlt_current_size(nhlt);
+
+ ret = nhlt_serialise_oem_overrides(ctx, nhlt, oem_id, oem_table_id,
+   oem_revision);
+ if (ret)
+ return log_msg_ret("serialise", ret);
+
+ return 0;
+}
+
+struct acpi_ops coral_acpi_ops = {
+ .write_tables = coral_write_acpi_tables,
+ .inject_dsdt = chromeos_acpi_gpio_generate,
+};
+
+static const struct udevice_id coral_ids[] = {
+ { .compatible = "google,coral" },
+ { }
+};
+
+U_BOOT_DRIVER(coral_drv) = {
+ .name = "coral",
+ .id = UCLASS_BOARD,
+ .of_match = coral_ids,
+ ACPI_OPS_PTR(&coral_acpi_ops)
+};
diff --git a/board/google/chromebook_coral/dsdt.asl b/board/google/chromebook_coral/dsdt.asl
new file mode 100644
index 00000000000..b51e0b05005
--- /dev/null
+++ b/board/google/chromebook_coral/dsdt.asl
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "variant_ec.h"
+#include "variant_gpio.h"
+#include <acpi/acpi_table.h>
+#include <asm/acpi/global_nvs.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ OEM_TABLE_ID,
+ 0x20110725 // OEM revision
+)
+{
+ /* global NVS and variables */
+ #include <asm/arch/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <asm/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <asm/arch/acpi/northbridge.asl>
+ #include <asm/arch/acpi/southbridge.asl>
+ #include <asm/arch/acpi/pch_hda.asl>
+ }
+ }
+
+ /* Chrome OS specific */
+ #include <asm/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <asm/acpi/sleepstates.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <asm/acpi/cros_ec/superio.asl>
+ /* ACPI code for EC functions */
+ #include <asm/acpi/cros_ec/ec.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+ #include "variant_dptf.asl"
+ /* Include soc specific DPTF changes */
+ #include <asm/arch/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+ #include <asm/acpi/dptf/dptf.asl>
+ }
+}
diff --git a/board/google/chromebook_coral/variant_dptf.asl b/board/google/chromebook_coral/variant_dptf.asl
new file mode 100644
index 00000000000..943ebeaac26
--- /dev/null
+++ b/board/google/chromebook_coral/variant_dptf.asl
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+#include "baseboard_dptf.asl"
diff --git a/board/google/chromebook_coral/variant_ec.h b/board/google/chromebook_coral/variant_ec.h
new file mode 100644
index 00000000000..7d5e1a674cf
--- /dev/null
+++ b/board/google/chromebook_coral/variant_ec.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+/*
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#include "variant_gpio.h"
+#include <ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif
diff --git a/board/google/chromebook_coral/variant_gpio.h b/board/google/chromebook_coral/variant_gpio.h
new file mode 100644
index 00000000000..f516d88be5c
--- /dev/null
+++ b/board/google/chromebook_coral/variant_gpio.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <asm/arch/gpio.h>
+#include <ec_commands.h>
+
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI GPE0_DW1_11
+
+/* EC SMI */
+#define EC_SMI_GPI GPIO_49
+
+/*
+ * On lidopen/lidclose GPIO_22 from North Community gets toggled and
+ * is used in _PRW to wake up device from sleep. GPIO_22 maps to
+ * group GPIO_GPE_N_31_0 and the pad is configured as SCI with
+ * EDGE_SINGLE and INVERT.
+ */
+#define GPE_EC_WAKE GPE0_DW1_22
+
+/* Write Protect and indication if EC is in RW code. */
+#define GPIO_PCH_WP GPIO_75
+#define GPIO_EC_IN_RW GPIO_41
+/* Determine if board is in final shipping mode. */
+#define GPIO_SHIP_MODE GPIO_10
+
+/*  Memory SKU GPIOs. */
+#define MEM_CONFIG3 GPIO_45
+#define MEM_CONFIG2 GPIO_38
+#define MEM_CONFIG1 GPIO_102
+#define MEM_CONFIG0 GPIO_101
+
+/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */
+#define DMIC_CONFIG_PIN GPIO_17
+
+#ifndef __ASSEMBLY__
+
+enum cros_gpio_t {
+ CROS_GPIO_REC = 1, /* Recovery */
+
+ /* Developer; * deprecated (chromium:942901) */
+ CROS_GPIO_DEPRECATED_DEV = 2,
+ CROS_GPIO_WP = 3, /* Write Protect */
+ CROS_GPIO_PE = 4, /* Phase enforcement for final product */
+
+ CROS_GPIO_ACTIVE_LOW = 0,
+ CROS_GPIO_ACTIVE_HIGH = 1,
+
+ CROS_GPIO_VIRTUAL = -1,
+};
+#endif
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/include/bloblist.h b/include/bloblist.h
index 609ac421d66..bbe0a35d5a2 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -27,6 +27,11 @@ enum bloblist_tag_t {
  BLOBLISTT_SPL_HANDOFF, /* Hand-off info from SPL */
  BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */
  BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */
+ /*
+ * Advanced Configuration and Power Interface Global Non-Volatile
+ * Sleeping table. This forms part of the ACPI tables passed to Linux.
+ */
+ BLOBLISTT_ACPI_GNVS,
 };
 
 /**
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 11/59] acpi: Add support for writing a _PRW

Simon Glass-3
In reply to this post by Simon Glass-3
A 'Power Resource for Wake' list the resources a device depends on for
wake. Add a function to generate this.

Signed-off-by: Simon Glass <[hidden email]>
---

Changes in v4:
- Correct comment for dm_test_acpi_write_prw()

 include/acpi/acpigen.h | 10 ++++++++++
 lib/acpi/acpigen.c     | 10 ++++++++++
 test/dm/acpigen.c      | 30 ++++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index 228ac9c404b..a9b70123c0a 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -563,4 +563,14 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val,
        const char *dw0_read, const char *dw0_write,
        struct acpi_gpio *gpio, bool enable);
 
+/**
+ * acpigen_write_prw() - Write a power resource for wake (_PRW)
+ *
+ * @ctx: ACPI context pointer
+ * @wake: GPE that wakes up the device
+ * @level: Deepest power system sleeping state that can be entered while still
+ * providing wake functionality
+ */
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
+
 #endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index c609ef4daa4..527de89b1e1 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -426,6 +426,16 @@ void acpigen_write_register_resource(struct acpi_ctx *ctx,
  acpigen_write_resourcetemplate_footer(ctx);
 }
 
+void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level)
+{
+ /* Name (_PRW, Package () { wake, level } */
+ acpigen_write_name(ctx, "_PRW");
+ acpigen_write_package(ctx, 2);
+ acpigen_write_integer(ctx, wake);
+ acpigen_write_integer(ctx, level);
+ acpigen_pop_len(ctx);
+}
+
 /*
  * ToUUID(uuid)
  *
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 1b2767e732d..1dc064ffbcf 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1097,3 +1097,33 @@ static int dm_test_acpi_write_name(struct unit_test_state *uts)
  return 0;
 }
 DM_TEST(dm_test_acpi_write_name, 0);
+
+/* Test emitting a _PRW component */
+static int dm_test_acpi_write_prw(struct unit_test_state *uts)
+{
+ struct acpi_ctx *ctx;
+ u8 *ptr;
+
+ ut_assertok(alloc_context(&ctx));
+
+ ptr = acpigen_get_current(ctx);
+ acpigen_write_prw(ctx, 5, 3);
+ ut_asserteq(NAME_OP, *ptr++);
+
+ ut_asserteq_strn("_PRW", (char *)ptr);
+ ptr += 4;
+ ut_asserteq(PACKAGE_OP, *ptr++);
+ ut_asserteq(8, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(2, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(5, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(3, *ptr++);
+ ut_asserteq_ptr(ptr, ctx->current);
+
+ free_context(&ctx);
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_write_prw, 0);
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 12/59] acpi: Add support for conditions and return values

Simon Glass-3
In reply to this post by Simon Glass-3
Add functions to support generating ACPI code for condition checks and
return values.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 include/acpi/acpigen.h | 93 ++++++++++++++++++++++++++++++++++++++++++
 lib/acpi/acpigen.c     | 68 ++++++++++++++++++++++++++++++
 test/dm/acpigen.c      | 91 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 252 insertions(+)

diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index a9b70123c0a..fa9409e3528 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -52,12 +52,24 @@ enum {
  LOCAL5_OP = 0x65,
  LOCAL6_OP = 0x66,
  LOCAL7_OP = 0x67,
+ ARG0_OP = 0x68,
+ ARG1_OP = 0x69,
+ ARG2_OP = 0x6a,
+ ARG3_OP = 0x6b,
+ ARG4_OP = 0x6c,
+ ARG5_OP = 0x6d,
+ ARG6_OP = 0x6e,
  STORE_OP = 0x70,
  AND_OP = 0x7b,
  OR_OP = 0x7d,
  NOT_OP = 0x80,
  DEVICE_OP = 0x82,
  POWER_RES_OP = 0x84,
+ LEQUAL_OP = 0x93,
+ TO_BUFFER_OP = 0x96,
+ TO_INTEGER_OP = 0x99,
+ IF_OP = 0xa0,
+ ELSE_OP = 0xa1,
  RETURN_OP = 0xa4,
 };
 
@@ -573,4 +585,85 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val,
  */
 void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level);
 
+/**
+ * acpigen_write_if() - Write an If block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_if(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_if_lequal_op_int() - Write comparison between op and integer
+ *
+ * Generates ACPI code for checking if operand1 and operand2 are equal
+ *
+ * If (Lequal (op, val))
+ *
+ * @ctx: ACPI context pointer
+ * @op: Operand to check
+ * @val: Value to check against
+ */
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val);
+
+/**
+ * acpigen_write_else() - Write an Ef block
+ *
+ * This requires a call to acpigen_pop_len() to complete the block
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_else(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_to_buffer() - Write a ToBuffer operation
+ *
+ * E.g.: to generate: ToBuffer (Arg0, Local0)
+ * use acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_to_integer() - Write a ToInteger operation
+ *
+ * E.g.: to generate: ToInteger (Arg0, Local0)
+ * use acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP)
+ *
+ * @ctx: ACPI context pointer
+ * @src: Source argument
+ * @dst: Destination argument
+ */
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst);
+
+/**
+ * acpigen_write_return_byte_buffer() - Write a return of a byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arr: Array of bytes to return
+ * @size: Number of bytes
+ */
+void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr,
+      size_t size);
+
+/**
+ * acpigen_write_return_singleton_buffer() - Write a return of a 1-byte buffer
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg);
+
+/**
+ * acpigen_write_return_byte() - Write a return of a byte
+ *
+ * @ctx: ACPI context pointer
+ * @arg: Byte to return
+ */
+void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg);
+
 #endif
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index 527de89b1e1..2518bf83dda 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -541,6 +541,74 @@ void acpigen_write_debug_string(struct acpi_ctx *ctx, const char *str)
  acpigen_emit_ext_op(ctx, DEBUG_OP);
 }
 
+void acpigen_write_if(struct acpi_ctx *ctx)
+{
+ acpigen_emit_byte(ctx, IF_OP);
+ acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val)
+{
+ acpigen_write_if(ctx);
+ acpigen_emit_byte(ctx, LEQUAL_OP);
+ acpigen_emit_byte(ctx, op);
+ acpigen_write_integer(ctx, val);
+}
+
+void acpigen_write_else(struct acpi_ctx *ctx)
+{
+ acpigen_emit_byte(ctx, ELSE_OP);
+ acpigen_write_len_f(ctx);
+}
+
+void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+ acpigen_emit_byte(ctx, TO_BUFFER_OP);
+ acpigen_emit_byte(ctx, src);
+ acpigen_emit_byte(ctx, dst);
+}
+
+void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst)
+{
+ acpigen_emit_byte(ctx, TO_INTEGER_OP);
+ acpigen_emit_byte(ctx, src);
+ acpigen_emit_byte(ctx, dst);
+}
+
+void acpigen_write_byte_buffer(struct acpi_ctx *ctx, u8 *arr, size_t size)
+{
+ size_t i;
+
+ acpigen_emit_byte(ctx, BUFFER_OP);
+ acpigen_write_len_f(ctx);
+ acpigen_write_integer(ctx, size);
+
+ for (i = 0; i < size; i++)
+ acpigen_emit_byte(ctx, arr[i]);
+
+ acpigen_pop_len(ctx);
+}
+
+void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr,
+      size_t size)
+{
+ acpigen_emit_byte(ctx, RETURN_OP);
+ acpigen_write_byte_buffer(ctx, arr, size);
+}
+
+void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg)
+{
+ u8 buf = arg;
+
+ acpigen_write_return_byte_buffer(ctx, &buf, 1);
+}
+
+void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg)
+{
+ acpigen_emit_byte(ctx, RETURN_OP);
+ acpigen_write_byte(ctx, arg);
+}
+
 /**
  * acpigen_get_dw0_in_local5() - Generate code to put dw0 cfg0 in local5
  *
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index 1dc064ffbcf..cce19f11209 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -1127,3 +1127,94 @@ static int dm_test_acpi_write_prw(struct unit_test_state *uts)
  return 0;
 }
 DM_TEST(dm_test_acpi_write_prw, 0);
+
+/* Test emitting writing conditionals */
+static int dm_test_acpi_write_cond(struct unit_test_state *uts)
+{
+ struct acpi_ctx *ctx;
+ u8 *ptr;
+
+ ut_assertok(alloc_context(&ctx));
+
+ ptr = acpigen_get_current(ctx);
+ acpigen_write_if(ctx);
+ acpigen_pop_len(ctx);
+ ut_asserteq(IF_OP, *ptr++);
+ ut_asserteq(3, acpi_test_get_length(ptr));
+ ptr += 3;
+
+ acpigen_write_else(ctx);
+ acpigen_pop_len(ctx);
+ ut_asserteq(ELSE_OP, *ptr++);
+ ut_asserteq(3, acpi_test_get_length(ptr));
+ ptr += 3;
+
+ acpigen_write_if_lequal_op_int(ctx, LOCAL1_OP, 5);
+ acpigen_pop_len(ctx);
+ ut_asserteq(IF_OP, *ptr++);
+ ut_asserteq(7, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(LEQUAL_OP, *ptr++);
+ ut_asserteq(LOCAL1_OP, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(5, *ptr++);
+
+ ut_asserteq_ptr(ptr, ctx->current);
+
+ free_context(&ctx);
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_write_cond, 0);
+
+/* Test emitting writing return values and ToBuffer/ToInteger */
+static int dm_test_acpi_write_return(struct unit_test_state *uts)
+{
+ int len = sizeof(TEST_STRING);
+ struct acpi_ctx *ctx;
+ u8 *ptr;
+
+ ut_assertok(alloc_context(&ctx));
+
+ ptr = acpigen_get_current(ctx);
+ acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP);
+ ut_asserteq(TO_BUFFER_OP, *ptr++);
+ ut_asserteq(ARG0_OP, *ptr++);
+ ut_asserteq(LOCAL0_OP, *ptr++);
+
+ acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP);
+ ut_asserteq(TO_INTEGER_OP, *ptr++);
+ ut_asserteq(ARG0_OP, *ptr++);
+ ut_asserteq(LOCAL0_OP, *ptr++);
+
+ acpigen_write_return_byte_buffer(ctx, (u8 *)TEST_STRING, len);
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ut_asserteq(5 + len, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(len, *ptr++);
+ ut_asserteq_mem(TEST_STRING, ptr, len);
+ ptr += len;
+
+ acpigen_write_return_singleton_buffer(ctx, 123);
+ len = 1;
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ut_asserteq(4 + len, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(ONE_OP, *ptr++);
+ ut_asserteq(123, *ptr++);
+
+ acpigen_write_return_byte(ctx, 43);
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(43, *ptr++);
+
+ ut_asserteq_ptr(ptr, ctx->current);
+
+ free_context(&ctx);
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_write_return, 0);
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 13/59] acpi: Support generating a multi-function _DSM for devices

Simon Glass-3
In reply to this post by Simon Glass-3
Add a function to generate ACPI code for a _DSM method for a device.
This includes functions for starting and ending each part of the _DSM.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 include/acpi/acpi_device.h |  14 +++++
 include/acpi/acpigen.h     |  99 +++++++++++++++++++++++++++++
 lib/acpi/acpi_device.c     |  43 +++++++++++++
 lib/acpi/acpigen.c         |  54 ++++++++++++++++
 test/dm/acpigen.c          | 126 +++++++++++++++++++++++++++++++++++++
 5 files changed, 336 insertions(+)

diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index 11461e168d3..a5b12217820 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -28,6 +28,9 @@ struct udevice;
 /* Length of a full path to an ACPI device */
 #define ACPI_PATH_MAX 30
 
+/* UUID for an I2C _DSM method */
+#define ACPI_DSM_I2C_HID_UUID "3cdff6f7-4267-4555-ad05-b30a3d8938de"
+
 /* Values that can be returned for ACPI device _STA method */
 enum acpi_dev_status {
  ACPI_DSTATUS_PRESENT = BIT(0),
@@ -319,6 +322,17 @@ int acpi_device_write_gpio_desc(struct acpi_ctx *ctx,
 int acpi_device_write_interrupt_or_gpio(struct acpi_ctx *ctx,
  struct udevice *dev, const char *prop);
 
+/**
+ * acpi_device_write_dsm_i2c_hid() - Write a device-specific method for HID
+ *
+ * This writes a DSM for an I2C Human-Interface Device based on the config
+ * provided
+ *
+ * @hid_desc_reg_offset: HID register offset
+ */
+int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
+  int hid_desc_reg_offset);
+
 /**
  * acpi_device_write_i2c_dev() - Write an I2C device to ACPI
  *
diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h
index fa9409e3528..34b3115bc9c 100644
--- a/include/acpi/acpigen.h
+++ b/include/acpi/acpigen.h
@@ -666,4 +666,103 @@ void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg);
  */
 void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg);
 
+/**
+ * acpigen_write_dsm_start() - Start a _DSM method
+ *
+ * Generate ACPI AML code to start the _DSM method.
+ *
+ * The functions need to be called in the correct sequence as below.
+ *
+ * Within the <generate-code-here> region, Local0 and Local1 must be are left
+ * untouched, but Local2-Local7 can be used
+ *
+ * Arguments passed into _DSM method:
+ * Arg0 = UUID
+ * Arg1 = Revision
+ * Arg2 = Function index
+ * Arg3 = Function-specific arguments
+ *
+ * AML code generated looks like this:
+ * Method (_DSM, 4, Serialized) {   -- acpigen_write_dsm_start)
+ * ToBuffer (Arg0, Local0)
+ * If (LEqual (Local0, ToUUID(uuid))) {  -- acpigen_write_dsm_uuid_start
+ * ToInteger (Arg2, Local1)
+ * If (LEqual (Local1, 0)) {  -- acpigen_write_dsm_uuid_start_cond
+ * <generate-code-here>
+ * }                          -- acpigen_write_dsm_uuid_end_cond
+ * ...
+ * If (LEqual (Local1, n)) {  -- acpigen_write_dsm_uuid_start_cond
+ * <generate-code-here>
+ * }                          -- acpigen_write_dsm_uuid_end_cond
+ * Return (Buffer (One) { 0x0 })
+ * }                                  -- acpigen_write_dsm_uuid_end
+ * ...
+ * If (LEqual (Local0, ToUUID(uuidn))) {
+ * ...
+ * }
+ * Return (Buffer (One) { 0x0 })  -- acpigen_write_dsm_end
+ * }
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_start(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_start() - Start a new UUID block
+ *
+ * This starts generation of code to handle a particular UUID:
+ *
+ * If (LEqual (Local0, ToUUID(uuid))) {
+ * ToInteger (Arg2, Local1)
+ *
+ * @ctx: ACPI context pointer
+ */
+int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid);
+
+/**
+ * acpigen_write_dsm_uuid_start_cond() - Start a new condition block
+ *
+ * This starts generation of condition-checking code to handle a particular
+ * function:
+ *
+ * If (LEqual (Local1, i))
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq);
+
+/**
+ * acpigen_write_dsm_uuid_end_cond() - Start a new condition block
+ *
+ * This ends generation of condition-checking code to handle a particular
+ * function:
+ *
+ * }
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_uuid_end() - End a UUID block
+ *
+ * This ends generation of code to handle a particular UUID:
+ *
+ * Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx);
+
+/**
+ * acpigen_write_dsm_end() - End a _DSM method
+ *
+ * This ends generates of the _DSM block:
+ *
+ * Return (Buffer (One) { 0x0 })
+ *
+ * @ctx: ACPI context pointer
+ */
+void acpigen_write_dsm_end(struct acpi_ctx *ctx);
+
 #endif
diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c
index 3c75b6d9629..8248664a10a 100644
--- a/lib/acpi/acpi_device.c
+++ b/lib/acpi/acpi_device.c
@@ -487,6 +487,49 @@ int acpi_device_add_power_res(struct acpi_ctx *ctx, u32 tx_state_val,
  return 0;
 }
 
+int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx,
+  int hid_desc_reg_offset)
+{
+ int ret;
+
+ acpigen_write_dsm_start(ctx);
+ ret = acpigen_write_dsm_uuid_start(ctx, ACPI_DSM_I2C_HID_UUID);
+ if (ret)
+ return log_ret(ret);
+
+ acpigen_write_dsm_uuid_start_cond(ctx, 0);
+ /* ToInteger (Arg1, Local2) */
+ acpigen_write_to_integer(ctx, ARG1_OP, LOCAL2_OP);
+ /* If (LEqual (Local2, 0x0)) */
+ acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x0);
+ /*   Return (Buffer (One) { 0x1f }) */
+ acpigen_write_return_singleton_buffer(ctx, 0x1f);
+ acpigen_pop_len(ctx); /* Pop : If */
+ /* Else */
+ acpigen_write_else(ctx);
+ /*   If (LEqual (Local2, 0x1)) */
+ acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x1);
+ /*     Return (Buffer (One) { 0x3f }) */
+ acpigen_write_return_singleton_buffer(ctx, 0x3f);
+ acpigen_pop_len(ctx); /* Pop : If */
+ /*   Else */
+ acpigen_write_else(ctx);
+ /*     Return (Buffer (One) { 0x0 }) */
+ acpigen_write_return_singleton_buffer(ctx, 0x0);
+ acpigen_pop_len(ctx); /* Pop : Else */
+ acpigen_pop_len(ctx); /* Pop : Else */
+ acpigen_write_dsm_uuid_end_cond(ctx);
+
+ acpigen_write_dsm_uuid_start_cond(ctx, 1);
+ acpigen_write_return_byte(ctx, hid_desc_reg_offset);
+ acpigen_write_dsm_uuid_end_cond(ctx);
+
+ acpigen_write_dsm_uuid_end(ctx);
+ acpigen_write_dsm_end(ctx);
+
+ return 0;
+}
+
 /* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBus() */
 static void acpi_device_write_i2c(struct acpi_ctx *ctx,
   const struct acpi_i2c *i2c)
diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c
index 2518bf83dda..d859f378413 100644
--- a/lib/acpi/acpigen.c
+++ b/lib/acpi/acpigen.c
@@ -609,6 +609,60 @@ void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg)
  acpigen_write_byte(ctx, arg);
 }
 
+void acpigen_write_dsm_start(struct acpi_ctx *ctx)
+{
+ /* Method (_DSM, 4, Serialized) */
+ acpigen_write_method_serialized(ctx, "_DSM", 4);
+
+ /* ToBuffer (Arg0, Local0) */
+ acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP);
+}
+
+int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid)
+{
+ int ret;
+
+ /* If (LEqual (Local0, ToUUID(uuid))) */
+ acpigen_write_if(ctx);
+ acpigen_emit_byte(ctx, LEQUAL_OP);
+ acpigen_emit_byte(ctx, LOCAL0_OP);
+ ret = acpigen_write_uuid(ctx, uuid);
+ if (ret)
+ return log_msg_ret("uuid", ret);
+
+ /* ToInteger (Arg2, Local1) */
+ acpigen_write_to_integer(ctx, ARG2_OP, LOCAL1_OP);
+
+ return 0;
+}
+
+void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq)
+{
+ /* If (LEqual (Local1, i)) */
+ acpigen_write_if_lequal_op_int(ctx, LOCAL1_OP, seq);
+}
+
+void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx)
+{
+ acpigen_pop_len(ctx); /* If */
+}
+
+void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx)
+{
+ /* Default case: Return (Buffer (One) { 0x0 }) */
+ acpigen_write_return_singleton_buffer(ctx, 0x0);
+
+ acpigen_pop_len(ctx); /* If (LEqual (Local0, ToUUID(uuid))) */
+}
+
+void acpigen_write_dsm_end(struct acpi_ctx *ctx)
+{
+ /* Return (Buffer (One) { 0x0 }) */
+ acpigen_write_return_singleton_buffer(ctx, 0x0);
+
+ acpigen_pop_len(ctx); /* Method _DSM */
+}
+
 /**
  * acpigen_get_dw0_in_local5() - Generate code to put dw0 cfg0 in local5
  *
diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c
index cce19f11209..381fcb97022 100644
--- a/test/dm/acpigen.c
+++ b/test/dm/acpigen.c
@@ -10,6 +10,7 @@
 #include <dm.h>
 #include <irq.h>
 #include <malloc.h>
+#include <uuid.h>
 #include <acpi/acpigen.h>
 #include <acpi/acpi_device.h>
 #include <acpi/acpi_table.h>
@@ -1218,3 +1219,128 @@ static int dm_test_acpi_write_return(struct unit_test_state *uts)
  return 0;
 }
 DM_TEST(dm_test_acpi_write_return, 0);
+
+/* Test emitting a DSM for an I2C HID */
+static int dm_test_acpi_write_i2c_dsm(struct unit_test_state *uts)
+{
+ char uuid_str[UUID_STR_LEN + 1];
+ const int reg_offset = 0x20;
+ struct acpi_ctx *ctx;
+ u8 *ptr;
+
+ ut_assertok(alloc_context(&ctx));
+
+ ptr = acpigen_get_current(ctx);
+ ut_assertok(acpi_device_write_dsm_i2c_hid(ctx, reg_offset));
+
+ /* acpigen_write_dsm_start() */
+ ut_asserteq(METHOD_OP, *ptr++);
+ ut_asserteq(0x78, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq_strn("_DSM", (char *)ptr);
+ ptr += 4;
+ ut_asserteq(ACPI_METHOD_SERIALIZED_MASK | 4, *ptr++);
+
+ ut_asserteq(TO_BUFFER_OP, *ptr++);
+ ut_asserteq(ARG0_OP, *ptr++);
+ ut_asserteq(LOCAL0_OP, *ptr++);
+
+ /* acpigen_write_dsm_uuid_start() */
+ ut_asserteq(IF_OP, *ptr++);
+ ut_asserteq(0x65, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(LEQUAL_OP, *ptr++);
+ ut_asserteq(LOCAL0_OP, *ptr++);
+
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ut_asserteq(UUID_BIN_LEN + 6, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(WORD_PREFIX, *ptr++);
+ ut_asserteq(UUID_BIN_LEN, get_unaligned((u16 *)ptr));
+ ptr += 2;
+ uuid_bin_to_str(ptr, uuid_str, UUID_STR_FORMAT_GUID);
+ ut_asserteq_str(ACPI_DSM_I2C_HID_UUID, uuid_str);
+ ptr += UUID_BIN_LEN;
+
+ ut_asserteq(TO_INTEGER_OP, *ptr++);
+ ut_asserteq(ARG2_OP, *ptr++);
+ ut_asserteq(LOCAL1_OP, *ptr++);
+
+ /* acpigen_write_dsm_uuid_start_cond() */
+ ut_asserteq(IF_OP, *ptr++);
+ ut_asserteq(0x34, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(LEQUAL_OP, *ptr++);
+ ut_asserteq(LOCAL1_OP, *ptr++);
+ ut_asserteq(ZERO_OP, *ptr++);
+
+ /*
+ * See code from acpi_device_write_dsm_i2c_hid(). We don't check every
+ * piece
+ */
+ ut_asserteq(TO_INTEGER_OP, *ptr++);
+ ut_asserteq(ARG1_OP, *ptr++);
+ ut_asserteq(LOCAL2_OP, *ptr++);
+
+ ut_asserteq(IF_OP, *ptr++);
+ ut_asserteq(0xd, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(LEQUAL_OP, *ptr++);
+ ut_asserteq(LOCAL2_OP, *ptr++);
+ ut_asserteq(ZERO_OP, *ptr++); /* function 0 */
+
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ptr += 5;
+
+ ut_asserteq(ELSE_OP, *ptr++);
+ ptr += 3;
+
+ ut_asserteq(IF_OP, *ptr++);
+ ut_asserteq(0xd, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(LEQUAL_OP, *ptr++);
+ ut_asserteq(LOCAL2_OP, *ptr++);
+ ut_asserteq(ONE_OP, *ptr++);
+
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ptr += 5;
+
+ ut_asserteq(ELSE_OP, *ptr++);
+ ptr += 3;
+
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ptr += 5;
+
+ /* acpigen_write_dsm_uuid_start_cond() */
+ ut_asserteq(IF_OP, *ptr++);
+ ut_asserteq(9, acpi_test_get_length(ptr));
+ ptr += 3;
+ ut_asserteq(LEQUAL_OP, *ptr++);
+ ut_asserteq(LOCAL1_OP, *ptr++);
+ ut_asserteq(ONE_OP, *ptr++); /* function 1 */
+
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BYTE_PREFIX, *ptr++);
+ ut_asserteq(reg_offset, *ptr++);
+
+ /* acpigen_write_dsm_uuid_end() */
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ptr += 5;
+
+ /* acpigen_write_dsm_end */
+ ut_asserteq(RETURN_OP, *ptr++);
+ ut_asserteq(BUFFER_OP, *ptr++);
+ ptr += 5;
+
+ ut_asserteq_ptr(ptr, ctx->current);
+
+ free_context(&ctx);
+
+ return 0;
+}
+DM_TEST(dm_test_acpi_write_i2c_dsm, 0);
+
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 14/59] dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()

Simon Glass-3
In reply to this post by Simon Glass-3
This function currently accepts the IRQ-polarity type. Fix it to use the
GPIO type instead.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v2)

Changes in v2:
- add new patch to fix polarity type in acpi_dp_add_gpio()

 drivers/sound/max98357a.c | 2 +-
 include/acpi/acpi_dp.h    | 2 +-
 lib/acpi/acpi_dp.c        | 4 ++--
 test/dm/acpi_dp.c         | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c
index 841bc6ef682..827262d235c 100644
--- a/drivers/sound/max98357a.c
+++ b/drivers/sound/max98357a.c
@@ -81,7 +81,7 @@ static int max98357a_acpi_fill_ssdt(const struct udevice *dev,
  dp = acpi_dp_new_table("_DSD");
  acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0,
  priv->sdmode_gpio.flags & GPIOD_ACTIVE_LOW ?
- ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH);
+ ACPI_GPIO_ACTIVE_LOW : ACPI_GPIO_ACTIVE_HIGH);
  acpi_dp_add_integer(dp, "sdmode-delay",
     dev_read_u32_default(dev, "sdmode-delay", 0));
  acpi_dp_write(ctx, dp);
diff --git a/include/acpi/acpi_dp.h b/include/acpi/acpi_dp.h
index 0b514bce59c..5e539b1d218 100644
--- a/include/acpi/acpi_dp.h
+++ b/include/acpi/acpi_dp.h
@@ -221,7 +221,7 @@ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name,
  */
 struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name,
  const char *ref, int index, int pin,
- enum acpi_irq_polarity polarity);
+ enum acpi_gpio_polarity polarity);
 
 /**
  * acpi_dp_write() - Write Device Property hierarchy and clean up resources
diff --git a/lib/acpi/acpi_dp.c b/lib/acpi/acpi_dp.c
index 579cab47715..7e3e3259d8d 100644
--- a/lib/acpi/acpi_dp.c
+++ b/lib/acpi/acpi_dp.c
@@ -324,7 +324,7 @@ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name,
 
 struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name,
  const char *ref, int index, int pin,
- enum acpi_irq_polarity polarity)
+ enum acpi_gpio_polarity polarity)
 {
  struct acpi_dp *gpio;
 
@@ -336,7 +336,7 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name,
  if (!acpi_dp_add_reference(gpio, NULL, ref) ||
     !acpi_dp_add_integer(gpio, NULL, index) ||
     !acpi_dp_add_integer(gpio, NULL, pin) ||
-    !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_IRQ_ACTIVE_LOW))
+    !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_GPIO_ACTIVE_LOW))
  return NULL;
 
  if (!acpi_dp_add_array(dp, gpio))
diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c
index e0fa61263c8..44bcabda6bc 100644
--- a/test/dm/acpi_dp.c
+++ b/test/dm/acpi_dp.c
@@ -398,9 +398,9 @@ static int dm_test_acpi_dp_gpio(struct unit_test_state *uts)
 
  /* Try a few different parameters */
  ut_assertnonnull(acpi_dp_add_gpio(dp, "reset", TEST_REF, 0x23, 0x24,
-  ACPI_IRQ_ACTIVE_HIGH));
+  ACPI_GPIO_ACTIVE_HIGH));
  ut_assertnonnull(acpi_dp_add_gpio(dp, "allow", TEST_REF, 0, 0,
-  ACPI_IRQ_ACTIVE_LOW));
+  ACPI_GPIO_ACTIVE_LOW));
 
  ptr = acpigen_get_current(ctx);
  ut_assertok(acpi_dp_write(ctx, dp));
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 15/59] x86: link: Allow more space for U-Boot

Simon Glass-3
In reply to this post by Simon Glass-3
The extra ACPI code increases U-Boot above it current size limit. Move
the start earlier to provide space.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Bin Meng <[hidden email]>
---

(no changes since v2)

Changes in v2:
- Add new patch to allow more space for U-Boot on link

 configs/chromebook_link_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 82485a5a3f7..c59a7f3c994 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -1,5 +1,5 @@
 CONFIG_X86=y
-CONFIG_SYS_TEXT_BASE=0xFFF00000
+CONFIG_SYS_TEXT_BASE=0xFFEF0000
 CONFIG_SYS_MALLOC_F_LEN=0x2400
 CONFIG_NR_DRAM_BANKS=8
 CONFIG_ENV_SIZE=0x1000
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 16/59] i2c: Add a generic driver to generate ACPI info

Simon Glass-3
In reply to this post by Simon Glass-3
Many I2C devices produce roughly the same ACPI data with just things like
the GPIO/interrupt information being different.

This can be handled by a generic driver along with some information in the
device tree.

Add a generic i2c driver for this purpose.

Signed-off-by: Simon Glass <[hidden email]>
Reviewed-by: Heiko Schocher <[hidden email]>
---

(no changes since v2)

Changes in v2:
- Fix incorrect space in enable-off-delay-ms

Changes in v1:
- Adjust implementation to match new ACPI GPIO generation
- Capitalise ACPI_OPS_PTR
- Rename acpi-probed to linux,probed
- Support hid-over-i2c separately as well
- Use acpi,ddn instead of acpi,desc
- Use updated acpi_device_write_dsm_i2c_hid() function

 doc/device-tree-bindings/i2c/generic-acpi.txt |  42 ++++
 drivers/i2c/Makefile                          |   3 +
 drivers/i2c/acpi_i2c.c                        | 226 ++++++++++++++++++
 drivers/i2c/acpi_i2c.h                        |  15 ++
 drivers/i2c/i2c-uclass.c                      |  17 ++
 include/acpi/acpi_device.h                    |  55 +++++
 include/i2c.h                                 |  23 ++
 7 files changed, 381 insertions(+)
 create mode 100644 doc/device-tree-bindings/i2c/generic-acpi.txt
 create mode 100644 drivers/i2c/acpi_i2c.c
 create mode 100644 drivers/i2c/acpi_i2c.h

diff --git a/doc/device-tree-bindings/i2c/generic-acpi.txt b/doc/device-tree-bindings/i2c/generic-acpi.txt
new file mode 100644
index 00000000000..3510a71b570
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/generic-acpi.txt
@@ -0,0 +1,42 @@
+I2C generic device
+==================
+
+This is used only to generate ACPI tables for an I2C device.
+
+Required properties :
+
+ - compatible : "i2c-chip";
+ - reg : I2C chip address
+ - acpi,hid : HID name for the device
+
+Optional properies in addition to device.txt:
+
+ - reset-gpios : GPIO used to assert reset to the device
+ - irq-gpios : GPIO used for interrupt (if Interrupt is not used)
+ - stop-gpios : GPIO used to stop the device
+ - interrupts-extended : Interrupt to use for the device
+ - reset-delay-ms : Delay after de-asserting reset, in ms
+ - reset-off-delay-ms : Delay after asserting reset (during power off)
+ - enable-delay-ms : Delay after asserting enable
+ - enable-off-delay-ms : Delay after de-asserting enable (during power off)
+ - stop-delay-ms : Delay after de-aserting stop
+ - stop-off-delay-ms : Delay after asserting stop (during power off)
+ - hid-descr-addr : HID register offset (for Human Interface Devices)
+
+Example
+-------
+
+ elan-touchscreen@10 {
+ compatible = "i2c-chip";
+ reg = <0x10>;
+ acpi,hid = "ELAN0001";
+ acpi,ddn = "ELAN Touchscreen";
+ interrupts-extended = <&acpi_gpe GPIO_21_IRQ
+ IRQ_TYPE_EDGE_FALLING>;
+ linux,probed;
+ reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
+ reset-delay-ms = <20>;
+ enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
+ enable-delay-ms = <1>;
+ acpi,has-power-resource;
+ };
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index f7b27864488..bd248cbf52b 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -3,6 +3,9 @@
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, [hidden email].
 obj-$(CONFIG_DM_I2C) += i2c-uclass.o
+ifdef CONFIG_ACPIGEN
+obj-$(CONFIG_DM_I2C) += acpi_i2c.o
+endif
 obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o
 obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
 obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
diff --git a/drivers/i2c/acpi_i2c.c b/drivers/i2c/acpi_i2c.c
new file mode 100644
index 00000000000..57d29683cbf
--- /dev/null
+++ b/drivers/i2c/acpi_i2c.c
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <log.h>
+#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_dp.h>
+#ifdef CONFIG_X86
+#include <asm/intel_pinctrl_defs.h>
+#endif
+#include <asm-generic/gpio.h>
+#include <dm/acpi.h>
+
+static bool acpi_i2c_add_gpios_to_crs(struct acpi_i2c_priv *priv)
+{
+ /*
+ * Return false if:
+ * 1. Request to explicitly disable export of GPIOs in CRS, or
+ * 2. Both reset and enable GPIOs are not provided.
+ */
+ if (priv->disable_gpio_export_in_crs ||
+    (!dm_gpio_is_valid(&priv->reset_gpio) &&
+     !dm_gpio_is_valid(&priv->enable_gpio)))
+ return false;
+
+ return true;
+}
+
+static int acpi_i2c_write_gpio(struct acpi_ctx *ctx, struct gpio_desc *gpio,
+       int *curindex)
+{
+ int ret;
+
+ if (!dm_gpio_is_valid(gpio))
+ return -ENOENT;
+
+ acpi_device_write_gpio_desc(ctx, gpio);
+ ret = *curindex;
+ (*curindex)++;
+
+ return ret;
+}
+
+int acpi_i2c_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
+{
+ int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1;
+ enum i2c_device_t type = dev_get_driver_data(dev);
+ struct acpi_i2c_priv *priv = dev_get_priv(dev);
+ struct acpi_dp *dsd = NULL;
+ char scope[ACPI_PATH_MAX];
+ char name[ACPI_NAME_MAX];
+ int tx_state_val;
+ int curindex = 0;
+ int ret;
+
+#ifdef CONFIG_X86
+ tx_state_val = PAD_CFG0_TX_STATE;
+#elif defined(CONFIG_SANDBOX)
+ tx_state_val = BIT(7);  /* test value */
+#else
+#error "Not supported on this architecture"
+#endif
+ ret = acpi_get_name(dev, name);
+ if (ret)
+ return log_msg_ret("name", ret);
+ ret = acpi_device_scope(dev, scope, sizeof(scope));
+ if (ret)
+ return log_msg_ret("scope", ret);
+
+ /* Device */
+ acpigen_write_scope(ctx, scope);
+ acpigen_write_device(ctx, name);
+ acpigen_write_name_string(ctx, "_HID", priv->hid);
+ if (type == I2C_DEVICE_HID_OVER_I2C)
+ acpigen_write_name_string(ctx, "_CID", "PNP0C50");
+ acpigen_write_name_integer(ctx, "_UID", priv->uid);
+ acpigen_write_name_string(ctx, "_DDN", priv->desc);
+ acpigen_write_sta(ctx, acpi_device_status(dev));
+
+ /* Resources */
+ acpigen_write_name(ctx, "_CRS");
+ acpigen_write_resourcetemplate_header(ctx);
+ acpi_device_write_i2c_dev(ctx, dev);
+
+ /* Use either Interrupt() or GpioInt() */
+ if (dm_gpio_is_valid(&priv->irq_gpio)) {
+ irq_gpio_index = acpi_i2c_write_gpio(ctx, &priv->irq_gpio,
+     &curindex);
+ } else {
+ ret = acpi_device_write_interrupt_irq(ctx, &priv->irq);
+ if (ret < 0)
+ return log_msg_ret("irq", ret);
+ }
+
+ if (acpi_i2c_add_gpios_to_crs(priv)) {
+ reset_gpio_index = acpi_i2c_write_gpio(ctx, &priv->reset_gpio,
+       &curindex);
+ enable_gpio_index = acpi_i2c_write_gpio(ctx, &priv->enable_gpio,
+ &curindex);
+ }
+ acpigen_write_resourcetemplate_footer(ctx);
+
+ /* Wake capabilities */
+ if (priv->wake) {
+ acpigen_write_name_integer(ctx, "_S0W", 4);
+ acpigen_write_prw(ctx, priv->wake, 3);
+ }
+
+ /* DSD */
+ if (priv->probed || priv->property_count || priv->compat_string ||
+    reset_gpio_index >= 0 || enable_gpio_index >= 0 ||
+    irq_gpio_index >= 0) {
+ char path[ACPI_PATH_MAX];
+
+ ret = acpi_device_path(dev, path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+
+ dsd = acpi_dp_new_table("_DSD");
+ if (priv->compat_string)
+ acpi_dp_add_string(dsd, "compatible",
+   priv->compat_string);
+ if (priv->probed)
+ acpi_dp_add_integer(dsd, "linux,probed", 1);
+ if (irq_gpio_index >= 0)
+ acpi_dp_add_gpio(dsd, "irq-gpios", path,
+ irq_gpio_index, 0,
+ priv->irq_gpio.flags &
+ GPIOD_ACTIVE_LOW ?
+ ACPI_GPIO_ACTIVE_LOW : 0);
+ if (reset_gpio_index >= 0)
+ acpi_dp_add_gpio(dsd, "reset-gpios", path,
+ reset_gpio_index, 0,
+ priv->reset_gpio.flags &
+ GPIOD_ACTIVE_LOW ?
+ ACPI_GPIO_ACTIVE_LOW : 0);
+ if (enable_gpio_index >= 0)
+ acpi_dp_add_gpio(dsd, "enable-gpios", path,
+ enable_gpio_index, 0,
+ priv->enable_gpio.flags &
+ GPIOD_ACTIVE_LOW ?
+ ACPI_GPIO_ACTIVE_LOW : 0);
+ /* Generic property list is not supported */
+ acpi_dp_write(ctx, dsd);
+ }
+
+ /* Power Resource */
+ if (priv->has_power_resource) {
+ ret = acpi_device_add_power_res(ctx, tx_state_val,
+ "\\_SB.GPC0", "\\_SB.SPC0",
+ &priv->reset_gpio, priv->reset_delay_ms,
+ priv->reset_off_delay_ms, &priv->enable_gpio,
+ priv->enable_delay_ms, priv->enable_off_delay_ms,
+ &priv->stop_gpio, priv->stop_delay_ms,
+ priv->stop_off_delay_ms);
+ if (ret)
+ return log_msg_ret("power", ret);
+ }
+ if (priv->hid_desc_reg_offset) {
+ ret = acpi_device_write_dsm_i2c_hid(ctx,
+    priv->hid_desc_reg_offset);
+ if (ret)
+ return log_msg_ret("dsm", ret);
+ }
+
+ acpigen_pop_len(ctx); /* Device */
+ acpigen_pop_len(ctx); /* Scope */
+
+ return 0;
+}
+
+int acpi_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct acpi_i2c_priv *priv = dev_get_priv(dev);
+
+ gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
+     GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable_gpio,
+     GPIOD_IS_OUT);
+ gpio_request_by_name(dev, "irq-gpios", 0, &priv->irq_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "stop-gpios", 0, &priv->stop_gpio,
+     GPIOD_IS_OUT);
+ irq_get_by_index(dev, 0, &priv->irq);
+ priv->hid = dev_read_string(dev, "acpi,hid");
+ if (!priv->hid)
+ return log_msg_ret("hid", -EINVAL);
+ dev_read_u32(dev, "acpi,uid", &priv->uid);
+ priv->desc = dev_read_string(dev, "acpi,ddn");
+ dev_read_u32(dev, "acpi,wake", &priv->wake);
+ priv->probed = dev_read_bool(dev, "linux,probed");
+ priv->compat_string = dev_read_string(dev, "acpi,compatible");
+ priv->has_power_resource = dev_read_bool(dev,
+ "acpi,has-power-resource");
+ dev_read_u32(dev, "hid-descr-addr", &priv->hid_desc_reg_offset);
+ dev_read_u32(dev, "reset-delay-ms", &priv->reset_delay_ms);
+ dev_read_u32(dev, "reset-off-delay-ms", &priv->reset_off_delay_ms);
+ dev_read_u32(dev, "enable-delay-ms", &priv->enable_delay_ms);
+ dev_read_u32(dev, "enable-off-delay-ms", &priv->enable_off_delay_ms);
+ dev_read_u32(dev, "stop-delay-ms", &priv->stop_delay_ms);
+ dev_read_u32(dev, "stop-off-delay-ms", &priv->stop_off_delay_ms);
+
+ return 0;
+}
+
+/* Use name specified in priv or build one from I2C address */
+static int acpi_i2c_get_name(const struct udevice *dev, char *out_name)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ struct acpi_i2c_priv *priv = dev_get_priv(dev);
+
+ snprintf(out_name, ACPI_NAME_MAX,
+ priv->hid_desc_reg_offset ? "H%03X" : "D%03X",
+ chip->chip_addr);
+
+ return 0;
+}
+
+struct acpi_ops acpi_i2c_ops = {
+ .fill_ssdt = acpi_i2c_fill_ssdt,
+ .get_name = acpi_i2c_get_name,
+};
diff --git a/drivers/i2c/acpi_i2c.h b/drivers/i2c/acpi_i2c.h
new file mode 100644
index 00000000000..1f4be296016
--- /dev/null
+++ b/drivers/i2c/acpi_i2c.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ACPI_I2C_H
+#define __ACPI_I2C_H
+
+#include <dm/acpi.h>
+
+extern struct acpi_ops acpi_i2c_ops;
+
+int acpi_i2c_ofdata_to_platdata(struct udevice *dev);
+
+#endif
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 2373aa2ea4c..5c4626b0442 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -9,6 +9,8 @@
 #include <i2c.h>
 #include <log.h>
 #include <malloc.h>
+#include <acpi/acpi_device.h>
+#include <dm/acpi.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
 #include <dm/pinctrl.h>
@@ -16,6 +18,7 @@
 #include <asm/gpio.h>
 #endif
 #include <linux/delay.h>
+#include "acpi_i2c.h"
 
 #define I2C_MAX_OFFSET_LEN 4
 
@@ -749,7 +752,21 @@ UCLASS_DRIVER(i2c_generic) = {
  .name = "i2c_generic",
 };
 
+static const struct udevice_id generic_chip_i2c_ids[] = {
+ { .compatible = "i2c-chip", .data = I2C_DEVICE_GENERIC },
+#if CONFIG_IS_ENABLED(ACPIGEN)
+ { .compatible = "hid-over-i2c", .data = I2C_DEVICE_HID_OVER_I2C },
+#endif
+ { }
+};
+
 U_BOOT_DRIVER(i2c_generic_chip_drv) = {
  .name = "i2c_generic_chip_drv",
  .id = UCLASS_I2C_GENERIC,
+ .of_match = generic_chip_i2c_ids,
+#if CONFIG_IS_ENABLED(ACPIGEN)
+ .ofdata_to_platdata = acpi_i2c_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct acpi_i2c_priv),
+#endif
+ ACPI_OPS_PTR(&acpi_i2c_ops)
 };
diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h
index a5b12217820..1b838fcb857 100644
--- a/include/acpi/acpi_device.h
+++ b/include/acpi/acpi_device.h
@@ -10,7 +10,9 @@
 #define __ACPI_DEVICE_H
 
 #include <i2c.h>
+#include <irq.h>
 #include <spi.h>
+#include <asm-generic/gpio.h>
 #include <linux/bitops.h>
 
 struct acpi_ctx;
@@ -235,6 +237,59 @@ struct acpi_spi {
  const char *resource;
 };
 
+/**
+ * struct acpi_i2c_priv - Information read from device tree
+ *
+ * This is used by devices which want to specify various pieces of ACPI
+ * information, including power control. It allows a generic function to
+ * generate the information for ACPI, based on device-tree properties.
+ *
+ * @disable_gpio_export_in_crs: Don't export GPIOs in the CRS
+ * @reset_gpio: GPIO used to assert reset to the device
+ * @enable_gpio: GPIO used to enable the device
+ * @stop_gpio: GPIO used to stop the device
+ * @irq_gpio: GPIO used for interrupt (if @irq is not used)
+ * @irq: IRQ used for interrupt (if @irq_gpio is not used)
+ * @hid: _HID value for device (required)
+ * @uid: _UID value for device
+ * @desc: _DDN value for device
+ * @wake: Wake event, e.g. GPE0_DW1_15; 0 if none
+ * @property_count: Number of other DSD properties (currently always 0)
+ * @probed: true set set 'linux,probed' property
+ * @compat_string: Device tree compatible string to report through ACPI
+ * @has_power_resource: true if this device has a power resource
+ * @reset_delay_ms: Delay after de-asserting reset, in ms
+ * @reset_off_delay_ms: Delay after asserting reset (during power off)
+ * @enable_delay_ms: Delay after asserting enable
+ * @enable_off_delay_ms: Delay after de-asserting enable (during power off)
+ * @stop_delay_ms: Delay after de-aserting stop
+ * @stop_off_delay_ms: Delay after asserting stop (during power off)
+ * @hid_desc_reg_offset: HID register offset (for Human Interface Devices)
+ */
+struct acpi_i2c_priv {
+ bool disable_gpio_export_in_crs;
+ struct gpio_desc reset_gpio;
+ struct gpio_desc enable_gpio;
+ struct gpio_desc irq_gpio;
+ struct gpio_desc stop_gpio;
+ struct irq irq;
+ const char *hid;
+ u32 uid;
+ const char *desc;
+ u32 wake;
+ u32 property_count;
+ bool probed;
+ const char *compat_string;
+ bool has_power_resource;
+ u32 reset_delay_ms;
+ u32 reset_off_delay_ms;
+ u32 enable_delay_ms;
+ u32 enable_off_delay_ms;
+ u32 stop_delay_ms;
+ u32 stop_off_delay_ms;
+ u32 hid_desc_reg_offset;
+};
+
 /**
  * acpi_device_path() - Get the full path to an ACPI device
  *
diff --git a/include/i2c.h b/include/i2c.h
index 1d792db454a..880aa8032b7 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -58,6 +58,12 @@ enum i2c_address_mode {
  I2C_MODE_10_BIT
 };
 
+/** enum i2c_device_t - Types of I2C devices, used for compatible strings */
+enum i2c_device_t {
+ I2C_DEVICE_GENERIC,
+ I2C_DEVICE_HID_OVER_I2C,
+};
+
 struct udevice;
 /**
  * struct dm_i2c_chip - information about an i2c chip
@@ -558,6 +564,23 @@ int i2c_emul_find(struct udevice *dev, struct udevice **emulp);
  */
 struct udevice *i2c_emul_get_device(struct udevice *emul);
 
+/* ACPI operations for generic I2C devices */
+extern struct acpi_ops i2c_acpi_ops;
+
+/**
+ * acpi_i2c_ofdata_to_platdata() - Read properties intended for ACPI
+ *
+ * This reads the generic I2C properties from the device tree, so that these
+ * can be used to create ACPI information for the device.
+ *
+ * See the i2c/generic-acpi.txt binding file for information about the
+ * properties.
+ *
+ * @dev: I2C device to process
+ * @return 0 if OK, -EINVAL if acpi,hid is not present
+ */
+int acpi_i2c_ofdata_to_platdata(struct udevice *dev);
+
 #ifndef CONFIG_DM_I2C
 
 /*
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 17/59] x86: Add wake sources for the acpi_gpe driver

Simon Glass-3
In reply to this post by Simon Glass-3
Some devices can wake the system from sleep, e.g opening the lid on a
clamshell or moving a USB mouse.

Add a wake to specify this for USB devices and add the settings for Apollo
Lake.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

 arch/x86/include/asm/arch-apollolake/gpe.h  | 135 ++++++++++++++++++++
 arch/x86/include/asm/arch-apollolake/gpio.h |   3 +
 doc/device-tree-bindings/device.txt         |   3 +
 3 files changed, 141 insertions(+)
 create mode 100644 arch/x86/include/asm/arch-apollolake/gpe.h

diff --git a/arch/x86/include/asm/arch-apollolake/gpe.h b/arch/x86/include/asm/arch-apollolake/gpe.h
new file mode 100644
index 00000000000..f5792960bee
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/gpe.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2016 Intel Corporation
+ * Copyright 2020 Google LLC
+ *
+ * Taken from coreboot apl gpe.h
+ */
+
+#ifndef _ASM_ARCH_GPE_H_
+#define _ASM_ARCH_GPE_H_
+
+/* bit position in GPE0a_STS register */
+#define GPE0A_PCIE_SCI_STS 0
+#define GPE0A_SWGPE_STS 2
+#define GPE0A_PCIE_WAKE0_STS 3
+#define GPE0A_PUNIT_SCI_STS 4
+#define GPE0A_PCIE_WAKE1_STS 6
+#define GPE0A_PCIE_WAKE2_STS 7
+#define GPE0A_PCIE_WAKE3_STS 8
+#define GPE0A_PCIE_GPE_STS 9
+#define GPE0A_BATLOW_STS 10
+#define GPE0A_CSE_PME_STS 11
+#define GPE0A_XDCI_PME_STS 12
+#define GPE0A_XHCI_PME_STS 13
+#define GPE0A_AVS_PME_STS 14
+#define GPE0A_GPIO_TIER1_SCI_STS 15
+#define GPE0A_SMB_WAK_STS 16
+#define GPE0A_SATA_PME_STS 17
+#define GPE0A_CNVI_PME_STS        18
+
+/* Group DW0 is reserved in Apollolake */
+
+/* GPE_63_32 */
+#define GPE0_DW1_00 32
+#define GPE0_DW1_01 33
+#define GPE0_DW1_02 34
+#define GPE0_DW1_03 36
+#define GPE0_DW1_04 36
+#define GPE0_DW1_05 37
+#define GPE0_DW1_06 38
+#define GPE0_DW1_07 39
+#define GPE0_DW1_08 40
+#define GPE0_DW1_09 41
+#define GPE0_DW1_10 42
+#define GPE0_DW1_11 43
+#define GPE0_DW1_12 44
+#define GPE0_DW1_13 45
+#define GPE0_DW1_14 46
+#define GPE0_DW1_15 47
+#define GPE0_DW1_16 48
+#define GPE0_DW1_17 49
+#define GPE0_DW1_18 50
+#define GPE0_DW1_19 51
+#define GPE0_DW1_20 52
+#define GPE0_DW1_21 53
+#define GPE0_DW1_22 54
+#define GPE0_DW1_23 55
+#define GPE0_DW1_24 56
+#define GPE0_DW1_25 57
+#define GPE0_DW1_26 58
+#define GPE0_DW1_27 59
+#define GPE0_DW1_28 60
+#define GPE0_DW1_29 61
+#define GPE0_DW1_30 62
+#define GPE0_DW1_31 63
+/* GPE_95_64 */
+#define GPE0_DW2_00 64
+#define GPE0_DW2_01 65
+#define GPE0_DW2_02 66
+#define GPE0_DW2_03 67
+#define GPE0_DW2_04 68
+#define GPE0_DW2_05 69
+#define GPE0_DW2_06 70
+#define GPE0_DW2_07 71
+#define GPE0_DW2_08 72
+#define GPE0_DW2_09 73
+#define GPE0_DW2_10 74
+#define GPE0_DW2_11 75
+#define GPE0_DW2_12 76
+#define GPE0_DW2_13 77
+#define GPE0_DW2_14 78
+#define GPE0_DW2_15 79
+#define GPE0_DW2_16 80
+#define GPE0_DW2_17 81
+#define GPE0_DW2_18 82
+#define GPE0_DW2_19 83
+#define GPE0_DW2_20 84
+#define GPE0_DW2_21 85
+#define GPE0_DW2_22 86
+#define GPE0_DW2_23 87
+#define GPE0_DW2_24 88
+#define GPE0_DW2_25 89
+#define GPE0_DW2_26 90
+#define GPE0_DW2_27 91
+#define GPE0_DW2_28 92
+#define GPE0_DW2_29 93
+#define GPE0_DW2_30 94
+#define GPE0_DW2_31 95
+/* GPE_127_96 */
+#define GPE0_DW3_00 96
+#define GPE0_DW3_01 97
+#define GPE0_DW3_02 98
+#define GPE0_DW3_03 99
+#define GPE0_DW3_04 100
+#define GPE0_DW3_05 101
+#define GPE0_DW3_06 102
+#define GPE0_DW3_07 103
+#define GPE0_DW3_08 104
+#define GPE0_DW3_09 105
+#define GPE0_DW3_10 106
+#define GPE0_DW3_11 107
+#define GPE0_DW3_12 108
+#define GPE0_DW3_13 109
+#define GPE0_DW3_14 110
+#define GPE0_DW3_15 111
+#define GPE0_DW3_16 112
+#define GPE0_DW3_17 113
+#define GPE0_DW3_18 114
+#define GPE0_DW3_19 115
+#define GPE0_DW3_20 116
+#define GPE0_DW3_21 117
+#define GPE0_DW3_22 118
+#define GPE0_DW3_23 119
+#define GPE0_DW3_24 120
+#define GPE0_DW3_25 121
+#define GPE0_DW3_26 122
+#define GPE0_DW3_27 123
+#define GPE0_DW3_28 124
+#define GPE0_DW3_29 125
+#define GPE0_DW3_30 126
+#define GPE0_DW3_31 127
+
+#define GPE_MAX GPE0_DW3_31
+
+#endif
diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h
index 10879c168ec..ab5860c0fd0 100644
--- a/arch/x86/include/asm/arch-apollolake/gpio.h
+++ b/arch/x86/include/asm/arch-apollolake/gpio.h
@@ -482,4 +482,7 @@
 #define GPIO_72_IRQ 0x65
 #define GPIO_73_IRQ 0x66
 
+/* This is needed by ACPI */
+#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+
 #endif /* _ASM_ARCH_GPIO_H_ */
diff --git a/doc/device-tree-bindings/device.txt b/doc/device-tree-bindings/device.txt
index 2a5736c5981..73ce2a3b5b5 100644
--- a/doc/device-tree-bindings/device.txt
+++ b/doc/device-tree-bindings/device.txt
@@ -22,6 +22,8 @@ the acpi,compatible property.
  - acpi,name : Provides the ACPI name for a device, which is a string consisting
    of four alphanumeric character (upper case)
  - acpi,uid : _UID value for device
+ - acpi,wake : Provides the GPE used to detect a request from a device to wake
+   from sleep
  - linux,probed : Tells U-Boot to add 'linux,probed' to the ACPI tables so that
     Linux will only load the driver if the device can be detected (e.g. on I2C
     bus). Note that this is an out-of-tree Linux feature.
@@ -46,6 +48,7 @@ pcie-a0@14,0 {
  compatible = "intel,generic-wifi";
  acpi,ddn = "Intel WiFi";
  acpi,name = "WF00";
+ acpi,wake = <GPE0_DW3_00>;
  interrupts-extended = <&acpi_gpe 0x3c 0>;
  };
 };
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 18/59] x86: apl: Support writing the IntelGraphicsMem table

Simon Glass-3
In reply to this post by Simon Glass-3
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

Changes in v1:
- Capitalise ACPI_OPS_PTR
- Don't build for SPL

 arch/x86/Kconfig                           |   8 +
 arch/x86/cpu/apollolake/Kconfig            |   1 +
 arch/x86/cpu/intel_common/Makefile         |   4 +
 arch/x86/cpu/intel_common/intel_opregion.c | 168 ++++++++++++++
 arch/x86/include/asm/intel_opregion.h      | 247 +++++++++++++++++++++
 arch/x86/lib/fsp/fsp_graphics.c            |  32 +++
 include/bloblist.h                         |   1 +
 7 files changed, 461 insertions(+)
 create mode 100644 arch/x86/cpu/intel_common/intel_opregion.c
 create mode 100644 arch/x86/include/asm/intel_opregion.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 680f26f1b8e..675a43e3b60 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1001,4 +1001,12 @@ config PCIEX_LENGTH_128MB
 config PCIEX_LENGTH_64MB
  bool
 
+config INTEL_GMA_ACPI
+ bool "Generate ACPI table for Intel GMA graphics"
+ help
+  The Intel GMA graphics driver in Linux expects an ACPI table
+  which describes the layout of the registers and the display
+  connected to the device. Enable this option to create this
+  table so that graphics works correctly.
+
 endmenu
diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig
index 16ac2b3f504..319f12684b7 100644
--- a/arch/x86/cpu/apollolake/Kconfig
+++ b/arch/x86/cpu/apollolake/Kconfig
@@ -48,6 +48,7 @@ config INTEL_APOLLOLAKE
  imply CMD_CLK
  imply CLK_INTEL
  imply ACPI_GPE
+ imply INTEL_GMA_ACPI
 
 if INTEL_APOLLOLAKE
 
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 374803b8760..207d5413965 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -9,6 +9,10 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
 endif
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o
+endif
+
 ifdef CONFIG_INTEL_CAR_CQOS
 obj-$(CONFIG_TPL_BUILD) += car2.o
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c
new file mode 100644
index 00000000000..4e6c64d9aaa
--- /dev/null
+++ b/arch/x86/cpu/intel_common/intel_opregion.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Writing IntelGraphicsMem table for ACPI
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/soc/intel/gma/opregion.c
+ */
+
+#include <common.h>
+#include <binman.h>
+#include <bloblist.h>
+#include <dm.h>
+#include <spi_flash.h>
+#include <asm/intel_opregion.h>
+
+static char vbt_data[8 << 10];
+
+static int locate_vbt(char **vbtp, int *sizep)
+{
+ struct binman_entry vbt;
+ struct udevice *dev;
+ u32 vbtsig = 0;
+ int size;
+ int ret;
+
+ ret = binman_entry_find("intel-vbt", &vbt);
+ if (ret)
+ return log_msg_ret("find VBT", ret);
+ ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
+ if (ret)
+ return log_msg_ret("find flash", ret);
+ size = vbt.size;
+ if (size > sizeof(vbt_data))
+ return log_msg_ret("vbt", -E2BIG);
+ ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data);
+ if (ret)
+ return log_msg_ret("read", ret);
+
+ memcpy(&vbtsig, vbt_data, sizeof(vbtsig));
+ if (vbtsig != VBT_SIGNATURE) {
+ log_err("Missing/invalid signature in VBT data file!\n");
+ return -EINVAL;
+ }
+
+ log_info("Found a VBT of %u bytes\n", size);
+ *sizep = size;
+ *vbtp = vbt_data;
+
+ return 0;
+}
+
+/* Write ASLS PCI register and prepare SWSCI register */
+static int intel_gma_opregion_register(struct udevice *dev, ulong opregion)
+{
+ int sci_reg;
+
+ if (!device_active(dev))
+ return -ENOENT;
+
+ /*
+ * Intel BIOS Specification
+ * Chapter 5.3.7 "Initialise Hardware State"
+ */
+ dm_pci_write_config32(dev, ASLS, opregion);
+
+ /*
+ * Atom-based platforms use a combined SMI/SCI register,
+ * whereas non-Atom platforms use a separate SCI register
+ */
+ if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
+ sci_reg = SWSMISCI;
+ else
+ sci_reg = SWSCI;
+
+ /*
+ * Intel's Windows driver relies on this:
+ * Intel BIOS Specification
+ * Chapter 5.4 "ASL Software SCI Handler"
+ */
+ dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL);
+
+ return 0;
+}
+
+int intel_gma_init_igd_opregion(struct udevice *dev,
+ struct igd_opregion *opregion)
+{
+ struct optionrom_vbt *vbt = NULL;
+ char *vbt_buf;
+ int vbt_size;
+ int ret;
+
+ ret = locate_vbt(&vbt_buf, &vbt_size);
+ if (ret) {
+ log_err("GMA: VBT couldn't be found\n");
+ return log_msg_ret("find vbt", ret);
+ }
+ vbt = (struct optionrom_vbt *)vbt_buf;
+
+ memset(opregion, '\0', sizeof(struct igd_opregion));
+
+ memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+       sizeof(opregion->header.signature));
+ memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
+       ARRAY_SIZE(vbt->coreblock_biosbuild));
+ /* Extended VBT support */
+ if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) {
+ struct optionrom_vbt *ext_vbt;
+
+ ret = bloblist_ensure_size(BLOBLISTT_INTEL_VBT,
+   vbt->hdr_vbt_size,
+   (void **)&ext_vbt);
+ if (ret) {
+ log_err("GMA: Unable to add Ext VBT to bloblist\n");
+ return log_msg_ret("blob", ret);
+ }
+
+ memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
+ opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
+ opregion->mailbox3.rvds = vbt->hdr_vbt_size;
+ } else {
+ /* Raw VBT size which can fit in gvd1 */
+ printf("copy to %p\n", opregion->vbt.gvd1);
+ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);
+ }
+
+ /* 8kb */
+ opregion->header.size = sizeof(struct igd_opregion) / 1024;
+
+ /*
+ * Left-shift version field to accommodate Intel Windows driver quirk
+ * when not using a VBIOS.
+ * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver.
+ *
+ * No adverse effects when using VBIOS or booting Linux.
+ */
+ opregion->header.version = IGD_OPREGION_VERSION << 24;
+
+ /* We just assume we're mobile for now */
+ opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+ /* Initialise Mailbox 1 */
+ opregion->mailbox1.clid = 1;
+
+ /* Initialise Mailbox 3 */
+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+ opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+ /* Write ASLS PCI register and prepare SWSCI register */
+ ret = intel_gma_opregion_register(dev, (ulong)opregion);
+ if (ret)
+ return log_msg_ret("write asls", ret);
+
+ return 0;
+}
diff --git a/arch/x86/include/asm/intel_opregion.h b/arch/x86/include/asm/intel_opregion.h
new file mode 100644
index 00000000000..fb3e38617e4
--- /dev/null
+++ b/arch/x86/include/asm/intel_opregion.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Writing IntelGraphicsMem table for ACPI
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/soc/intel/gma/opregion.h
+ */
+
+#ifndef _ASM_INTEL_OPREGION_H_
+#define _ASM_INTEL_OPREGION_H_
+
+#define VBT_SIGNATURE 0x54425624
+
+/* IGD PCI Configuration register */
+#define ASLS 0xfc /* OpRegion Base */
+#define SWSCI 0xe8 /* SWSCI Register */
+#define SWSMISCI 0xe0 /* SWSMISCI Register */
+#define GSSCIE BIT(0) /* SCI Event trigger */
+#define SMISCISEL BIT(15) /* Select SMI or SCI event source */
+
+/* mailbox 0: header */
+struct __packed opregion_header {
+ u8 signature[16];    /* Offset 0    OpRegion signature */
+ u32 size;    /* Offset 16   OpRegion size */
+ u32 version;    /* Offset 20   OpRegion structure version */
+ u8 sbios_version[32];  /* Offset 24   System BIOS build version */
+ u8 vbios_version[16];  /* Offset 56   Video BIOS build version */
+ u8 driver_version[16]; /* Offset 72   Graphic drvr build version */
+ u32 mailboxes;    /* Offset 88   Mailboxes supported */
+ u32 dmod;    /* Offset 92   Driver Model */
+ u32 pcon;    /* Offset 96   Platform Capabilities */
+ u16 dver[16];    /* Offset 100  GOP Version */
+ u8 reserved[124];    /* Offset 132  Reserved */
+};
+
+#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
+#define IGD_OPREGION_VERSION  2
+
+#define IGD_MBOX1 BIT(0)
+#define IGD_MBOX2 BIT(1)
+#define IGD_MBOX3 BIT(2)
+#define IGD_MBOX4 BIT(3)
+#define IGD_MBOX5 BIT(4)
+
+#define MAILBOXES_MOBILE  (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
+   IGD_MBOX4 | IGD_MBOX5)
+#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
+
+#define SBIOS_VERSION_SIZE 32
+
+/* mailbox 1: public ACPI methods */
+struct __packed opregion_mailbox1 {
+ u32 drdy; /* Offset 0    Driver readiness */
+ u32 csts; /* Offset 4    Status */
+ u32 cevt; /* Offset 8    Current event */
+ u8 reserved[20]; /* Offset 12   Reserved */
+ u32 didl; /* Offset 32   Supported display device 1 */
+ u32 ddl2; /* Offset 36   Supported display device 2 */
+ u32 ddl3; /* Offset 40   Supported display device 3 */
+ u32 ddl4; /* Offset 44   Supported display device 4 */
+ u32 ddl5; /* Offset 48   Supported display device 5 */
+ u32 ddl6; /* Offset 52   Supported display device 6 */
+ u32 ddl7; /* Offset 56   Supported display device 7 */
+ u32 ddl8; /* Offset 60   Supported display device 8 */
+ u32 cpdl; /* Offset 64   Currently present display device 1 */
+ u32 cpl2; /* Offset 68   Currently present display device 2 */
+ u32 cpl3; /* Offset 72   Currently present display device 3 */
+ u32 cpl4; /* Offset 76   Currently present display device 4 */
+ u32 cpl5; /* Offset 80   Currently present display device 5 */
+ u32 cpl6; /* Offset 84   Currently present display device 6 */
+ u32 cpl7; /* Offset 88   Currently present display device 7 */
+ u32 cpl8; /* Offset 92   Currently present display device 8 */
+ u32 cadl; /* Offset 96   Currently active display device 1 */
+ u32 cal2; /* Offset 100  Currently active display device 2 */
+ u32 cal3; /* Offset 104  Currently active display device 3 */
+ u32 cal4; /* Offset 108  Currently active display device 4 */
+ u32 cal5; /* Offset 112  Currently active display device 5 */
+ u32 cal6; /* Offset 116  Currently active display device 6 */
+ u32 cal7; /* Offset 120  Currently active display device 7 */
+ u32 cal8; /* Offset 124  Currently active display device 8 */
+ u32 nadl; /* Offset 128  Next active device 1 */
+ u32 ndl2; /* Offset 132  Next active device 2 */
+ u32 ndl3; /* Offset 136  Next active device 3 */
+ u32 ndl4; /* Offset 140  Next active device 4 */
+ u32 ndl5; /* Offset 144  Next active device 5 */
+ u32 ndl6; /* Offset 148  Next active device 6 */
+ u32 ndl7; /* Offset 152  Next active device 7 */
+ u32 ndl8; /* Offset 156  Next active device 8 */
+ u32 aslp; /* Offset 160  ASL sleep timeout */
+ u32 tidx; /* Offset 164  Toggle table index */
+ u32 chpd; /* Offset 168  Current hot plug enable indicator */
+ u32 clid; /* Offset 172  Current lid state indicator */
+ u32 cdck; /* Offset 176  Current docking state indicator */
+ u32 sxsw; /* Offset 180  Display Switch notification on Sx State
+ * resume
+ */
+ u32 evts; /* Offset 184  Events supported by ASL */
+ u32 cnot; /* Offset 188  Current OS Notification */
+ u32 nrdy; /* Offset 192  Reasons for DRDY = 0 */
+ u32 ddl9; /* Offset 196  Extended Supported display device 1 */
+ u32 dd10; /* Offset 200  Extended Supported display device 2 */
+ u32 dd11; /* Offset 204  Extended Supported display device 3 */
+ u32 dd12; /* Offset 208  Extended Supported display device 4 */
+ u32 dd13; /* Offset 212  Extended Supported display device 5 */
+ u32 dd14; /* Offset 216  Extended Supported display device 6 */
+ u32 dd15; /* Offset 220  Extended Supported display device 7 */
+ u32 cpl9; /* Offset 224  Extended Currently present device 1 */
+ u32 cp10; /* Offset 228  Extended Currently present device 2 */
+ u32 cp11; /* Offset 232  Extended Currently present device 3 */
+ u32 cp12; /* Offset 236  Extended Currently present device 4 */
+ u32 cp13; /* Offset 240  Extended Currently present device 5 */
+ u32 cp14; /* Offset 244  Extended Currently present device 6 */
+ u32 cp15; /* Offset 248  Extended Currently present device 7 */
+ u8 reserved2[4]; /* Offset 252  Reserved 4 bytes */
+};
+
+/* mailbox 2: software sci interface */
+struct __packed opregion_mailbox2 {
+ u32 scic; /* Offset 0  Software SCI function number parameters */
+ u32 parm; /* Offset 4  Software SCI function number parameters */
+ u32 dslp; /* Offset 8  Driver sleep timeout */
+ u8 reserved[244]; /* Offset 12   Reserved */
+};
+
+/* mailbox 3: power conservation */
+struct __packed opregion_mailbox3 {
+ u32 ardy; /* Offset 0   Driver readiness */
+ u32 aslc; /* Offset 4   ASLE interrupt command / status */
+ u32 tche; /* Offset 8   Technology enabled indicator */
+ u32 alsi; /* Offset 12  Current ALS illuminance reading */
+ u32 bclp; /* Offset 16  Backlight britness to set */
+ u32 pfit; /* Offset 20  Panel fitting Request */
+ u32 cblv; /* Offset 24  Brightness Current State */
+ /* Offset 28  Backlight Brightness Level Duty Cycle Mapping Table */
+ u16 bclm[20];
+ u32 cpfm; /* Offset 68  Panel Fitting Current Mode */
+ u32 epfm; /* Offset 72  Enabled Panel Fitting Modes */
+ u8 plut[74]; /* Offset 76  Panel Look Up Table */
+ /* Offset 150 PWM Frequency and Minimum Brightness */
+ u32 pfmb;
+ u32 ccdv; /* Offset 154 Color Correction Default Values */
+ u32 pcft; /* Offset 158 Power Conservation Features */
+ u32 srot; /* Offset 162 Supported Rotation angle */
+ u32 iuer; /* Offset 166 Intel Ultrabook Event Register */
+ u64 fdsp; /* Offset 170 FFS Display Physical address */
+ u32 fdss; /* Offset 178 FFS Display Size */
+ u32 stat; /* Offset 182 State Indicator */
+ /*
+ * Offset 186 (Igd opregion offset 0x3BAh)
+ * Physical address of Raw VBT data
+ */
+ u64 rvda;
+ /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */
+ u32 rvds;
+ u8 reserved[58]; /* Offset 198 Reserved */
+};
+
+#define IGD_BACKLIGHT_BRIGHTNESS 0xff
+#define IGD_INITIAL_BRIGHTNESS 0x64
+
+#define IGD_FIELD_VALID BIT(31)
+#define IGD_WORD_FIELD_VALID BIT(15)
+#define IGD_PFIT_STRETCH 6
+
+/* mailbox 4: vbt */
+struct __packed opregion_vbt {
+ u8 gvd1[6 << 10];
+};
+
+/* Mailbox 5: BIOS to Driver Notification Extension */
+struct __packed opregion_mailbox5 {
+ u32 phed; /* Offset 7168 Panel Header */
+ u8 bddc[256]; /* Offset 7172 Panel EDID */
+ u8 reserved[764]; /* Offset 7428 764 bytes */
+};
+
+/* IGD OpRegion */
+struct __packed igd_opregion {
+ struct opregion_header header;
+ struct opregion_mailbox1 mailbox1;
+ struct opregion_mailbox2 mailbox2;
+ struct opregion_mailbox3 mailbox3;
+ struct opregion_vbt vbt;
+ struct opregion_mailbox5 mailbox5;
+};
+
+/* Intel Video BIOS (Option ROM) */
+struct __packed optionrom_header {
+ u16 signature;
+ u8 size;
+ u8 reserved[21];
+ u16 pcir_offset;
+ u16 vbt_offset;
+};
+
+#define OPROM_SIGNATURE 0xaa55
+
+struct __packed optionrom_pcir {
+ u32 signature;
+ u16 vendor;
+ u16 device;
+ u16 reserved1;
+ u16 length;
+ u8 revision;
+ u8 classcode[3];
+ u16 imagelength;
+ u16 coderevision;
+ u8 codetype;
+ u8 indicator;
+ u16 reserved2;
+};
+
+struct __packed optionrom_vbt {
+ u8 hdr_signature[20];
+ u16 hdr_version;
+ u16 hdr_size;
+ u16 hdr_vbt_size;
+ u8 hdr_vbt_checksum;
+ u8 hdr_reserved;
+ u32 hdr_vbt_datablock;
+ u32 hdr_aim[4];
+ u8 datahdr_signature[16];
+ u16 datahdr_version;
+ u16 datahdr_size;
+ u16 datahdr_datablocksize;
+ u8 coreblock_id;
+ u16 coreblock_size;
+ u16 coreblock_biossize;
+ u8 coreblock_biostype;
+ u8 coreblock_releasestatus;
+ u8 coreblock_hwsupported;
+ u8 coreblock_integratedhw;
+ u8 coreblock_biosbuild[4];
+ u8 coreblock_biossignon[155];
+};
+
+/**
+ * intel_gma_init_igd_opregion() - Initialise IGD OpRegion
+ *
+ * This is called from ACPI code and OS drivers
+ *
+ * @return 0 if OK, -ve on error
+ */
+int intel_gma_init_igd_opregion(struct udevice *dev,
+ struct igd_opregion *opregion);
+
+#endif /* _ASM_INTEL_OPREGION_H_ */
diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index e8c1e07af1c..858d7942fed 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -3,14 +3,19 @@
  * Copyright (C) 2017, Bin Meng <[hidden email]>
  */
 
+#define LOG_CATEGORY UCLASS_VIDEO
+
 #include <common.h>
 #include <dm.h>
 #include <init.h>
 #include <log.h>
 #include <vbe.h>
 #include <video.h>
+#include <acpi/acpi_table.h>
 #include <asm/fsp/fsp_support.h>
+#include <asm/intel_opregion.h>
 #include <asm/mtrr.h>
+#include <dm/acpi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -127,6 +132,32 @@ static int fsp_video_bind(struct udevice *dev)
  return 0;
 }
 
+#ifdef CONFIG_INTEL_GMA_ACPI
+static int fsp_video_acpi_write_tables(const struct udevice *dev,
+       struct acpi_ctx *ctx)
+{
+ struct igd_opregion *opregion;
+ int ret;
+
+ printf("ACPI:    * IGD OpRegion\n");
+ opregion = (struct igd_opregion *)ctx->current;
+
+ ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion);
+ if (ret)
+ return ret;
+
+ acpi_inc_align(ctx, sizeof(struct igd_opregion));
+
+ return 0;
+}
+#endif
+
+struct acpi_ops fsp_video_acpi_ops = {
+#ifdef CONFIG_INTEL_GMA_ACPI
+ .write_tables = fsp_video_acpi_write_tables,
+#endif
+};
+
 static const struct udevice_id fsp_video_ids[] = {
  { .compatible = "fsp-fb" },
  { }
@@ -139,6 +170,7 @@ U_BOOT_DRIVER(fsp_video) = {
  .bind = fsp_video_bind,
  .probe = fsp_video_probe,
  .flags = DM_FLAG_PRE_RELOC,
+ ACPI_OPS_PTR(&fsp_video_acpi_ops)
 };
 
 static struct pci_device_id fsp_video_supported[] = {
diff --git a/include/bloblist.h b/include/bloblist.h
index bbe0a35d5a2..7d8480548e0 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -32,6 +32,7 @@ enum bloblist_tag_t {
  * Sleeping table. This forms part of the ACPI tables passed to Linux.
  */
  BLOBLISTT_ACPI_GNVS,
+ BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */
 };
 
 /**
--
2.28.0.681.g6f77f65b4e-goog

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[PATCH v4 19/59] x86: acpi: Add a common routine to write WiFi info

Simon Glass-3
In reply to this post by Simon Glass-3
Intel WiFi chips can use a common routine to write the information needed
by linux. Add an implementation of this.

Enable it for coral.

Signed-off-by: Simon Glass <[hidden email]>
---

(no changes since v1)

Changes in v1:
- Capitalise ACPI_OPS_PTR
- Use acpi,ddn instead of acpi,desc

 arch/x86/Kconfig                         |   8 ++
 arch/x86/cpu/intel_common/Makefile       |   1 +
 arch/x86/cpu/intel_common/generic_wifi.c | 120 +++++++++++++++++++++++
 configs/chromebook_coral_defconfig       |   1 +
 4 files changed, 130 insertions(+)
 create mode 100644 arch/x86/cpu/intel_common/generic_wifi.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 675a43e3b60..495629d32ed 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1009,4 +1009,12 @@ config INTEL_GMA_ACPI
   connected to the device. Enable this option to create this
   table so that graphics works correctly.
 
+config INTEL_GENERIC_WIFI
+ bool "Enable generation of ACPI tables for Intel WiFi"
+ help
+  Select this option to provide code to a build generic WiFi ACPI table
+  for Intel WiFi devices. This is not a WiFi driver and offers no
+  network functionality. It is only here to generate the ACPI tables
+  required by Linux.
+
 endmenu
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 207d5413965..f1d1513a981 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -24,6 +24,7 @@ obj-y += cpu.o
 obj-y += fast_spi.o
 obj-y += lpc.o
 obj-y += lpss.o
+obj-$(CONFIG_INTEL_GENERIC_WIFI) += generic_wifi.o
 ifndef CONFIG_TARGET_EFI_APP
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
 ifndef CONFIG_$(SPL_)X86_64
diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c
new file mode 100644
index 00000000000..61ec5391b09
--- /dev/null
+++ b/arch/x86/cpu/intel_common/generic_wifi.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generic WiFi ACPI info
+ *
+ * Copyright 2019 Google LLC
+ * Modified from coreboot src/drivers/wifi/generic.c
+ */
+
+#include <common.h>
+#include <log.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpi_device.h>
+#include <dm.h>
+#include <dm/acpi.h>
+
+/* WRDS Spec Revision */
+#define WRDS_REVISION 0x0
+
+/* EWRD Spec Revision */
+#define EWRD_REVISION 0x0
+
+/* WRDS Domain type */
+#define WRDS_DOMAIN_TYPE_WIFI 0x7
+
+/* EWRD Domain type */
+#define EWRD_DOMAIN_TYPE_WIFI 0x7
+
+/* WGDS Domain type */
+#define WGDS_DOMAIN_TYPE_WIFI 0x7
+
+/*
+ * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0'
+ * The above representation returns unique and consistent name every time
+ * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is
+ * chosen since it contains the bus address of the device.
+ */
+#define WIFI_ACPI_NAME_MAX_LEN 5
+
+/**
+ * struct generic_wifi_config - Data structure to contain common wifi config
+ * @wake: Wake pin for ACPI _PRW
+ * @maxsleep: Maximum sleep state to wake from
+ */
+struct generic_wifi_config {
+ unsigned int wake;
+ unsigned int maxsleep;
+};
+
+static int generic_wifi_fill_ssdt(struct acpi_ctx *ctx,
+  const struct udevice *dev,
+  const struct generic_wifi_config *config)
+{
+ char name[ACPI_NAME_MAX];
+ char path[ACPI_PATH_MAX];
+ pci_dev_t bdf;
+ u32 address;
+ int ret;
+
+ ret = acpi_device_path(dev_get_parent(dev), path, sizeof(path));
+ if (ret)
+ return log_msg_ret("path", ret);
+ ret = acpi_get_name(dev, name);
+ if (ret)
+ return log_msg_ret("name", ret);
+
+ /* Device */
+ acpigen_write_scope(ctx, path);
+ acpigen_write_device(ctx, name);
+ acpigen_write_name_integer(ctx, "_UID", 0);
+ acpigen_write_name_string(ctx, "_DDN",
+  dev_read_string(dev, "acpi,ddn"));
+
+ /* Address */
+ bdf = dm_pci_get_bdf(dev);
+ address = (PCI_DEV(bdf) << 16) | PCI_FUNC(bdf);
+ acpigen_write_name_dword(ctx, "_ADR", address);
+
+ /* Wake capabilities */
+ if (config)
+ acpigen_write_prw(ctx, config->wake, config->maxsleep);
+
+ acpigen_pop_len(ctx); /* Device */
+ acpigen_pop_len(ctx); /* Scope */
+
+ return 0;
+}
+
+static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev,
+     struct acpi_ctx *ctx)
+{
+ struct generic_wifi_config config;
+ bool have_config;
+ int ret;
+
+ ret = dev_read_u32(dev, "acpi,wake", &config.wake);
+ have_config = !ret;
+ /* By default, all intel wifi chips wake from S3 */
+ config.maxsleep = 3;
+ ret = generic_wifi_fill_ssdt(ctx, dev, have_config ? &config : NULL);
+ if (ret)
+ return log_msg_ret("wifi", ret);
+
+ return 0;
+}
+
+struct acpi_ops wifi_acpi_ops = {
+ .fill_ssdt = intel_wifi_acpi_fill_ssdt,
+};
+
+static const struct udevice_id intel_wifi_ids[] = {
+ { .compatible = "intel,generic-wifi" },
+ { }
+};
+
+U_BOOT_DRIVER(intel_wifi) = {
+ .name = "intel_wifi",
+ .id = UCLASS_MISC,
+ .of_match = intel_wifi_ids,
+ ACPI_OPS_PTR(&wifi_acpi_ops)
+};
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index e1d0749239b..c9006e2f934 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -18,6 +18,7 @@ CONFIG_HAVE_ACPI_RESUME=y
 CONFIG_INTEL_CAR_CQOS=y
 CONFIG_X86_OFFSET_U_BOOT=0xffe00000
 CONFIG_X86_OFFSET_SPL=0xffe80000
+CONFIG_INTEL_GENERIC_WIFI=y
 CONFIG_BOOTSTAGE=y
 CONFIG_SPL_BOOTSTAGE=y
 CONFIG_TPL_BOOTSTAGE=y
--
2.28.0.681.g6f77f65b4e-goog

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