[PATCH v4 00/27] TF-A Boot support for NXP Chassis 2 platforms

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[PATCH v4 00/27] TF-A Boot support for NXP Chassis 2 platforms

Rajesh Bhagat-2
Includes changes in u-boot framework to support TF-A for NXP Chassis 2
platforms. A new defconfig is added namely ls*_tfa_defconfig which will
be used for all boot sources when TF-A is used.                                
                                                                               
Tested on LS1043A, LS1046A and LS1012A platforms.

Changes in v4:
 - Changed order of patches to solve compilation issue and warning
 - Added support for additional ls1012a boards

Changes in v3:
 - Changed order of TFABOOT dependent patches
 - Merged secureboot TFA boot support patches
 - Merged nand env patches to remove warning

Changes in v2:
 - Patch subject and description changes
 - Removed extra CONFIG_TFABOOT flag usage
 - Merged board specific TFA boot support patches                                
 - Checked compilation using buildman tool for each commit

Pankit Garg (5):
  armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
  drivers: ifc: dynamic chipselect mapping support
  armv8: fsl-layerscape: bootcmd identification for TFABOOT
  armv8: sec_firmware: return job ring status as true in TFABOOT
  armv8: fsl-layerscape: add support of MC framework for TFA

Rajesh Bhagat (19):
  env: allow flash and nand env driver to compile together
  env: sf: define API to override sf environment address
  driver/ifc: replace __ilog2 with LOG2 macro
  armv8: layerscape: Add TFABOOT support
  armv8: fsl-layerscape: identify boot source from PORSR register
  armv8: layerscape: remove EL3 specific erratas for TFABOOT
  armv8: layerscape: add SMC calls for DDR size and bank info
  armv8: layerscape: skip OCRAM init for TFABOOT
  armv8: sec_firmware: change el2_to_aarch32 SMC ID
  net: fm: add TFABOOT support
  drivers: qe: add TFABOOT support
  armv8: ls1046ardb: Add TFABOOT support
  armv8: ls1046aqds: Add TFABOOT support
  armv8: ls1043ardb: Add TFABOOT support
  armv8: ls1043aqds: Add TFABOOT support
  armv8: ls1012ardb: Add TFABOOT support
  armv8: ls1012aqds: fix secure boot compilation
  armv8: ls1012aqds: Add TFABOOT support
  armv8: ls1012afrx: Add TFABOOT support

York Sun (3):
  move data structure out of cpu.h
  armv8: layerscape: Enable routing SError exception
  armv8: fsl-layerscape: Update parsing boot source

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig     |  31 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c       | 613 +++++++++++++++++-
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S  |  12 +-
 arch/arm/cpu/armv8/fsl-layerscape/soc.c       | 128 ++++
 arch/arm/cpu/armv8/sec_firmware.c             |   4 +
 arch/arm/cpu/armv8/sec_firmware_asm.S         |   2 +-
 .../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 ---------
 .../asm/arch-fsl-layerscape/immap_lsch2.h     |  20 +
 .../asm/arch-fsl-layerscape/immap_lsch3.h     |  49 ++
 .../arm/include/asm/arch-fsl-layerscape/soc.h |  22 +
 board/freescale/ls1012afrdm/ls1012afrdm.c     |  29 +-
 board/freescale/ls1012aqds/Kconfig            |  10 +
 board/freescale/ls1012aqds/ls1012aqds.c       |  23 +-
 board/freescale/ls1012ardb/Kconfig            |   4 +
 board/freescale/ls1012ardb/ls1012ardb.c       |  16 +-
 board/freescale/ls1043aqds/ddr.c              |  11 +
 board/freescale/ls1043aqds/ls1043aqds.c       | 147 ++++-
 board/freescale/ls1043ardb/ddr.c              |  14 +
 board/freescale/ls1043ardb/ls1043ardb.c       | 110 ++++
 board/freescale/ls1046aqds/ddr.c              |  11 +
 board/freescale/ls1046aqds/ls1046aqds.c       | 148 ++++-
 board/freescale/ls1046ardb/ddr.c              |  12 +
 configs/ls1012a2g5rdb_tfa_defconfig           |  50 ++
 configs/ls1012afrdm_tfa_defconfig             |  50 ++
 configs/ls1012afrwy_tfa_defconfig             |  48 ++
 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig  |  65 ++
 configs/ls1012aqds_tfa_defconfig              |  62 ++
 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig  |  63 ++
 configs/ls1012ardb_tfa_defconfig              |  56 ++
 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig  |  58 ++
 configs/ls1043aqds_tfa_defconfig              |  54 ++
 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig  |  51 ++
 configs/ls1043ardb_tfa_defconfig              |  49 ++
 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig  |  58 ++
 configs/ls1046aqds_tfa_defconfig              |  57 ++
 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig  |  52 ++
 configs/ls1046ardb_tfa_defconfig              |  49 ++
 drivers/misc/fsl_ifc.c                        | 488 ++++++++++----
 drivers/net/fm/fm.c                           | 102 ++-
 drivers/qe/qe.c                               |  81 +++
 env/flash.c                                   |   4 +-
 env/nand.c                                    |   6 +-
 env/sf.c                                      |   9 +-
 include/configs/B4860QDS.h                    |   2 +-
 include/configs/T102xQDS.h                    |   2 +-
 include/configs/T1040QDS.h                    |   2 +-
 include/configs/T208xQDS.h                    |   2 +-
 include/configs/T4240QDS.h                    |   2 +-
 include/configs/T4240RDB.h                    |   2 +-
 include/configs/ls1012a2g5rdb.h               |   6 +
 include/configs/ls1012a_common.h              |  16 +-
 include/configs/ls1012afrdm.h                 |   5 +
 include/configs/ls1012afrwy.h                 |   6 +
 include/configs/ls1012aqds.h                  |   1 +
 include/configs/ls1012ardb.h                  |   6 +
 include/configs/ls1043a_common.h              |  27 +-
 include/configs/ls1043aqds.h                  |  50 +-
 include/configs/ls1043ardb.h                  |  29 +
 include/configs/ls1046a_common.h              |  12 +
 include/configs/ls1046aqds.h                  |  59 +-
 include/configs/ls1046ardb.h                  |  15 +
 include/environment.h                         |   1 -
 include/fsl_ifc.h                             |  27 +-
 63 files changed, 3012 insertions(+), 488 deletions(-)
 create mode 100644 configs/ls1012a2g5rdb_tfa_defconfig
 create mode 100644 configs/ls1012afrdm_tfa_defconfig
 create mode 100644 configs/ls1012afrwy_tfa_defconfig
 create mode 100644 configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1012aqds_tfa_defconfig
 create mode 100644 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1012ardb_tfa_defconfig
 create mode 100644 configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1043aqds_tfa_defconfig
 create mode 100644 configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1043ardb_tfa_defconfig
 create mode 100644 configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1046aqds_tfa_defconfig
 create mode 100644 configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
 create mode 100644 configs/ls1046ardb_tfa_defconfig

--
2.17.1

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[PATCH v4 01/27] move data structure out of cpu.h

Rajesh Bhagat-2
From: York Sun <[hidden email]>

Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.

Signed-off-by: York Sun <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c       | 297 +++++++++++++++++
 .../arm/include/asm/arch-fsl-layerscape/cpu.h | 300 ------------------
 2 files changed, 297 insertions(+), 300 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 052e0708d4..bae50f68d8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,303 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+ CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+ CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+ CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
+ CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
+ CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
+ CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
+ CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
+ CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
+ CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
+ CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+ CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+ CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+ CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+ CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+ CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
+};
+
+#define EARLY_PGTABLE_SIZE 0x5000
+static struct mm_region early_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+  CONFIG_SYS_FSL_CCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+  SYS_FSL_OCRAM_SPACE_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+  CONFIG_SYS_FSL_QSPI_SIZE1,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+  CONFIG_SYS_FSL_IFC_SIZE1_1,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+  CONFIG_SYS_FSL_IFC_SIZE1,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+  CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#ifdef CONFIG_FSL_IFC
+ /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+  CONFIG_SYS_FSL_DCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+  CONFIG_SYS_FSL_DRAM_SIZE2,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+  CONFIG_SYS_FSL_CCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+  SYS_FSL_OCRAM_SPACE_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+  CONFIG_SYS_FSL_DCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+  CONFIG_SYS_FSL_QSPI_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+  CONFIG_SYS_FSL_IFC_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+  CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+  CONFIG_SYS_FSL_DRAM_SIZE2,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#endif
+ {}, /* list terminator */
+};
+
+static struct mm_region final_map[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+  CONFIG_SYS_FSL_CCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+  SYS_FSL_OCRAM_SPACE_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+  CONFIG_SYS_FSL_DRAM_SIZE1,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+  CONFIG_SYS_FSL_QSPI_SIZE1,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+  CONFIG_SYS_FSL_QSPI_SIZE2,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+  CONFIG_SYS_FSL_IFC_SIZE2,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#endif
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+  CONFIG_SYS_FSL_DCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+  CONFIG_SYS_FSL_MC_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+  CONFIG_SYS_FSL_NI_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ /* For QBMAN portal, only the first 64MB is cache-enabled */
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+  CONFIG_SYS_FSL_QBMAN_SIZE_1,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+  CONFIG_SYS_PCIE1_PHYS_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+  CONFIG_SYS_PCIE2_PHYS_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+  CONFIG_SYS_PCIE3_PHYS_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#ifdef CONFIG_ARCH_LS2080A
+ { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+  CONFIG_SYS_PCIE4_PHYS_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#endif
+ { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+  CONFIG_SYS_FSL_WRIOP1_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+  CONFIG_SYS_FSL_AIOP1_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+  CONFIG_SYS_FSL_PEBUF_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+  CONFIG_SYS_FSL_DRAM_SIZE2,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
+  CONFIG_SYS_FSL_BOOTROM_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+  CONFIG_SYS_FSL_CCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+  SYS_FSL_OCRAM_SPACE_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+  CONFIG_SYS_FSL_DCSR_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+  CONFIG_SYS_FSL_QSPI_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#ifdef CONFIG_FSL_IFC
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+  CONFIG_SYS_FSL_IFC_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ },
+#endif
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+  CONFIG_SYS_FSL_DRAM_SIZE1,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+  CONFIG_SYS_FSL_QBMAN_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+  CONFIG_SYS_FSL_DRAM_SIZE2,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+  CONFIG_SYS_PCIE1_PHYS_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+  CONFIG_SYS_PCIE2_PHYS_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+  CONFIG_SYS_PCIE3_PHYS_SIZE,
+  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+  CONFIG_SYS_FSL_DRAM_SIZE3,
+  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
+ },
+#endif
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+ {}, /* space holder for secure mem */
+#endif
+ {},
+};
+
 struct mm_region *mem_map = early_map;
 
 void cpu_name(char *name)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 48d0ab163a..3926aa3039 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -7,30 +7,6 @@
 #ifndef _FSL_LAYERSCAPE_CPU_H
 #define _FSL_LAYERSCAPE_CPU_H
 
-static struct cpu_type cpu_type_list[] = {
- CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
- CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
- CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
- CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
- CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
- CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
- CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
- CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
- CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
- CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
- CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
- CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
- CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
- CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
- CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
- CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
- CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
- CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
- CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
-};
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-
 #ifdef CONFIG_FSL_LSCH3
 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
@@ -90,282 +66,6 @@ static struct cpu_type cpu_type_list[] = {
 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
 #endif
 
-#define EARLY_PGTABLE_SIZE 0x5000
-static struct mm_region early_map[] = {
-#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-  CONFIG_SYS_FSL_CCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-  SYS_FSL_OCRAM_SPACE_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-  CONFIG_SYS_FSL_QSPI_SIZE1,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
-#ifdef CONFIG_FSL_IFC
- /* For IFC Region #1, only the first 4MB is cache-enabled */
- { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-  CONFIG_SYS_FSL_IFC_SIZE1_1,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-  CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
-  CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-  CONFIG_SYS_FSL_IFC_SIZE1,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-  CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#ifdef CONFIG_FSL_IFC
- /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-  CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-  CONFIG_SYS_FSL_DCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-  CONFIG_SYS_FSL_DRAM_SIZE2,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#elif defined(CONFIG_FSL_LSCH2)
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-  CONFIG_SYS_FSL_CCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-  SYS_FSL_OCRAM_SPACE_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-  CONFIG_SYS_FSL_DCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-  CONFIG_SYS_FSL_QSPI_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-  CONFIG_SYS_FSL_IFC_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-  CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-#endif
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-  CONFIG_SYS_FSL_DRAM_SIZE2,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#endif
- {}, /* list terminator */
-};
-
-static struct mm_region final_map[] = {
-#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-  CONFIG_SYS_FSL_CCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-  SYS_FSL_OCRAM_SPACE_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-  CONFIG_SYS_FSL_DRAM_SIZE1,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
-  CONFIG_SYS_FSL_QSPI_SIZE1,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
-  CONFIG_SYS_FSL_QSPI_SIZE2,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-  CONFIG_SYS_FSL_IFC_SIZE2,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-  CONFIG_SYS_FSL_DCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
-  CONFIG_SYS_FSL_MC_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
-  CONFIG_SYS_FSL_NI_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- /* For QBMAN portal, only the first 64MB is cache-enabled */
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-  CONFIG_SYS_FSL_QBMAN_SIZE_1,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-  CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
-  CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-  CONFIG_SYS_PCIE1_PHYS_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-  CONFIG_SYS_PCIE2_PHYS_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-  CONFIG_SYS_PCIE3_PHYS_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#ifdef CONFIG_ARCH_LS2080A
- { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-  CONFIG_SYS_PCIE4_PHYS_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#endif
- { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
-  CONFIG_SYS_FSL_WRIOP1_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
-  CONFIG_SYS_FSL_AIOP1_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
-  CONFIG_SYS_FSL_PEBUF_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-  CONFIG_SYS_FSL_DRAM_SIZE2,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#elif defined(CONFIG_FSL_LSCH2)
- { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
-  CONFIG_SYS_FSL_BOOTROM_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-  CONFIG_SYS_FSL_CCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-  SYS_FSL_OCRAM_SPACE_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
- },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-  CONFIG_SYS_FSL_DCSR_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-  CONFIG_SYS_FSL_QSPI_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
-#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
-  CONFIG_SYS_FSL_IFC_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
- },
-#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-  CONFIG_SYS_FSL_DRAM_SIZE1,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-  CONFIG_SYS_FSL_QBMAN_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-  CONFIG_SYS_FSL_DRAM_SIZE2,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
- { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-  CONFIG_SYS_PCIE1_PHYS_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-  CONFIG_SYS_PCIE2_PHYS_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-  CONFIG_SYS_PCIE3_PHYS_SIZE,
-  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
- },
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-  CONFIG_SYS_FSL_DRAM_SIZE3,
-  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
- },
-#endif
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
- {}, /* space holder for secure mem */
-#endif
- {},
-};
-#endif /* !CONFIG_SYS_DCACHE_OFF */
-
 int fsl_qoriq_core_to_cluster(unsigned int core);
 u32 cpu_mask(void);
 
--
2.17.1

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[PATCH v4 02/27] env: allow flash and nand env driver to compile together

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Define env_ptr as static in flash and nand env driver to
allow these to compile together.

Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None

Change in v3:
 - Merged env nand specific patches to remove compilation warning

Change in v2: None

 env/flash.c           | 4 ++--
 env/nand.c            | 6 ++----
 include/environment.h | 1 -
 3 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/env/flash.c b/env/flash.c
index 32236c716e..33b199f05b 100644
--- a/env/flash.c
+++ b/env/flash.c
@@ -45,13 +45,13 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 #ifdef ENV_IS_EMBEDDED
-env_t *env_ptr = &environment;
+static env_t *env_ptr = &environment;
 
 static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR;
 
 #else /* ! ENV_IS_EMBEDDED */
 
-env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
+static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR;
 static __maybe_unused env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR;
 #endif /* ENV_IS_EMBEDDED */
 
diff --git a/env/nand.c b/env/nand.c
index 3698e68957..29eda66fad 100644
--- a/env/nand.c
+++ b/env/nand.c
@@ -40,11 +40,9 @@
 #endif
 
 #if defined(ENV_IS_EMBEDDED)
-env_t *env_ptr = &environment;
+static env_t *env_ptr = &environment;
 #elif defined(CONFIG_NAND_ENV_DST)
-env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST;
-#else /* ! ENV_IS_EMBEDDED */
-env_t *env_ptr;
+static env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST;
 #endif /* ENV_IS_EMBEDDED */
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/include/environment.h b/include/environment.h
index 5e90f157e8..7da1291d5b 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -157,7 +157,6 @@ extern env_t environment;
 #endif /* ENV_IS_EMBEDDED */
 
 extern const unsigned char default_environment[];
-extern env_t *env_ptr;
 
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 extern void env_reloc(void);
--
2.17.1

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[PATCH v4 03/27] env: sf: define API to override sf environment address

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Defines env_sf_get_env_addr API to override sf environment address,
required to support multiple environment.

Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 env/sf.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/env/sf.c b/env/sf.c
index 2e3c600483..23cbad5d88 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -298,10 +298,17 @@ out:
 }
 #endif
 
+#ifdef CONFIG_ENV_ADDR
+__weak void *env_sf_get_env_addr(void)
+{
+ return (void *)CONFIG_ENV_ADDR;
+}
+#endif
+
 #if defined(INITENV) && defined(CONFIG_ENV_ADDR)
 static int env_sf_init(void)
 {
- env_t *env_ptr = (env_t *)(CONFIG_ENV_ADDR);
+ env_t *env_ptr = (env_t *)env_sf_get_env_addr();
 
  if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
  gd->env_addr = (ulong)&(env_ptr->data);
--
2.17.1

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[PATCH v4 04/27] driver/ifc: replace __ilog2 with LOG2 macro

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Replaces __ilog2 function call with LOG2 macro, required to
use macros in global variables.

Also, corrects the value passed in LOG2 for some PowerPC
platforms. Minimum value that can be configured is is 64K
for IFC IP.

Signed-off-by: Pankit Garg <[hidden email]>
Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 include/configs/B4860QDS.h |  2 +-
 include/configs/T102xQDS.h |  2 +-
 include/configs/T1040QDS.h |  2 +-
 include/configs/T208xQDS.h |  2 +-
 include/configs/T4240QDS.h |  2 +-
 include/configs/T4240RDB.h |  2 +-
 include/fsl_ifc.h          | 10 +++++-----
 7 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index c37864c139..be7ee8e433 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -286,7 +286,7 @@ unsigned long get_board_ddr_clk(void);
  | CSPR_PORT_SIZE_8 \
  | CSPR_MSEL_GPCM \
  | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
 #define CONFIG_SYS_CSOR3 0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index 191616b8b0..a8d64998f2 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -299,7 +299,7 @@ unsigned long get_board_ddr_clk(void);
  | CSPR_PORT_SIZE_8 \
  | CSPR_MSEL_GPCM \
  | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR3 0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index 25615be40e..6a91071162 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -225,7 +225,7 @@ unsigned long get_board_ddr_clk(void);
  | CSPR_PORT_SIZE_8 \
  | CSPR_MSEL_GPCM \
  | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR3 0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 7d9354b360..8d358c9285 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -275,7 +275,7 @@ unsigned long get_board_ddr_clk(void);
  | CSPR_PORT_SIZE_8 \
  | CSPR_MSEL_GPCM \
  | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR3 0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index f85881fc3c..0b469b1477 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -201,7 +201,7 @@ unsigned long get_board_ddr_clk(void);
  | CSPR_PORT_SIZE_8 \
  | CSPR_MSEL_GPCM \
  | CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR3 0x0
 /* QIXIS Timing parameters for IFC CS3 */
 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 9d8834a3be..27bd145b52 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -470,7 +470,7 @@ unsigned long get_board_ddr_clk(void);
  | CSPR_MSEL_GPCM \
  | CSPR_V)
 
-#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
 #define CONFIG_SYS_CSOR3 0x0
 
 /* CPLD Timing parameters for IFC CS3 */
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index 8120ca0de8..17697c7341 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -70,7 +70,7 @@
 #define IFC_AMASK_MASK 0xFFFF0000
 #define IFC_AMASK_SHIFT 16
 #define IFC_AMASK(n) (IFC_AMASK_MASK << \
- (__ilog2(n) - IFC_AMASK_SHIFT))
+ (LOG2(n) - IFC_AMASK_SHIFT))
 
 /*
  * Chip Select Option Register IFC_NAND Machine
@@ -111,7 +111,7 @@
 /* Pages Per Block */
 #define CSOR_NAND_PB_MASK 0x00000700
 #define CSOR_NAND_PB_SHIFT 8
-#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
+#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
 /* Time for Read Enable High to Output High Impedance */
 #define CSOR_NAND_TRHZ_MASK 0x0000001C
 #define CSOR_NAND_TRHZ_SHIFT 2
@@ -164,7 +164,7 @@
 /* GPCM Timeout Count */
 #define CSOR_GPCM_GPTO_MASK 0x0F000000
 #define CSOR_GPCM_GPTO_SHIFT 24
-#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
+#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
 /* GPCM External Access Termination mode for read access */
 #define CSOR_GPCM_RGETA_EXT 0x00080000
 /* GPCM External Access Termination mode for write access */
@@ -644,7 +644,7 @@ enum ifc_nand_fir_opcodes {
  */
 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
 #define IFC_NAND_NCR_FTOCNT_SHIFT 25
-#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
+#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
 
 /*
  * NAND_AUTOBOOT_TRGR
@@ -727,7 +727,7 @@ enum ifc_nand_fir_opcodes {
 /* Sequence Timeout Count */
 #define IFC_NORCR_STOCNT_MASK 0x000F0000
 #define IFC_NORCR_STOCNT_SHIFT 16
-#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
+#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
 
 /*
  * GPCM Machine specific registers
--
2.17.1

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[PATCH v4 05/27] armv8: layerscape: Enable routing SError exception

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
From: York Sun <[hidden email]>

In case SError happens at EL2, if SCR_EL3[EA] is not routing it to
EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes
the exception to EL2. Otherwise this exception is not taken.

Signed-off-by: York Sun <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index ef3987ea84..11b5fb2ec3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus)
 ENTRY(lowlevel_init)
  mov x29, lr /* Save LR */
 
+ /* unmask SError and abort */
+ msr daifclr, #4
+
+ /* Set HCR_EL2[AMO] so SError @EL2 is taken */
+ mrs x0, hcr_el2
+ orr x0, x0, #0x20 /* AMO */
+ msr hcr_el2, x0
+ isb
+
  switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
 1:
 
--
2.17.1

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[PATCH v4 06/27] armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
From: Pankit Garg <[hidden email]>

Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <[hidden email]>
Signed-off-by: Pankit Garg <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bae50f68d8..6304825180 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -371,7 +371,10 @@ static inline void early_mmu_setup(void)
  unsigned int el = current_el();
 
  /* global data is already setup, no allocation yet */
- gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+ if (el == 3)
+ gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+ else
+ gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
  gd->arch.tlb_fillptr = gd->arch.tlb_addr;
  gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 
--
2.17.1

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[PATCH v4 07/27] drivers: ifc: dynamic chipselect mapping support

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
From: Pankit Garg <[hidden email]>

IFC driver changes to implement the chipselect mappings at run time.

Defines init_early_memctl_regs and init_final_memctl_regs with
chipselect dynamic mapping for nor and nand boot.

Signed-off-by: Pankit Garg <[hidden email]>
Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 drivers/misc/fsl_ifc.c | 488 +++++++++++++++++++++++++++++------------
 include/fsl_ifc.h      |  17 ++
 2 files changed, 369 insertions(+), 136 deletions(-)

diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c
index 7d66c3cf76..2e3b43356e 100644
--- a/drivers/misc/fsl_ifc.c
+++ b/drivers/misc/fsl_ifc.c
@@ -7,185 +7,401 @@
 #include <common.h>
 #include <fsl_ifc.h>
 
-void print_ifc_regs(void)
-{
- int i, j;
-
- printf("IFC Controller Registers\n");
- for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
- printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
- i, get_ifc_cspr(i), i, get_ifc_amask(i),
- i, get_ifc_csor(i));
- for (j = 0; j < 4; j++)
- printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
- }
-}
-
-void init_early_memctl_regs(void)
-{
+struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
+        {
+ "cs0",
 #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
- set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
- set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
- set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
- set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
-
-#ifndef CONFIG_A003399_NOR_WORKAROUND
+ CONFIG_SYS_CSPR0,
 #ifdef CONFIG_SYS_CSPR0_EXT
- set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
-#endif
+ CONFIG_SYS_CSPR0_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK0
+ CONFIG_SYS_AMASK0,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR0,
+ {
+ CONFIG_SYS_CS0_FTIM0,
+ CONFIG_SYS_CS0_FTIM1,
+ CONFIG_SYS_CS0_FTIM2,
+ CONFIG_SYS_CS0_FTIM3,
+ },
 #ifdef CONFIG_SYS_CSOR0_EXT
- set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT);
+ CONFIG_SYS_CSOR0_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_CSPR0_FINAL
+ CONFIG_SYS_CSPR0_FINAL,
+#else
+ 0,
 #endif
- set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
- set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
- set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#ifdef CONFIG_SYS_AMASK0_FINAL
+ CONFIG_SYS_AMASK0_FINAL,
+#else
+ 0,
 #endif
 #endif
+ },
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2
+ {
+ "cs1",
+#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
+ CONFIG_SYS_CSPR1,
 #ifdef CONFIG_SYS_CSPR1_EXT
- set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
-#endif
+ CONFIG_SYS_CSPR1_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK1
+ CONFIG_SYS_AMASK1,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR1,
+ {
+ CONFIG_SYS_CS1_FTIM0,
+ CONFIG_SYS_CS1_FTIM1,
+ CONFIG_SYS_CS1_FTIM2,
+ CONFIG_SYS_CS1_FTIM3,
+ },
 #ifdef CONFIG_SYS_CSOR1_EXT
- set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT);
+ CONFIG_SYS_CSOR1_EXT,
+#else
+ 0,
 #endif
-#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
- set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
- set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
- set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
- set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
-
- set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
- set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
- set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
+#ifdef CONFIG_SYS_CSPR1_FINAL
+ CONFIG_SYS_CSPR1_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK1_FINAL
+ CONFIG_SYS_AMASK1_FINAL,
+#else
+ 0,
+#endif
+#endif
+ },
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3
+ {
+ "cs2",
+#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
+ CONFIG_SYS_CSPR2,
 #ifdef CONFIG_SYS_CSPR2_EXT
- set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
-#endif
+ CONFIG_SYS_CSPR2_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK2
+ CONFIG_SYS_AMASK2,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR2,
+ {
+ CONFIG_SYS_CS2_FTIM0,
+ CONFIG_SYS_CS2_FTIM1,
+ CONFIG_SYS_CS2_FTIM2,
+ CONFIG_SYS_CS2_FTIM3,
+ },
 #ifdef CONFIG_SYS_CSOR2_EXT
- set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT);
+ CONFIG_SYS_CSOR2_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_CSPR2_FINAL
+ CONFIG_SYS_CSPR2_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK2_FINAL
+ CONFIG_SYS_AMASK2_FINAL,
+#else
+ 0,
 #endif
-#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
- set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
- set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
- set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
- set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
-
- set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
- set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
- set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
+#endif
+ },
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4
+ {
+ "cs3",
+#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
+ CONFIG_SYS_CSPR3,
 #ifdef CONFIG_SYS_CSPR3_EXT
- set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
-#endif
+ CONFIG_SYS_CSPR3_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK3
+ CONFIG_SYS_AMASK3,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR3,
+ {
+ CONFIG_SYS_CS3_FTIM0,
+ CONFIG_SYS_CS3_FTIM1,
+ CONFIG_SYS_CS3_FTIM2,
+ CONFIG_SYS_CS3_FTIM3,
+ },
 #ifdef CONFIG_SYS_CSOR3_EXT
- set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT);
+ CONFIG_SYS_CSOR3_EXT,
+#else
+ 0,
 #endif
-#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
- set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
- set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
- set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
- set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
-
- set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
- set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
- set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
+#ifdef CONFIG_SYS_CSPR3_FINAL
+ CONFIG_SYS_CSPR3_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK3_FINAL
+ CONFIG_SYS_AMASK3_FINAL,
+#else
+ 0,
+#endif
+#endif
+ },
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5
+ {
+ "cs4",
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+ CONFIG_SYS_CSPR4,
 #ifdef CONFIG_SYS_CSPR4_EXT
- set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
-#endif
+ CONFIG_SYS_CSPR4_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK4
+ CONFIG_SYS_AMASK4,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR4,
+ {
+ CONFIG_SYS_CS4_FTIM0,
+ CONFIG_SYS_CS4_FTIM1,
+ CONFIG_SYS_CS4_FTIM2,
+ CONFIG_SYS_CS4_FTIM3,
+ },
 #ifdef CONFIG_SYS_CSOR4_EXT
- set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT);
+ CONFIG_SYS_CSOR4_EXT,
+#else
+ 0,
 #endif
-#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
- set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
- set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
- set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
- set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
-
- set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
- set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
- set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#ifdef CONFIG_SYS_CSPR4_FINAL
+ CONFIG_SYS_CSPR4_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK4_FINAL
+ CONFIG_SYS_AMASK4_FINAL,
+#else
+ 0,
+#endif
+#endif
+ },
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 6
+ {
+ "cs5",
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+ CONFIG_SYS_CSPR5,
 #ifdef CONFIG_SYS_CSPR5_EXT
- set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
-#endif
+ CONFIG_SYS_CSPR5_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK5
+ CONFIG_SYS_AMASK5,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR5,
+ {
+ CONFIG_SYS_CS5_FTIM0,
+ CONFIG_SYS_CS5_FTIM1,
+ CONFIG_SYS_CS5_FTIM2,
+ CONFIG_SYS_CS5_FTIM3,
+ },
 #ifdef CONFIG_SYS_CSOR5_EXT
- set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT);
+ CONFIG_SYS_CSOR5_EXT,
+#else
+ 0,
 #endif
-#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
- set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
- set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
- set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
- set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
-
- set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
- set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
- set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#ifdef CONFIG_SYS_CSPR5_FINAL
+ CONFIG_SYS_CSPR5_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK5_FINAL
+ CONFIG_SYS_AMASK5_FINAL,
+#else
+ 0,
+#endif
+#endif
+ },
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7
+ {
+ "cs6",
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+ CONFIG_SYS_CSPR6,
 #ifdef CONFIG_SYS_CSPR6_EXT
- set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
-#endif
+ CONFIG_SYS_CSPR6_EXT,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK6
+ CONFIG_SYS_AMASK6,
+#else
+ 0,
+#endif
+ CONFIG_SYS_CSOR6,
+ {
+ CONFIG_SYS_CS6_FTIM0,
+ CONFIG_SYS_CS6_FTIM1,
+ CONFIG_SYS_CS6_FTIM2,
+ CONFIG_SYS_CS6_FTIM3,
+ },
 #ifdef CONFIG_SYS_CSOR6_EXT
- set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT);
+ CONFIG_SYS_CSOR6_EXT,
+#else
+ 0,
 #endif
-#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
- set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
- set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
- set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
- set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
-
- set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
- set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
- set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#ifdef CONFIG_SYS_CSPR6_FINAL
+ CONFIG_SYS_CSPR6_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK6_FINAL
+ CONFIG_SYS_AMASK6_FINAL,
+#else
+ 0,
+#endif
+#endif
+ },
 #endif
 
+#if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8
+ {
+ "cs7",
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+ CONFIG_SYS_CSPR7,
 #ifdef CONFIG_SYS_CSPR7_EXT
- set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+ CONFIG_SYS_CSPR7_EXT,
+#else
+ 0,
 #endif
-#ifdef CONFIG_SYS_CSOR7_EXT
- set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT);
+#ifdef CONFIG_SYS_AMASK7
+ CONFIG_SYS_AMASK7,
+#else
+ 0,
 #endif
-#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
- set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
- set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
- set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
- set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+ CONFIG_SYS_CSOR7,
+#ifdef CONFIG_SYS_CSOR7_EXT
+ CONFIG_SYS_CSOR7_EXT,
+#else
+ 0,
+#endif
+ {
+ CONFIG_SYS_CS7_FTIM0,
+ CONFIG_SYS_CS7_FTIM1,
+ CONFIG_SYS_CS7_FTIM2,
+ CONFIG_SYS_CS7_FTIM3,
+ },
+#ifdef CONFIG_SYS_CSPR7_FINAL
+ CONFIG_SYS_CSPR7_FINAL,
+#else
+ 0,
+#endif
+#ifdef CONFIG_SYS_AMASK7_FINAL
+ CONFIG_SYS_AMASK7_FINAL,
+#else
+ 0,
+#endif
+#endif
+ },
+#endif
+};
 
- set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
- set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
- set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
-#endif
+__weak void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
+{
+ regs_info->regs = ifc_cfg_default_boot;
+ regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
+}
+
+void print_ifc_regs(void)
+{
+ int i, j;
+
+ printf("IFC Controller Registers\n");
+ for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
+ printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
+ i, get_ifc_cspr(i), i, get_ifc_amask(i),
+ i, get_ifc_csor(i));
+ for (j = 0; j < 4; j++)
+ printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
+ }
+}
+
+void init_early_memctl_regs(void)
+{
+ int i, j;
+ struct ifc_regs *regs;
+ struct ifc_regs_info regs_info = {0};
+
+ ifc_cfg_boot_info(&regs_info);
+ regs = regs_info.regs;
+
+ for (i = 0 ; i < regs_info.cs_size; i++) {
+ if (regs[i].pr && (regs[i].pr & CSPR_V)) {
+ /* skip setting cspr/csor_ext in below condition */
+ if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) && \
+ i == 0 && \
+ ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) {
+ if (regs[i].pr_ext)
+ set_ifc_cspr_ext(i, regs[i].pr_ext);
+ if (regs[i].or_ext)
+ set_ifc_csor_ext(i, regs[i].or_ext);
+ }
+
+ for (j = 0; j < ARRAY_SIZE(regs->ftim); j++)
+ set_ifc_ftim(i, j, regs[i].ftim[j]);
+
+ set_ifc_csor(i, regs[i].or);
+ set_ifc_amask(i, regs[i].amask);
+ set_ifc_cspr(i, regs[i].pr);
+ }
+ }
 }
 
 void init_final_memctl_regs(void)
 {
-#ifdef CONFIG_SYS_CSPR0_FINAL
- set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK0_FINAL
- set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
-#endif
-#ifdef CONFIG_SYS_CSPR1_FINAL
- set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK1_FINAL
- set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL);
-#endif
-#ifdef CONFIG_SYS_CSPR2_FINAL
- set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK2_FINAL
- set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
-#endif
-#ifdef CONFIG_SYS_CSPR3_FINAL
- set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL);
-#endif
-#ifdef CONFIG_SYS_AMASK3_FINAL
- set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
-#endif
+ int i;
+ struct ifc_regs *regs;
+ struct ifc_regs_info regs_info;
+
+ ifc_cfg_boot_info(&regs_info);
+ regs = regs_info.regs;
+
+ for (i = 0 ; i < regs_info.cs_size && i < ARRAY_SIZE(regs->ftim); i++) {
+ if (!(regs[i].pr_final & CSPR_V))
+ continue;
+ if (regs[i].pr_final)
+ set_ifc_cspr(i, regs[i].pr_final);
+ if (regs[i].amask_final)
+ set_ifc_amask(i, (i == 1) ? regs[i].amask_final :
+ regs[i].amask);
+ }
 }
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
index 17697c7341..c42affcf1f 100644
--- a/include/fsl_ifc.h
+++ b/include/fsl_ifc.h
@@ -1031,6 +1031,23 @@ struct fsl_ifc {
  struct fsl_ifc_runtime *rregs;
 };
 
+struct ifc_regs {
+ const char *name;
+ uint32_t pr;
+ uint32_t pr_ext;
+ uint32_t amask;
+ uint32_t or;
+ uint32_t ftim[4];
+ uint32_t or_ext;
+ uint32_t pr_final;
+ uint32_t amask_final;
+};
+
+struct ifc_regs_info {
+ struct ifc_regs *regs;
+ uint32_t cs_size;
+};
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #undef CSPR_MSEL_NOR
 #define CSPR_MSEL_NOR CSPR_MSEL_GPCM
--
2.17.1

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[PATCH v4 08/27] armv8: layerscape: Add TFABOOT support

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Adds TFABOOT support config option and add generic code to enable
execution from DDR.

Signed-off-by: York Sun <[hidden email]>
Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None
Change in v3:
 - Seperated TFABOOT generic code
 - Moved before dependency patches

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   | 9 ++++++---
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index f2111fadc0..9092757d1f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -514,3 +514,10 @@ config HAS_FSL_XHCI_USB
  help
   For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
   pins, select it when the pins are assigned to USB.
+
+config TFABOOT
+       bool "Support for booting from TFA"
+       default n
+       help
+         Enabling this will make a U-Boot binary that is capable of being
+         booted via TFA.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6304825180..3e084eddfa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -88,7 +88,8 @@ static struct mm_region early_map[] = {
 #endif
  { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
   CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
   PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
   PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -139,7 +140,8 @@ static struct mm_region early_map[] = {
 #endif
  { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
   CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_TFABOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
   PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
   PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
@@ -1236,7 +1238,8 @@ void update_early_mmu_table(void)
 __weak int dram_init(void)
 {
  fsl_initdram();
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
+ defined(CONFIG_SPL_BUILD)
  /* This will break-before-make MMU for DDR */
  update_early_mmu_table();
 #endif
--
2.17.1

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[PATCH v4 09/27] armv8: fsl-layerscape: identify boot source from PORSR register

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.

Further, it can be used to select the environment location.

Signed-off-by: Pankit Garg <[hidden email]>
Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c       | 190 ++++++++++++++++++
 .../asm/arch-fsl-layerscape/immap_lsch2.h     |  20 ++
 .../asm/arch-fsl-layerscape/immap_lsch3.h     |  49 +++++
 .../arm/include/asm/arch-fsl-layerscape/soc.h |  17 ++
 4 files changed, 276 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 3e084eddfa..5f56897ab0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -31,6 +31,10 @@
 #include <hwconfig.h>
 #include <fsl_qbman.h>
 
+#ifdef CONFIG_TFABOOT
+#include <environment.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct cpu_type cpu_type_list[] = {
@@ -581,7 +585,193 @@ void enable_caches(void)
  icache_enable();
  dcache_enable();
 }
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+#ifdef CONFIG_TFABOOT
+enum boot_src __get_boot_src(u32 porsr1)
+{
+ enum boot_src src = BOOT_SOURCE_RESERVED;
+ uint32_t rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
+#if !defined(CONFIG_FSL_LSCH3_2)
+ uint32_t val;
+#endif
+ debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
+
+#if defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_FSL_LSCH3_2)
+ switch (rcw_src) {
+ case RCW_SRC_SDHC1_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_SDHC2_VAL:
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ case RCW_SRC_FLEXSPI_NAND2K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_FLEXSPI_NAND4K_VAL:
+ src = BOOT_SOURCE_XSPI_NAND;
+ break;
+ case RCW_SRC_RESERVED_1_VAL:
+ src = BOOT_SOURCE_RESERVED;
+ break;
+ case RCW_SRC_FLEXSPI_NOR_24B:
+ src = BOOT_SOURCE_XSPI_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+#else
+ val = rcw_src & RCW_SRC_TYPE_MASK;
+ if (val == RCW_SRC_NOR_VAL) {
+ val = rcw_src & NOR_TYPE_MASK;
+
+ switch (val) {
+ case NOR_16B_VAL:
+ case NOR_32B_VAL:
+ src = BOOT_SOURCE_IFC_NOR;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ } else {
+ /* RCW SRC Serial Flash */
+ val = rcw_src & RCW_SRC_SERIAL_MASK;
+ switch (val) {
+ case RCW_SRC_QSPI_VAL:
+ /* RCW SRC Serial NOR (QSPI) */
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case RCW_SRC_SD_CARD_VAL:
+ /* RCW SRC SD Card */
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ case RCW_SRC_EMMC_VAL:
+ /* RCW SRC EMMC */
+ src = BOOT_SOURCE_SD_MMC2;
+ break;
+ case RCW_SRC_I2C1_VAL:
+ /* RCW SRC I2C1 Extended */
+ src = BOOT_SOURCE_I2C1_EXTENDED;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+#endif
+#elif defined(CONFIG_FSL_LSCH2)
+ /* RCW SRC NAND */
+ val = rcw_src & RCW_SRC_NAND_MASK;
+ if (val == RCW_SRC_NAND_VAL) {
+ val = rcw_src & NAND_RESERVED_MASK;
+ if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
+ src = BOOT_SOURCE_IFC_NAND;
+ }
+ } else {
+ /* RCW SRC NOR */
+ val = rcw_src & RCW_SRC_NOR_MASK;
+ if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
+ src = BOOT_SOURCE_IFC_NOR;
+ } else {
+ switch (rcw_src) {
+ case QSPI_VAL1:
+ case QSPI_VAL2:
+ src = BOOT_SOURCE_QSPI_NOR;
+ break;
+ case SD_VAL:
+ src = BOOT_SOURCE_SD_MMC;
+ break;
+ default:
+ src = BOOT_SOURCE_RESERVED;
+ }
+ }
+ }
 #endif
+ debug("%s: src 0x%x\n", __func__, src);
+ return src;
+}
+
+enum boot_src get_boot_src(void)
+{
+ u32 porsr1;
+
+#if defined(CONFIG_FSL_LSCH3)
+ u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ porsr1 = in_be32(&gur->porsr1);
+#endif
+ debug("%s: porsr1 0x%x\n", __func__, porsr1);
+
+ return __get_boot_src(porsr1);
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+int mmc_get_env_dev(void)
+{
+ enum boot_src src = get_boot_src();
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+ switch (src) {
+ case BOOT_SOURCE_SD_MMC:
+ dev = 0;
+ break;
+ case BOOT_SOURCE_SD_MMC2:
+ dev = 1;
+ break;
+ default:
+ break;
+ }
+
+ return dev;
+}
+#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_src src = get_boot_src();
+ enum env_location env_loc = ENVL_NOWHERE;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (src) {
+ case BOOT_SOURCE_IFC_NOR:
+ env_loc = ENVL_FLASH;
+ break;
+ case BOOT_SOURCE_QSPI_NOR:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_XSPI_NOR:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+ case BOOT_SOURCE_IFC_NAND:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_QSPI_NAND:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_XSPI_NAND:
+ env_loc = ENVL_NAND;
+ break;
+ case BOOT_SOURCE_SD_MMC:
+ /* FALLTHROUGH */
+ case BOOT_SOURCE_SD_MMC2:
+ env_loc =  ENVL_MMC;
+ break;
+ case BOOT_SOURCE_I2C1_EXTENDED:
+ /* FALLTHROUGH */
+ default:
+ break;
+ }
+
+
+ return env_loc;
+}
+#endif /* CONFIG_TFABOOT */
 
 u32 initiator_type(u32 cluster, int init_id)
 {
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8c10526a6c..4d0f16f21c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -677,6 +677,26 @@ struct ccsr_gpio {
 #define SCR0_CLIENTPD_MASK 0x00000001
 #define SCR0_USFCFG_MASK 0x00000400
 
+#ifdef CONFIG_TFABOOT
+#define RCW_SRC_MASK (0xFF800000)
+#define RCW_SRC_BIT 23
+
+/* RCW SRC NAND */
+#define RCW_SRC_NAND_MASK (0x100)
+#define RCW_SRC_NAND_VAL (0x100)
+#define NAND_RESERVED_MASK (0xFC)
+#define NAND_RESERVED_1 (0x0)
+#define NAND_RESERVED_2 (0x80)
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_MASK (0x1F0)
+#define NOR_8B_VAL (0x10)
+#define NOR_16B_VAL (0x20)
+#define SD_VAL (0x40)
+#define QSPI_VAL1 (0x44)
+#define QSPI_VAL2 (0x45)
+#endif
+
 uint get_svr(void);
 
 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index b0cec74db0..816d960b2f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -82,6 +82,55 @@
 #define CONFIG_SYS_FSL_JR0_ADDR \
  (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_FSL_LSCH3_2
+/* RCW_SRC field in Power-On Reset Control Register 1 */
+#define RCW_SRC_MASK 0x07800000
+#define RCW_SRC_BIT 23
+
+/* CFG_RCW_SRC[3:0] */
+#define RCW_SRC_TYPE_MASK 0x8
+#define RCW_SRC_ADDR_OFFSET_8MB 0x800000
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL 0x0 /* 0x00 - 0x07 */
+
+#define RCW_SRC_SDHC1_VAL 0x8 /* 0x8 */
+#define RCW_SRC_SDHC2_VAL 0x9 /* 0x9 */
+#define RCW_SRC_I2C1_VAL 0xa /* 0xa */
+#define RCW_SRC_RESERVED_UART_VAL 0xb /* 0xb */
+#define RCW_SRC_FLEXSPI_NAND2K_VAL   0xc /* 0xc */
+#define RCW_SRC_FLEXSPI_NAND4K_VAL 0xd /* 0xd */
+#define RCW_SRC_RESERVED_1_VAL 0xe /* 0xe */
+#define RCW_SRC_FLEXSPI_NOR_24B 0xf /* 0xf */
+#else
+#define RCW_SRC_MASK (0xFF800000)
+#define RCW_SRC_BIT 23
+/* CFG_RCW_SRC[6:0] */
+#define RCW_SRC_TYPE_MASK               (0x70)
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL           (0x10)     /* 0x10 - 0x1f */
+/* Hardcoded will also have CFG_RCW_SRC[7] as 1.   0x90 - 0x9f */
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_VAL                 (0x20)
+#define NOR_TYPE_MASK                   (0x10)
+#define NOR_16B_VAL                     (0x0)       /* 0x20 - 0x2f */
+#define NOR_32B_VAL                     (0x10)       /* 0x30 - 0x3f */
+
+/* RCW SRC Serial Flash
+ * 1. SERIAL NOR (QSPI)
+ * 2. OTHERS (SD/MMC, SPI, I2C1
+ */
+#define RCW_SRC_SERIAL_MASK             (0x7F)
+#define RCW_SRC_QSPI_VAL                (0x62)     /* 0x62 */
+#define RCW_SRC_SD_CARD_VAL             (0x40)     /* 0x40 */
+#define RCW_SRC_EMMC_VAL                (0x41)     /* 0x41 */
+#define RCW_SRC_I2C1_VAL                (0x49)     /* 0x49 */
+#endif
+#endif
+
 /* Security Monitor */
 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 61b6e4bf07..d327c7ba1f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -53,6 +53,23 @@ struct cpu_type {
 
 #define CPU_TYPE_ENTRY(n, v, nc) \
  { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#ifdef CONFIG_TFABOOT
+enum boot_src {
+ BOOT_SOURCE_RESERVED = 0,
+ BOOT_SOURCE_IFC_NOR,
+ BOOT_SOURCE_IFC_NAND,
+ BOOT_SOURCE_QSPI_NOR,
+ BOOT_SOURCE_QSPI_NAND,
+ BOOT_SOURCE_XSPI_NOR,
+ BOOT_SOURCE_XSPI_NAND,
+ BOOT_SOURCE_SD_MMC,
+ BOOT_SOURCE_SD_MMC2,
+ BOOT_SOURCE_I2C1_EXTENDED,
+};
+
+enum boot_src get_boot_src(void);
+#endif
 #endif
 #define SVR_WO_E 0xFFFFFE
 #define SVR_LS1012A 0x870400
--
2.17.1

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[PATCH v4 10/27] armv8: layerscape: remove EL3 specific erratas for TFABOOT

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA.

ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511,
SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803
SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165

Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9092757d1f..1872c66dcd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -1,7 +1,7 @@
 config ARCH_LS1012A
  bool
  select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
+ select ARM_ERRATA_855873 if !TFABOOT
  select FSL_LSCH2
  select SYS_FSL_SRDS_1
  select SYS_HAS_SERDES
@@ -22,22 +22,22 @@ config ARCH_LS1012A
 config ARCH_LS1043A
  bool
  select ARMV8_SET_SMPEN
- select ARM_ERRATA_855873
+ select ARM_ERRATA_855873 if !TFABOOT
  select FSL_LSCH2
  select SYS_FSL_SRDS_1
  select SYS_HAS_SERDES
  select SYS_FSL_DDR
  select SYS_FSL_DDR_BE
  select SYS_FSL_DDR_VER_50
- select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  select SYS_FSL_ERRATUM_A008997
  select SYS_FSL_ERRATUM_A009007
  select SYS_FSL_ERRATUM_A009008
- select SYS_FSL_ERRATUM_A009660
- select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009660 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009663 if !TFABOOT
  select SYS_FSL_ERRATUM_A009798
  select SYS_FSL_ERRATUM_A009929
- select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A009942 if !TFABOOT
  select SYS_FSL_ERRATUM_A010315
  select SYS_FSL_ERRATUM_A010539
  select SYS_FSL_HAS_DDR3
@@ -62,17 +62,17 @@ config ARCH_LS1046A
  select SYS_FSL_DDR
  select SYS_FSL_DDR_BE
  select SYS_FSL_DDR_VER_50
- select SYS_FSL_ERRATUM_A008336
- select SYS_FSL_ERRATUM_A008511
- select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A008336 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+ select SYS_FSL_ERRATUM_A008850 if !TFABOOT
  select SYS_FSL_ERRATUM_A008997
  select SYS_FSL_ERRATUM_A009007
  select SYS_FSL_ERRATUM_A009008
  select SYS_FSL_ERRATUM_A009798
  select SYS_FSL_ERRATUM_A009801
- select SYS_FSL_ERRATUM_A009803
- select SYS_FSL_ERRATUM_A009942
- select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+ select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+ select SYS_FSL_ERRATUM_A010165 if !TFABOOT
  select SYS_FSL_ERRATUM_A010539
  select SYS_FSL_HAS_DDR4
  select SYS_FSL_SRDS_2
--
2.17.1

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[PATCH v4 11/27] armv8: fsl-layerscape: bootcmd identification for TFABOOT

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
From: Pankit Garg <[hidden email]>

Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.

Signed-off-by: Rajesh Bhagat <[hidden email]>
Signed-off-by: Pankit Garg <[hidden email]>
---
Change in v4: None
 
Change in v3:
 - Merged secure boot bootcmd changes

Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 +++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 78 +++++++++++++++++++++++++
 2 files changed, 92 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 5f56897ab0..6c1b1ffec8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -33,6 +33,9 @@
 
 #ifdef CONFIG_TFABOOT
 #include <environment.h>
+#ifdef CONFIG_CHAIN_OF_TRUST
+#include <fsl_validate.h>
+#endif
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -741,6 +744,14 @@ enum env_location env_get_location(enum env_operation op, int prio)
  if (prio)
  return ENVL_UNKNOWN;
 
+#ifdef CONFIG_CHAIN_OF_TRUST
+ /* Check Boot Mode
+ * If Boot Mode is Secure, return ENVL_NOWHERE
+ */
+ if (fsl_check_boot_mode_secure() == 1)
+ goto done;
+#endif
+
  switch (src) {
  case BOOT_SOURCE_IFC_NOR:
  env_loc = ENVL_FLASH;
@@ -768,6 +779,9 @@ enum env_location env_get_location(enum env_operation op, int prio)
  break;
  }
 
+#ifdef CONFIG_CHAIN_OF_TRUST
+done:
+#endif
 
  return env_loc;
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 54fb0745f9..b68d99c765 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -24,6 +24,10 @@
 #include <fsl_validate.h>
 #endif
 #include <fsl_immap.h>
+#ifdef CONFIG_TFABOOT
+#include <environment.h>
+DECLARE_GLOBAL_DATA_PTR;
+#endif
 
 bool soc_has_dp_ddr(void)
 {
@@ -679,12 +683,86 @@ int qspi_ahb_init(void)
 }
 #endif
 
+#ifdef CONFIG_TFABOOT
+#define MAX_BOOTCMD_SIZE 256
+
+int fsl_setenv_bootcmd(void)
+{
+ int ret;
+ enum boot_src src = get_boot_src();
+ char bootcmd_str[MAX_BOOTCMD_SIZE];
+
+ switch (src) {
+#ifdef IFC_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NOR:
+ sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NOR:
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NOR_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NOR:
+ sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
+ break;
+#endif
+#ifdef IFC_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_IFC_NAND:
+ sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef QSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_QSPI_NAND:
+ sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef XSPI_NAND_BOOTCOMMAND
+ case BOOT_SOURCE_XSPI_NAND:
+ sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC:
+ sprintf(bootcmd_str, SD_BOOTCOMMAND);
+ break;
+#endif
+#ifdef SD2_BOOTCOMMAND
+ case BOOT_SOURCE_SD_MMC2:
+ sprintf(bootcmd_str, SD2_BOOTCOMMAND);
+ break;
+#endif
+ default:
+#ifdef QSPI_NOR_BOOTCOMMAND
+ sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
+#endif
+ break;
+ }
+
+ ret = env_set("bootcmd", bootcmd_str);
+ if (ret) {
+ printf("Failed to set bootcmd: ret = %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
 #ifdef CONFIG_CHAIN_OF_TRUST
  fsl_setenv_chain_of_trust();
 #endif
+#ifdef CONFIG_TFABOOT
+ /*
+ * check if gd->env_addr is default_environment; then setenv bootcmd
+ */
+ if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
+ fsl_setenv_bootcmd();
+ }
+#endif
 #ifdef CONFIG_QSPI_AHB_INIT
  qspi_ahb_init();
 #endif
--
2.17.1

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[PATCH v4 12/27] armv8: layerscape: add SMC calls for DDR size and bank info

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Adds SMC calls for getting DDR size and bank info for TFABOOT.

Signed-off-by: Rajesh Bhagat <[hidden email]>
Signed-off-by: Pankit Garg <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c       | 84 +++++++++++++++++++
 .../arm/include/asm/arch-fsl-layerscape/soc.h |  4 +
 2 files changed, 88 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6c1b1ffec8..ca5329f25c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1230,12 +1230,96 @@ phys_size_t get_effective_memsize(void)
  return ea_size;
 }
 
+#ifdef CONFIG_TFABOOT
+phys_size_t tfa_get_dram_size(void)
+{
+ struct pt_regs regs;
+ phys_size_t dram_size = 0;
+
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = -1;
+
+ smc_call(&regs);
+ if (regs.regs[0])
+ return 0;
+
+ dram_size = regs.regs[1];
+ return dram_size;
+}
+
+static int tfa_dram_init_banksize(void)
+{
+ int i = 0, ret = 0;
+ struct pt_regs regs;
+ phys_size_t dram_size = tfa_get_dram_size();
+
+ debug("dram_size %llx\n", dram_size);
+
+ if (!dram_size)
+ return -EINVAL;
+
+ do {
+ regs.regs[0] = SMC_DRAM_BANK_INFO;
+ regs.regs[1] = i;
+
+ smc_call(&regs);
+ if (regs.regs[0]) {
+ ret = -EINVAL;
+ break;
+ }
+
+ debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
+      regs.regs[2]);
+ gd->bd->bi_dram[i].start = regs.regs[1];
+ gd->bd->bi_dram[i].size = regs.regs[2];
+
+ dram_size -= gd->bd->bi_dram[i].size;
+
+ i++;
+ } while (dram_size);
+
+ if (i > 0)
+ ret = 0;
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+ /* Assign memory for MC */
+#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
+ if (gd->bd->bi_dram[2].size >=
+    board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[2].start +
+    gd->bd->bi_dram[2].size -
+    board_reserve_ram_top(gd->bd->bi_dram[2].size);
+ } else
+#endif
+ {
+ if (gd->bd->bi_dram[1].size >=
+    board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[1].start +
+ gd->bd->bi_dram[1].size -
+ board_reserve_ram_top(gd->bd->bi_dram[1].size);
+ } else if (gd->bd->bi_dram[0].size >
+   board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
+ gd->arch.resv_ram = gd->bd->bi_dram[0].start +
+ gd->bd->bi_dram[0].size -
+ board_reserve_ram_top(gd->bd->bi_dram[0].size);
+ }
+ }
+#endif /* CONFIG_FSL_MC_ENET */
+
+ return ret;
+}
+#endif
+
 int dram_init_banksize(void)
 {
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  phys_size_t dp_ddr_size;
 #endif
 
+#ifdef CONFIG_TFABOOT
+ if (!tfa_dram_init_banksize())
+ return 0;
+#endif
  /*
  * gd->ram_size has the total size of DDR memory, less reserved secure
  * memory. The DDR extends from low region to high region(s) presuming
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index d327c7ba1f..ef228b6443 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -55,6 +55,10 @@ struct cpu_type {
  { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #ifdef CONFIG_TFABOOT
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+phys_size_t tfa_get_dram_size(void);
+
 enum boot_src {
  BOOT_SOURCE_RESERVED = 0,
  BOOT_SOURCE_IFC_NOR,
--
2.17.1

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[PATCH v4 13/27] armv8: layerscape: skip OCRAM init for TFABOOT

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
OCRAM initialization is performed by TFA, Hence
skipped from u-boot.

Signed-off-by: Ruchika Gupta <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 11b5fb2ec3..cbc9112eb1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -304,7 +304,8 @@ ENTRY(lowlevel_init)
 100:
 #endif
 
-#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_TFABOOT) && \
+ (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
  bl fsl_ocram_init
 #endif
 
--
2.17.1

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[PATCH v4 14/27] armv8: fsl-layerscape: Update parsing boot source

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
From: York Sun <[hidden email]>

Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.

Signed-off-by: York Sun <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c       | 26 ++++++++++++++++---
 .../arm/include/asm/arch-fsl-layerscape/soc.h |  1 +
 2 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ca5329f25c..2e3494bee4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -693,23 +693,41 @@ enum boot_src __get_boot_src(u32 porsr1)
  }
  }
 #endif
+
+ if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
+ src = BOOT_SOURCE_QSPI_NOR;
+
  debug("%s: src 0x%x\n", __func__, src);
  return src;
 }
 
 enum boot_src get_boot_src(void)
 {
- u32 porsr1;
+ struct pt_regs regs;
+ u32 porsr1 = 0;
 
 #if defined(CONFIG_FSL_LSCH3)
  u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
-
- porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 #elif defined(CONFIG_FSL_LSCH2)
  struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#endif
+
+ if (current_el() == 2) {
+ regs.regs[0] = SIP_SVC_RCW;
 
- porsr1 = in_be32(&gur->porsr1);
+ smc_call(&regs);
+ if (!regs.regs[0])
+ porsr1 = regs.regs[1];
+ }
+
+ if (current_el() == 3 || !porsr1) {
+#ifdef CONFIG_FSL_LSCH3
+ porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+#elif defined(CONFIG_FSL_LSCH2)
+ porsr1 = in_be32(&gur->porsr1);
 #endif
+ }
+
  debug("%s: porsr1 0x%x\n", __func__, porsr1);
 
  return __get_boot_src(porsr1);
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index ef228b6443..daa1c70b3a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -56,6 +56,7 @@ struct cpu_type {
 
 #ifdef CONFIG_TFABOOT
 #define SMC_DRAM_BANK_INFO (0xC200FF12)
+#define SIP_SVC_RCW 0xC200FF18
 
 phys_size_t tfa_get_dram_size(void);
 
--
2.17.1

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[PATCH v4 15/27] armv8: sec_firmware: change el2_to_aarch32 SMC ID

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17,
it is applicable to both TFA and non-TFA boot.

Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 1c0f963e18..af1b2da072 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -68,7 +68,7 @@ ENTRY(armv8_el2_to_aarch32)
  mov x3, x2
  mov x2, x1
  mov x1, x4
- ldr x0, =0xc000ff04
+ ldr x0, =0xc200ff17
  smc #0
  ret
 ENDPROC(armv8_el2_to_aarch32)
--
2.17.1

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[PATCH v4 16/27] armv8: sec_firmware: return job ring status as true in TFABOOT

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
From: Pankit Garg <[hidden email]>

Returns job ring status as true in TFABOOT, as one job ring is always
reserved.

Signed-off-by: Ruchika Gupta <[hidden email]>
Signed-off-by: Pankit Garg <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/sec_firmware.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index a13c92e246..8dc0ac9266 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -348,6 +348,10 @@ unsigned int sec_firmware_support_psci_version(void)
  */
 bool sec_firmware_support_hwrng(void)
 {
+#ifdef CONFIG_TFABOOT
+ /* return true as TFA has one job ring reserved */
+ return true;
+#endif
  if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
  return true;
  }
--
2.17.1

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[PATCH v4 17/27] net: fm: add TFABOOT support

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.

Signed-off-by: Pankit Garg <[hidden email]>
Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None

Change in v3: None
 
Change in v2:                                                                  
 - Removed extra CONFIG_TFABOOT flag usage

 drivers/net/fm/fm.c | 102 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 98 insertions(+), 4 deletions(-)

diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index c5cf188f05..768d4a9241 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -11,13 +11,13 @@
 #include "fm.h"
 #include <fsl_qe.h> /* For struct qe_firmware */
 
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
-#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
 #include <spi_flash.h>
-#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
 #include <mmc.h>
-#endif
+/* required to include IFC and QSPI base address */
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
+#include <environment.h>
 
 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
 
@@ -347,6 +347,99 @@ static void fm_init_qmi(struct fm_qmi_common *qmi)
 }
 
 /* Init common part of FM, index is fm num# like fm as above */
+#ifdef CONFIG_TFABOOT
+int fm_init_common(int index, struct ccsr_fman *reg)
+{
+ int rc;
+ void *addr = NULL;
+ enum boot_src src = get_boot_src();
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
+ CONFIG_SYS_FSL_IFC_BASE);
+ } else if (src == BOOT_SOURCE_IFC_NAND) {
+ size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+
+ rc = nand_read(get_nand_dev_by_index(0),
+       (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+       &fw_length, (u_char *)addr);
+ if (rc == -EUCLEAN) {
+ printf("NAND read of FMAN firmware at offset 0x%x\
+       failed %d\n", CONFIG_SYS_FMAN_FW_ADDR, rc);
+ }
+ } else if (src == BOOT_SOURCE_QSPI_NOR) {
+ struct spi_flash *ucode_flash;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ int ret = 0;
+
+#ifdef CONFIG_DM_SPI_FLASH
+ struct udevice *new;
+
+ /* speed and mode will be read from DT */
+ ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
+     CONFIG_ENV_SPI_CS, 0, 0, &new);
+
+ ucode_flash = dev_get_uclass_priv(new);
+#else
+ ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
+      CONFIG_ENV_SPI_CS,
+      CONFIG_ENV_SPI_MAX_HZ,
+      CONFIG_ENV_SPI_MODE);
+#endif
+ if (!ucode_flash)
+ printf("SF: probe for ucode failed\n");
+ else {
+ ret = spi_flash_read(ucode_flash,
+     CONFIG_SYS_FMAN_FW_ADDR +
+     CONFIG_SYS_FSL_QSPI_BASE,
+     CONFIG_SYS_QE_FMAN_FW_LENGTH,
+     addr);
+ if (ret)
+ printf("SF: read for ucode failed\n");
+ spi_flash_free(ucode_flash);
+ }
+ } else if (src == BOOT_SOURCE_SD_MMC) {
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc)
+ printf("\nMMC cannot find device for ucode\n");
+ else {
+ printf("\nMMC read: dev # %u, block # %u, count %u \
+       ...\n", dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk,
+ cnt, addr);
+ }
+ } else
+ addr = NULL;
+
+ /* Upload the Fman microcode if it's present */
+ rc = fman_upload_firmware(index, &reg->fm_imem, addr);
+ if (rc)
+ return rc;
+ env_set_addr("fman_ucode", addr);
+
+ fm_init_muram(index, &reg->muram);
+ fm_init_qmi(&reg->fm_qmi_common);
+ fm_init_fpm(&reg->fm_fpm);
+
+ /* clear DMA status */
+ setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
+
+ /* set DMA mode */
+ setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
+
+ return fm_init_bmi(index, &reg->fm_bmi_common);
+}
+#else
 int fm_init_common(int index, struct ccsr_fman *reg)
 {
  int rc;
@@ -429,3 +522,4 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 
  return fm_init_bmi(index, &reg->fm_bmi_common);
 }
+#endif
--
2.17.1

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[PATCH v4 18/27] drivers: qe: add TFABOOT support

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
Adds TFABOOT support and allows to pick QE firmware
on basis of boot source.

Signed-off-by: Pankit Garg <[hidden email]>
Signed-off-by: Rajesh Bhagat <[hidden email]>
---
Change in v4: None                                                              

Change in v3: None                                                              
                                                                               
Change in v2:                                                                  
 - Removed extra CONFIG_TFABOOT flag usage

 drivers/qe/qe.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 7010bbc230..daefb5aa07 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -17,9 +17,17 @@
 #include <asm/arch/immap_ls102xa.h>
 #endif
 
+#ifdef CONFIG_TFABOOT
+#include <mmc.h>
+/* required to include IFC and QSPI base address */
+#include <asm/armv8/mmu.h>
+#include <asm/arch/cpu.h>
+#include <environment.h>
+#else
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #include <mmc.h>
 #endif
+#endif
 
 #define MPC85xx_DEVDISR_QE_DISABLE 0x1
 
@@ -170,6 +178,33 @@ void qe_put_snum(u8 snum)
  }
 }
 
+#ifdef CONFIG_TFABOOT
+void qe_init(uint qe_base)
+{
+ enum boot_src src = get_boot_src();
+
+ /* Init the QE IMMR base */
+ qe_immr = (qe_map_t *)qe_base;
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ /*
+ * Upload microcode to IRAM for those SOCs
+ * which do not have ROM in QE.
+ */
+ qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
+   CONFIG_SYS_FSL_IFC_BASE));
+
+ /* enable the microcode in IRAM */
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ }
+
+ gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
+ gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
+
+ qe_sdma_init();
+ qe_snums_init();
+}
+#else
 void qe_init(uint qe_base)
 {
  /* Init the QE IMMR base */
@@ -192,8 +227,53 @@ void qe_init(uint qe_base)
  qe_snums_init();
 }
 #endif
+#endif
 
 #ifdef CONFIG_U_QE
+#ifdef CONFIG_TFABOOT
+void u_qe_init(void)
+{
+ enum boot_src src = get_boot_src();
+
+ qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
+
+ void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
+
+ if (src == BOOT_SOURCE_IFC_NOR) {
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
+ }
+ if (src == BOOT_SOURCE_QSPI_NOR) {
+ addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
+ }
+ if (src == BOOT_SOURCE_SD_MMC) {
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+ u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
+ u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
+
+ if (mmc_initialize(gd->bd)) {
+ printf("%s: mmc_initialize() failed\n", __func__);
+ return;
+ }
+ addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
+ struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+
+ if (!mmc) {
+ free(addr);
+ printf("\nMMC cannot find device for ucode\n");
+ } else {
+ printf("\nMMC read: dev # %u, block # %u,\
+       count %u ...\n", dev, blk, cnt);
+ mmc_init(mmc);
+ (void)mmc->block_dev.block_read(&mmc->block_dev, blk,
+ cnt, addr);
+ }
+ }
+ if (!u_qe_upload_firmware(addr))
+ out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+ if (src == BOOT_SOURCE_SD_MMC)
+ free(addr);
+}
+#else
 void u_qe_init(void)
 {
  qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
@@ -229,6 +309,7 @@ void u_qe_init(void)
 #endif
 }
 #endif
+#endif
 
 #ifdef CONFIG_U_QE
 void u_qe_resume(void)
--
2.17.1

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[PATCH v4 19/27] armv8: fsl-layerscape: add support of MC framework for TFA

Rajesh Bhagat-2
In reply to this post by Rajesh Bhagat-2
From: Pankit Garg <[hidden email]>

Add support of MC framework for TFA
Make MC framework independent of boot source.

Signed-off-by: Rajesh Bhagat <[hidden email]>
Signed-off-by: Pankit Garg <[hidden email]>
---
Change in v4: None
Change in v3: None
Change in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 50 +++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b68d99c765..0092a22394 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -747,6 +747,54 @@ int fsl_setenv_bootcmd(void)
  }
  return 0;
 }
+
+int fsl_setenv_mcinitcmd(void)
+{
+ int ret = 0;
+ enum boot_src src = get_boot_src();
+
+ switch (src) {
+#ifdef IFC_MC_INIT_CMD
+ case BOOT_SOURCE_IFC_NAND:
+ case BOOT_SOURCE_IFC_NOR:
+ ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
+ break;
+#endif
+#ifdef QSPI_MC_INIT_CMD
+ case BOOT_SOURCE_QSPI_NAND:
+ case BOOT_SOURCE_QSPI_NOR:
+ ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
+ break;
+#endif
+#ifdef XSPI_MC_INIT_CMD
+ case BOOT_SOURCE_XSPI_NAND:
+ case BOOT_SOURCE_XSPI_NOR:
+ ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
+ break;
+#endif
+#ifdef SD_MC_INIT_CMD
+ case BOOT_SOURCE_SD_MMC:
+ ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
+ break;
+#endif
+#ifdef SD2_MC_INIT_CMD
+ case BOOT_SOURCE_SD_MMC2:
+ ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
+ break;
+#endif
+ default:
+#ifdef QSPI_MC_INIT_CMD
+ ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
+#endif
+ break;
+ }
+
+ if (ret) {
+ printf("Failed to set mcinitcmd: ret = %d\n", ret);
+ return ret;
+ }
+ return 0;
+}
 #endif
 
 #ifdef CONFIG_BOARD_LATE_INIT
@@ -758,9 +806,11 @@ int board_late_init(void)
 #ifdef CONFIG_TFABOOT
  /*
  * check if gd->env_addr is default_environment; then setenv bootcmd
+ * and mcinitcmd.
  */
  if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
  fsl_setenv_bootcmd();
+ fsl_setenv_mcinitcmd();
  }
 #endif
 #ifdef CONFIG_QSPI_AHB_INIT
--
2.17.1

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