[PATCH v4 00/13] riscv: Add SPI support for Kendryte K210

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[PATCH v4 00/13] riscv: Add SPI support for Kendryte K210

Sean Anderson
This series adds support for SPI on the Kendryte K210. This covers the MMC
slot and SPI flash on the Sipeed Maix Bit.

This series makes significant changes to the designware SPI driver. I would
really appreciate if the maintainers I CC'd could test this series and ensure
that SPI still works on all their devices. I have tried my best not to affect
existing devices, but I'd rather find out if this breaks stuff now rather than
later. In particular, the method of detecting SSI_MAX_XFER_SIZE has changed
since the last revision, and will need to be re-tested.

This series was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576

Changes in v4:
- Auto-detect SSI_MAX_XFER_SIZE
- Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
  short succession.
- Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
  name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
  way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
  reduce the amount of instructions in those loops, even with logging enabled.
- Enable booting from MMC
- Fix MMC transfer errors
- Place env in spi flash
- Rearrange headers in designware_spi.c
- Remove spi_enable_chip
- Update documentation

Changes in v3:
- Lower the log level of some messages
- Prefix user-facing logs with SPI@<address>
- Rebase onto U-Boot master
- Remove env and bootcmd configuration. I'm going to punt on those for now,
  since I haven't worked out the best way to boot with SPI yet. Those
  settings may be added back in a follow-up patch.
- Reword error messages as "message (error %d)"
- Synchronize compatible strings between docs and driver
- Use constant 0x10000 instead of SZ_64K. The latter is not included on
  some platforms and I'm too lazy to figure out what the correct header is.

Changes in v2:
- Add Gigadevice SPI chips to dependencies
- Add external gpio cs support
- Clean up exec_op
- Configure ctrlr0 register layout based on compatible string
- Convert debug calls to log_ instead of removing the ones which affect
  timing
- Document new compatible strings
- Limit data transfers to 64k
- Remove broken-wp property (implicit due to no wp gpio)
- Remove ctrl0 field offsets from device tree
- Switch to new compatible strings
- Switch to new pinmux binding style

Sean Anderson (13):
  spi: dw: Fix driving MOSI low while recieving
  spi: dw: Convert calls to debug to dev_*
  spi: dw: Rename "cs-gpio" to "cs-gpios"
  spi: dw: Use generic function to read reg address
  spi: dw: Rename registers to match datasheet
  spi: dw: Remove spi_enable_chip
  spi: dw: Rearrange struct dw_spi_priv
  spi: dw: Add SoC-specific compatible strings
  spi: dw: Add support for multiple CTRLR0 layouts
  spi: dw: Document devicetree binding
  spi: dw: Add mem_ops
  riscv: Add device tree bindings for SPI
  riscv: Add support for SPI on Kendryte K210

 arch/arc/dts/axs10x_mb.dtsi                   |   5 +-
 arch/arc/dts/hsdk-common.dtsi                 |   5 +-
 arch/arm/dts/socfpga.dtsi                     |   6 +-
 arch/arm/dts/socfpga_agilex.dtsi              |   6 +-
 arch/arm/dts/socfpga_arria10.dtsi             |   6 +-
 arch/arm/dts/socfpga_stratix10.dtsi           |   6 +-
 arch/mips/dts/mscc,jr2.dtsi                   |   2 +-
 arch/mips/dts/mscc,ocelot.dtsi                |   2 +-
 arch/riscv/dts/k210-maix-bit.dts              |  46 +-
 arch/riscv/dts/k210.dtsi                      |  15 +-
 board/sipeed/maix/Kconfig                     |  16 +
 configs/sipeed_maix_bitm_defconfig            |  10 +
 doc/board/sipeed/maix.rst                     | 319 +++++++++++---
 .../spi/snps,dw-apb-ssi.txt                   |  56 +++
 drivers/spi/designware_spi.c                  | 401 ++++++++++++++----
 include/configs/sipeed-maix.h                 |   7 +-
 16 files changed, 743 insertions(+), 165 deletions(-)
 create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt

--
2.28.0

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[PATCH v4 01/13] spi: dw: Fix driving MOSI low while recieving

Sean Anderson
The resting state of MOSI is high when nothing is driving it. If we drive
it low while recieving, it looks like we are transmitting 0x00 instead of
transmitting nothing. This can confuse slaves (like SD cards) which allow
new commands to be sent over MOSI while they are returning data over MISO.
The return of MOSI from 0 to 1 at the end of recieving a byte can look like
a start bit and a transmission bit to an SD card. This will cause the card
to become out-of-sync with the SPI device, as it thinks the device has
already started transmitting two bytes of a new command. The mmc-spi driver
will not detect the R1 response from the SD card, since it is sent too
early, and offset by two bits. This patch fixes transfer errors when using
SD cards with dw spi.

Signed-off-by: Sean Anderson <[hidden email]>
---

Changes in v4:
- New

 drivers/spi/designware_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 2559aac2e9..74372171aa 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -322,7 +322,7 @@ static inline u32 rx_max(struct dw_spi_priv *priv)
 static void dw_writer(struct dw_spi_priv *priv)
 {
  u32 max = tx_max(priv);
- u16 txw = 0;
+ u16 txw = 0xFFFF;
 
  while (max--) {
  /* Set the tx word if the transfer's original "tx" is not null */
--
2.28.0

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[PATCH v4 02/13] spi: dw: Convert calls to debug to dev_*

Sean Anderson
In reply to this post by Sean Anderson
This allows different log levels to be enabled or disabled depending on the
desired level of verbosity. In particular, it allows for general debug
information to be printed while excluding more verbose logging which may
interfere with timing.

Signed-off-by: Sean Anderson <[hidden email]>
---

Changes in v4:
- Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
  short succession.
- Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
  name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
  way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
  reduce the amount of instructions in those loops, even with logging enabled.

Changes in v3:
- Lower the log level of some messages
- Prefix user-facing logs with SPI@<address>
- Reword error messages as "message (error %d)"

Changes in v2:
- New

 drivers/spi/designware_spi.c | 38 ++++++++++++++++++------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 74372171aa..b23655d4d9 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -9,6 +9,7 @@
  * Copyright (c) 2009, Intel Corporation.
  */
 
+#define LOG_CATEGORY UCLASS_SPI
 #include <common.h>
 #include <log.h>
 #include <asm-generic/gpio.h>
@@ -139,7 +140,7 @@ static int request_gpio_cs(struct udevice *bus)
  return 0;
 
  if (ret < 0) {
- printf("Error: %d: Can't get %s gpio!\n", ret, bus->name);
+ dev_err(bus, "Couldn't request gpio! (error %d)\n", ret);
  return ret;
  }
 
@@ -148,7 +149,7 @@ static int request_gpio_cs(struct udevice *bus)
       GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  }
 
- debug("%s: used external gpio for CS management\n", __func__);
+ dev_dbg(bus, "Using external gpio for CS management\n");
 #endif
  return 0;
 }
@@ -162,8 +163,7 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
  /* Use 500KHz as a suitable default */
  plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
        500000);
- debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
-      plat->frequency);
+ dev_info(bus, "max-frequency=%d\n", plat->frequency);
 
  return request_gpio_cs(bus);
 }
@@ -174,7 +174,7 @@ static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
 }
 
 /* Restart the controller, disable all interrupts, clean rx fifo */
-static void spi_hw_init(struct dw_spi_priv *priv)
+static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
 {
  spi_enable_chip(priv, 0);
  dw_write(priv, DW_SPI_IMR, 0xff);
@@ -196,7 +196,7 @@ static void spi_hw_init(struct dw_spi_priv *priv)
  priv->fifo_len = (fifo == 1) ? 0 : fifo;
  dw_write(priv, DW_SPI_TXFLTR, 0);
  }
- debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
+ dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
 }
 
 /*
@@ -221,8 +221,7 @@ __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
  if (!*rate)
  goto err_rate;
 
- debug("%s: get spi controller clk via device tree: %lu Hz\n",
-      __func__, *rate);
+ dev_dbg(bus, "Got clock via device tree: %lu Hz\n", *rate);
 
  return 0;
 
@@ -247,14 +246,16 @@ static int dw_spi_reset(struct udevice *bus)
  if (ret == -ENOENT || ret == -ENOTSUPP)
  return 0;
 
- dev_warn(bus, "Can't get reset: %d\n", ret);
+ dev_warn(bus, "Couldn't find/assert reset device (error %d)\n",
+ ret);
  return ret;
  }
 
  ret = reset_deassert_bulk(&priv->resets);
  if (ret) {
  reset_release_bulk(&priv->resets);
- dev_err(bus, "Failed to reset: %d\n", ret);
+ dev_err(bus, "Failed to de-assert reset for SPI (error %d)\n",
+ ret);
  return ret;
  }
 
@@ -284,7 +285,7 @@ static int dw_spi_probe(struct udevice *bus)
  priv->tmode = 0; /* Tx & Rx */
 
  /* Basic HW init */
- spi_hw_init(priv);
+ spi_hw_init(bus, priv);
 
  return 0;
 }
@@ -333,7 +334,7 @@ static void dw_writer(struct dw_spi_priv *priv)
  txw = *(u16 *)(priv->tx);
  }
  dw_write(priv, DW_SPI_DR, txw);
- debug("%s: tx=0x%02x\n", __func__, txw);
+ log_content("tx=0x%02x\n", txw);
  priv->tx += priv->bits_per_word >> 3;
  }
 }
@@ -345,7 +346,7 @@ static void dw_reader(struct dw_spi_priv *priv)
 
  while (max--) {
  rxw = dw_read(priv, DW_SPI_DR);
- debug("%s: rx=0x%02x\n", __func__, rxw);
+ log_content("rx=0x%02x\n", rxw);
 
  /* Care about rx if the transfer's original "rx" is not null */
  if (priv->rx_end - priv->len) {
@@ -400,7 +401,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
  /* spi core configured to do 8 bit transfers */
  if (bitlen % 8) {
- debug("Non byte aligned SPI transfer.\n");
+ dev_err(dev, "Non byte aligned SPI transfer.\n");
  return -1;
  }
 
@@ -427,7 +428,6 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
 
  priv->len = bitlen >> 3;
- debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
 
  priv->tx = (void *)tx;
  priv->tx_end = priv->tx + priv->len;
@@ -437,7 +437,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  /* Disable controller before writing control registers */
  spi_enable_chip(priv, 0);
 
- debug("%s: cr0=%08x\n", __func__, cr0);
+ dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
+ priv->len);
  /* Reprogram cr0 only if changed */
  if (dw_read(priv, DW_SPI_CTRL0) != cr0)
  dw_write(priv, DW_SPI_CTRL0, cr0);
@@ -497,8 +498,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
  spi_enable_chip(priv, 1);
 
  priv->freq = speed;
- debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
-      priv->freq, clk_div);
+ dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div);
 
  return 0;
 }
@@ -513,7 +513,7 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode)
  * real transfer function.
  */
  priv->mode = mode;
- debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
+ dev_dbg(bus, "mode=%d\n", priv->mode);
 
  return 0;
 }
--
2.28.0

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[PATCH v4 03/13] spi: dw: Rename "cs-gpio" to "cs-gpios"

Sean Anderson
In reply to this post by Sean Anderson
This property is named differently than other SPI drivers with the same
property, as well as the property as used in Linux.

Signed-off-by: Sean Anderson <[hidden email]>
Tested-by Eugeniy Paltsev <[hidden email]>
---
AFAIK these device trees are not synced with Linux. However, if they are,
they have not been synced since this property was renamed in Linux.

This patch was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576

(no changes since v1)

 arch/arc/dts/axs10x_mb.dtsi   | 3 ++-
 arch/arc/dts/hsdk-common.dtsi | 3 ++-
 drivers/spi/designware_spi.c  | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 33b0593438..daf7ca68fb 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -97,7 +97,8 @@
  spi-max-frequency = <4000000>;
  clocks = <&apbclk>;
  clock-names = "spi_clk";
- cs-gpio = <&cs_gpio 0>;
+ num-cs = <1>;
+ cs-gpios = <&cs_gpio 0>;
  spi_flash@0 {
  compatible = "jedec,spi-nor";
  reg = <0>;
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index 9aa10e4b25..a4b348b948 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -135,7 +135,8 @@
  spi-max-frequency = <4000000>;
  clocks = <&cgu_clk CLK_SYS_SPI_REF>;
  clock-names = "spi_clk";
- cs-gpio = <&cs_gpio 0>;
+ num-cs = <1>;
+ cs-gpios = <&cs_gpio 0>;
  spi_flash@0 {
  compatible = "jedec,spi-nor";
  reg = <0>;
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index b23655d4d9..32de33f695 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -135,7 +135,8 @@ static int request_gpio_cs(struct udevice *bus)
  int ret;
 
  /* External chip select gpio line is optional */
- ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0);
+ ret = gpio_request_by_name(bus, "cs-gpios", 0, &priv->cs_gpio,
+   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  if (ret == -ENOENT)
  return 0;
 
--
2.28.0

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[PATCH v4 04/13] spi: dw: Use generic function to read reg address

Sean Anderson
In reply to this post by Sean Anderson
Using an fdt-specific function causes problems when compiled with a live
tree.

Signed-off-by: Sean Anderson <[hidden email]>
Tested-by Eugeniy Paltsev <[hidden email]>
---
This patch was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576

(no changes since v1)

 drivers/spi/designware_spi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 32de33f695..e8ba80ef41 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -160,6 +160,8 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
  struct dw_spi_platdata *plat = bus->platdata;
 
  plat->regs = dev_read_addr_ptr(bus);
+ if (!plat->regs)
+ return -EINVAL;
 
  /* Use 500KHz as a suitable default */
  plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
--
2.28.0

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[PATCH v4 05/13] spi: dw: Rename registers to match datasheet

Sean Anderson
In reply to this post by Sean Anderson
A few registers had slightly different names from what is in the datasheet.

Signed-off-by: Sean Anderson <[hidden email]>
---

(no changes since v1)

 drivers/spi/designware_spi.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index e8ba80ef41..8abcdde8a3 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -27,14 +27,14 @@
 #include <asm/io.h>
 
 /* Register offsets */
-#define DW_SPI_CTRL0 0x00
-#define DW_SPI_CTRL1 0x04
+#define DW_SPI_CTRLR0 0x00
+#define DW_SPI_CTRLR1 0x04
 #define DW_SPI_SSIENR 0x08
 #define DW_SPI_MWCR 0x0c
 #define DW_SPI_SER 0x10
 #define DW_SPI_BAUDR 0x14
-#define DW_SPI_TXFLTR 0x18
-#define DW_SPI_RXFLTR 0x1c
+#define DW_SPI_TXFTLR 0x18
+#define DW_SPI_RXFTLR 0x1c
 #define DW_SPI_TXFLR 0x20
 #define DW_SPI_RXFLR 0x24
 #define DW_SPI_SR 0x28
@@ -191,13 +191,13 @@ static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
  u32 fifo;
 
  for (fifo = 1; fifo < 256; fifo++) {
- dw_write(priv, DW_SPI_TXFLTR, fifo);
- if (fifo != dw_read(priv, DW_SPI_TXFLTR))
+ dw_write(priv, DW_SPI_TXFTLR, fifo);
+ if (fifo != dw_read(priv, DW_SPI_TXFTLR))
  break;
  }
 
  priv->fifo_len = (fifo == 1) ? 0 : fifo;
- dw_write(priv, DW_SPI_TXFLTR, 0);
+ dw_write(priv, DW_SPI_TXFTLR, 0);
  }
  dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
 }
@@ -443,8 +443,8 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
  priv->len);
  /* Reprogram cr0 only if changed */
- if (dw_read(priv, DW_SPI_CTRL0) != cr0)
- dw_write(priv, DW_SPI_CTRL0, cr0);
+ if (dw_read(priv, DW_SPI_CTRLR0) != cr0)
+ dw_write(priv, DW_SPI_CTRLR0, cr0);
 
  /*
  * Configure the desired SS (slave select 0...3) in the controller
--
2.28.0

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[PATCH v4 06/13] spi: dw: Remove spi_enable_chip

Sean Anderson
In reply to this post by Sean Anderson
This function does nothing but wrap dw_write.

Signed-off-by: Sean Anderson <[hidden email]>
---

Changes in v4:
- New

 drivers/spi/designware_spi.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 8abcdde8a3..89a8266052 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -171,17 +171,12 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
  return request_gpio_cs(bus);
 }
 
-static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
-{
- dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
-}
-
 /* Restart the controller, disable all interrupts, clean rx fifo */
 static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
 {
- spi_enable_chip(priv, 0);
+ dw_write(priv, DW_SPI_SSIENR, 0);
  dw_write(priv, DW_SPI_IMR, 0xff);
- spi_enable_chip(priv, 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
 
  /*
  * Try to detect the FIFO depth if not set by interface driver,
@@ -438,7 +433,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  priv->rx_end = priv->rx + priv->len;
 
  /* Disable controller before writing control registers */
- spi_enable_chip(priv, 0);
+ dw_write(priv, DW_SPI_SSIENR, 0);
 
  dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
  priv->len);
@@ -455,7 +450,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  dw_write(priv, DW_SPI_SER, 1 << cs);
 
  /* Enable controller after writing control registers */
- spi_enable_chip(priv, 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
 
  /* Start transfer in a polling loop */
  ret = poll_transfer(priv);
@@ -490,7 +485,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
  speed = plat->frequency;
 
  /* Disable controller before writing control registers */
- spi_enable_chip(priv, 0);
+ dw_write(priv, DW_SPI_SSIENR, 0);
 
  /* clk_div doesn't support odd number */
  clk_div = priv->bus_clk_rate / speed;
@@ -498,7 +493,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
  dw_write(priv, DW_SPI_BAUDR, clk_div);
 
  /* Enable controller after writing control registers */
- spi_enable_chip(priv, 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
 
  priv->freq = speed;
  dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div);
--
2.28.0

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[PATCH v4 07/13] spi: dw: Rearrange struct dw_spi_priv

Sean Anderson
In reply to this post by Sean Anderson
This should reduce the size of the struct, and also groups more similar
fields together.

Signed-off-by: Sean Anderson <[hidden email]>
Tested-by Eugeniy Paltsev <[hidden email]>
---

(no changes since v2)

Changes in v2:
-New

 drivers/spi/designware_spi.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 89a8266052..0ebd2cf3cb 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -95,27 +95,26 @@ struct dw_spi_platdata {
 };
 
 struct dw_spi_priv {
- void __iomem *regs;
- unsigned int freq; /* Default frequency */
- unsigned int mode;
  struct clk clk;
- unsigned long bus_clk_rate;
-
+ struct reset_ctl_bulk resets;
  struct gpio_desc cs_gpio; /* External chip-select gpio */
 
- int bits_per_word;
- u8 cs; /* chip select pin */
- u8 tmode; /* TR/TO/RO/EEPROM */
- u8 type; /* SPI/SSP/MicroWire */
- int len;
+ void __iomem *regs;
+ unsigned long bus_clk_rate;
+ unsigned int freq; /* Default frequency */
+ unsigned int mode;
 
- u32 fifo_len; /* depth of the FIFO buffer */
- void *tx;
- void *tx_end;
+ const void *tx;
+ const void *tx_end;
  void *rx;
  void *rx_end;
+ u32 fifo_len; /* depth of the FIFO buffer */
 
- struct reset_ctl_bulk resets;
+ int bits_per_word;
+ int len;
+ u8 cs; /* chip select pin */
+ u8 tmode; /* TR/TO/RO/EEPROM */
+ u8 type; /* SPI/SSP/MicroWire */
 };
 
 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
--
2.28.0

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[PATCH v4 08/13] spi: dw: Add SoC-specific compatible strings

Sean Anderson
In reply to this post by Sean Anderson
This adds SoC-specific compatible strings to all users of the designware
spi device. This will allow for the correct driver to be selected for each
device. Where it is publicly documented, a compatible string for the
specific device version has also been added. Devices without
publicly-documented device versions include MSCC SoCs, and Arc Socs. All
compatible strings except those for SoCFPGAs and some of the versioned
strings have been taken from Linux.

Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly
necessary. However, it is a good cleanup and brings things closer to Linux.

Signed-off-by: Sean Anderson <[hidden email]>
Tested-by Eugeniy Paltsev <[hidden email]>
---

(no changes since v2)

Changes in v2:
- New

 arch/arc/dts/axs10x_mb.dtsi         |  2 +-
 arch/arc/dts/hsdk-common.dtsi       |  2 +-
 arch/arm/dts/socfpga.dtsi           |  6 ++++--
 arch/arm/dts/socfpga_agilex.dtsi    |  6 ++++--
 arch/arm/dts/socfpga_arria10.dtsi   |  6 ++++--
 arch/arm/dts/socfpga_stratix10.dtsi |  6 ++++--
 arch/mips/dts/mscc,jr2.dtsi         |  2 +-
 arch/mips/dts/mscc,ocelot.dtsi      |  2 +-
 arch/riscv/dts/k210.dtsi            | 13 ++++++++-----
 9 files changed, 28 insertions(+), 17 deletions(-)

diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index daf7ca68fb..d4ff4f7039 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -90,7 +90,7 @@
  };
 
  spi0: spi@0 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
  reg = <0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <0>;
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index a4b348b948..3fc82e57d7 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -128,7 +128,7 @@
  };
 
  spi0: spi@f0020000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
  reg = <0xf0020000 0x1000>;
  #address-cells = <1>;
  #size-cells = <0>;
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index eda558f2fe..ff79d335ac 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -804,7 +804,8 @@
  };
 
  spi0: spi@fff00000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
+     "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xfff00000 0x1000>;
@@ -816,7 +817,8 @@
  };
 
  spi1: spi@fff01000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "altr,socfpga-spi", "snps,dw-apb-ssi-3.20",
+     "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xfff01000 0x1000>;
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi
index 179b4d5591..c3ead2d72b 100644
--- a/arch/arm/dts/socfpga_agilex.dtsi
+++ b/arch/arm/dts/socfpga_agilex.dtsi
@@ -366,7 +366,8 @@
  };
 
  spi0: spi@ffda4000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "intel,agilex-spi",
+     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xffda4000 0x1000>;
@@ -379,7 +380,8 @@
  };
 
  spi1: spi@ffda5000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "intel,agilex-spi",
+     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xffda5000 0x1000>;
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index a598c75542..bab34ab56c 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -604,7 +604,8 @@
  };
 
  spi0: spi@ffda4000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "altr,socfpga-arria10-spi",
+     "snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xffda4000 0x100>;
@@ -617,7 +618,8 @@
  };
 
  spi1: spi@ffda5000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "altr,socfpga-arria10-spi",
+     "snps,dw-apb-ssi-3.22a", "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xffda5000 0x100>;
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
index cb799bc551..7a7777202c 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -268,7 +268,8 @@
  };
 
  spi0: spi@ffda4000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "intel,stratix10-spi",
+     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xffda4000 0x1000>;
@@ -281,7 +282,8 @@
  };
 
  spi1: spi@ffda5000 {
- compatible = "snps,dw-apb-ssi";
+ compatible = "intel,stratix10-spi",
+     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0xffda5000 0x1000>;
diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
index 7f5a96fecd..c44e9a2b3a 100644
--- a/arch/mips/dts/mscc,jr2.dtsi
+++ b/arch/mips/dts/mscc,jr2.dtsi
@@ -94,7 +94,7 @@
  spi0: spi-master@101000 {
  #address-cells = <1>;
  #size-cells = <0>;
- compatible = "snps,dw-apb-ssi";
+ compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi";
  reg = <0x101000 0x40>;
  num-chipselect = <4>;
  bus-num = <0>;
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 9a187b6e58..aeb4bf8f4b 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -100,7 +100,7 @@
  spi0: spi-master@101000 {
  #address-cells = <1>;
  #size-cells = <0>;
- compatible = "snps,dw-apb-ssi";
+ compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
  reg = <0x101000 0x40>;
  num-chipselect = <4>;
  bus-num = <0>;
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 7605c01f3c..1ae3bf9bdf 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -284,7 +284,8 @@
  };
 
  spi2: spi@50240000 {
- compatible = "kendryte,k120-spislave",
+ compatible = "canaan,kendryte-k210-spi",
+     "snps,dw-apb-ssi-4.01",
      "snps,dw-apb-ssi";
  spi-slave;
  reg = <0x50240000 0x100>;
@@ -557,7 +558,8 @@
  spi0: spi@52000000 {
  #address-cells = <1>;
  #size-cells = <0>;
- compatible = "kendryte,k210-spi",
+ compatible = "canaan,kendryte-k210-spi",
+     "snps,dw-apb-ssi-4.01",
      "snps,dw-apb-ssi";
  reg = <0x52000000 0x100>;
  interrupts = <1>;
@@ -573,7 +575,8 @@
  spi1: spi@53000000 {
  #address-cells = <1>;
  #size-cells = <0>;
- compatible = "kendryte,k210-spi",
+ compatible = "canaan,kendryte-k210-spi",
+     "snps,dw-apb-ssi-4.01",
      "snps,dw-apb-ssi";
  reg = <0x53000000 0x100>;
  interrupts = <2>;
@@ -589,8 +592,8 @@
  spi3: spi@54000000 {
  #address-cells = <1>;
  #size-cells = <0>;
- compatible = "kendryte,k210-spi",
-     "snps,dw-apb-ssi";
+ compatible = "canaan,kendryte-k210-ssi",
+     "snps,dwc-ssi-1.01a";
  reg = <0x54000000 0x200>;
  interrupts = <4>;
  clocks = <&sysclk K210_CLK_SPI3>;
--
2.28.0

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[PATCH v4 09/13] spi: dw: Add support for multiple CTRLR0 layouts

Sean Anderson
In reply to this post by Sean Anderson
CTRLR0 can have several different layouts depending on the specific device
(dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis.
Update the driver to support three specific configurations: dw-apb-ssi with
SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi.

dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC
SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver
supported before this change. The register layout before version 3.23a is:

|   31 .. 16  |
| other stuff |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 |
| other stuff |  TMOD  |  MODE  |  FRF   |  DFS   |

Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data
frames of 16 bits or less.

In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This
parameter defaults to 16 (resulting in the same layout as prior versions),
but may also be set to 32. To allow setting longer data frame sizes, a new
DFS_32 register was introduced:

|   31 .. 21  | 20 .. 16 |
| other stuff |  DFS_32  |

|   15 .. 10  | 9 .. 8 | 7 .. 6 | 5 .. 4 |  3 .. 0   |
| other stuff |  TMOD  |  MODE  |  FRF   | all zeros |

The old DFS field no longer controls the data frame size. To detect this
layout, we try writing 0xF to DFS. If we read back 0x0, then this device
has SSI_MAX_XFER_SIZE=32.

dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan
Kendryte K210 SoCs. The layout of ctrlr0 is:

|   31 .. 16  |
| other stuff |

|   15 .. 12  | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 |
| other stuff |   TMOD   |  MODE  |  FRF   | DFS_32 |

The semantics of the fields have not changed since the previous version.
However, SSI_MAX_XFER_SIZE is effectively always 32.

To support these different layouts, we model our approach on the one
which the Linux kernel has taken. During probe, the driver calls an init
function stored in driver_data. This init function is responsible for
determining the layout of CTRLR0, and supplying the update_cr0 function.

The style of and information behind this commit is based on the Linux MMIO
driver for these devices. Specific reference was made to the series adding
support for Intel Keem Bay SoCs [1].

[1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@.../

Signed-off-by: Sean Anderson <[hidden email]>
---

Changes in v4:
- Auto-detect SSI_MAX_XFER_SIZE

Changes in v3:
- Prefix log messages with SPI@<address>

Changes in v2:
- Configure ctrlr0 register layout based on compatible string
- Split documentation off into its own patch

 drivers/spi/designware_spi.c | 176 +++++++++++++++++++++++++++++------
 1 file changed, 145 insertions(+), 31 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 0ebd2cf3cb..9e02fce6c6 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -3,6 +3,7 @@
  * Designware master SPI core controller driver
  *
  * Copyright (C) 2014 Stefan Roese <[hidden email]>
+ * Copyright (C) 2020 Sean Anderson <[hidden email]>
  *
  * Very loosely based on the Linux driver:
  * drivers/spi/spi-dw.c, which is:
@@ -22,6 +23,7 @@
 #include <reset.h>
 #include <dm/device_compat.h>
 #include <linux/bitops.h>
+#include <linux/bitfield.h>
 #include <linux/compat.h>
 #include <linux/iopoll.h>
 #include <asm/io.h>
@@ -54,28 +56,48 @@
 #define DW_SPI_DR 0x60
 
 /* Bit fields in CTRLR0 */
-#define SPI_DFS_OFFSET 0
+/*
+ * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only
+ * option before version 3.23a.
+ */
+#define CTRLR0_DFS_MASK GENMASK(3, 0)
 
-#define SPI_FRF_OFFSET 4
-#define SPI_FRF_SPI 0x0
-#define SPI_FRF_SSP 0x1
-#define SPI_FRF_MICROWIRE 0x2
-#define SPI_FRF_RESV 0x3
+#define CTRLR0_FRF_MASK GENMASK(5, 4)
+#define CTRLR0_FRF_SPI 0x0
+#define CTRLR0_FRF_SSP 0x1
+#define CTRLR0_FRF_MICROWIRE 0x2
+#define CTRLR0_FRF_RESV 0x3
 
-#define SPI_MODE_OFFSET 6
-#define SPI_SCPH_OFFSET 6
-#define SPI_SCOL_OFFSET 7
+#define CTRLR0_MODE_MASK GENMASK(7, 6)
+#define CTRLR0_MODE_SCPH 0x1
+#define CTRLR0_MODE_SCPOL 0x2
 
-#define SPI_TMOD_OFFSET 8
-#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
-#define SPI_TMOD_TR 0x0 /* xmit & recv */
-#define SPI_TMOD_TO 0x1 /* xmit only */
-#define SPI_TMOD_RO 0x2 /* recv only */
-#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
+#define CTRLR0_TMOD_MASK GENMASK(9, 8)
+#define CTRLR0_TMOD_TR 0x0 /* xmit & recv */
+#define CTRLR0_TMOD_TO 0x1 /* xmit only */
+#define CTRLR0_TMOD_RO 0x2 /* recv only */
+#define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
 
-#define SPI_SLVOE_OFFSET 10
-#define SPI_SRL_OFFSET 11
-#define SPI_CFS_OFFSET 12
+#define CTRLR0_SLVOE_OFFSET 10
+#define CTRLR0_SRL_OFFSET 11
+#define CTRLR0_CFS_MASK GENMASK(15, 12)
+
+/* Only present when SSI_MAX_XFER_SIZE=32 */
+#define CTRLR0_DFS_32_MASK GENMASK(20, 16)
+
+/* The next field is only present on versions after 4.00a */
+#define CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
+#define CTRLR0_SPI_FRF_BYTE 0x0
+#define CTRLR0_SPI_FRF_DUAL 0x1
+#define CTRLR0_SPI_FRF_QUAD 0x2
+
+/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
+#define DWC_SSI_CTRLR0_DFS_MASK GENMASK(4, 0)
+#define DWC_SSI_CTRLR0_FRF_MASK GENMASK(7, 6)
+#define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8)
+#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
+#define DWC_SSI_CTRLR0_SRL_OFFSET 13
+#define DWC_SSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
 
 /* Bit fields in SR, 7 bits */
 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
@@ -99,6 +121,8 @@ struct dw_spi_priv {
  struct reset_ctl_bulk resets;
  struct gpio_desc cs_gpio; /* External chip-select gpio */
 
+ u32 (*update_cr0)(struct dw_spi_priv *priv);
+
  void __iomem *regs;
  unsigned long bus_clk_rate;
  unsigned int freq; /* Default frequency */
@@ -109,6 +133,7 @@ struct dw_spi_priv {
  void *rx;
  void *rx_end;
  u32 fifo_len; /* depth of the FIFO buffer */
+ u32 max_xfer; /* Maximum transfer size (in bits) */
 
  int bits_per_word;
  int len;
@@ -127,6 +152,53 @@ static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
  __raw_writel(val, priv->regs + offset);
 }
 
+static u32 dw_spi_dw16_update_cr0(struct dw_spi_priv *priv)
+{
+ return FIELD_PREP(CTRLR0_DFS_MASK, priv->bits_per_word - 1)
+     | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
+     | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
+     | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
+}
+
+static u32 dw_spi_dw32_update_cr0(struct dw_spi_priv *priv)
+{
+ return FIELD_PREP(CTRLR0_DFS_32_MASK, priv->bits_per_word - 1)
+     | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
+     | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
+     | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
+}
+
+static u32 dw_spi_dwc_update_cr0(struct dw_spi_priv *priv)
+{
+ return FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK, priv->bits_per_word - 1)
+     | FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
+     | FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
+     | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
+}
+
+static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv)
+{
+ /* If we read zeros from DFS, then we need to use DFS_32 instead */
+ dw_write(priv, DW_SPI_SSIENR, 0);
+ dw_write(priv, DW_SPI_CTRLR0, 0xffffffff);
+ if (FIELD_GET(CTRLR0_DFS_MASK, dw_read(priv, DW_SPI_CTRLR0))) {
+ priv->max_xfer = 16;
+ priv->update_cr0 = dw_spi_dw16_update_cr0;
+ } else {
+ priv->max_xfer = 32;
+ priv->update_cr0 = dw_spi_dw32_update_cr0;
+ }
+
+ return 0;
+}
+
+static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv)
+{
+ priv->max_xfer = 32;
+ priv->update_cr0 = dw_spi_dwc_update_cr0;
+ return 0;
+}
+
 static int request_gpio_cs(struct udevice *bus)
 {
 #if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
@@ -165,6 +237,10 @@ static int dw_spi_ofdata_to_platdata(struct udevice *bus)
  /* Use 500KHz as a suitable default */
  plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
        500000);
+
+ if (dev_read_bool(bus, "spi-slave"))
+ return -EINVAL;
+
  dev_info(bus, "max-frequency=%d\n", plat->frequency);
 
  return request_gpio_cs(bus);
@@ -259,11 +335,15 @@ static int dw_spi_reset(struct udevice *bus)
  return 0;
 }
 
+typedef int (*dw_spi_init_t)(struct udevice *bus, struct dw_spi_priv *priv);
+
 static int dw_spi_probe(struct udevice *bus)
 {
+ dw_spi_init_t init = (dw_spi_init_t)dev_get_driver_data(bus);
  struct dw_spi_platdata *plat = dev_get_platdata(bus);
  struct dw_spi_priv *priv = dev_get_priv(bus);
  int ret;
+ u32 version;
 
  priv->regs = plat->regs;
  priv->freq = plat->frequency;
@@ -276,6 +356,17 @@ static int dw_spi_probe(struct udevice *bus)
  if (ret)
  return ret;
 
+ if (!init)
+ return -EINVAL;
+ ret = init(bus, priv);
+ if (ret)
+ return ret;
+
+ version = dw_read(priv, DW_SPI_VERSION);
+ dev_dbg(bus, "ssi_version_id=%c.%c%c%c ssi_max_xfer_size=%u\n",
+ version >> 24, version >> 16, version >> 8, version,
+ priv->max_xfer);
+
  /* Currently only bits_per_word == 8 supported */
  priv->bits_per_word = 8;
 
@@ -320,7 +411,7 @@ static inline u32 rx_max(struct dw_spi_priv *priv)
 static void dw_writer(struct dw_spi_priv *priv)
 {
  u32 max = tx_max(priv);
- u16 txw = 0xFFFF;
+ u32 txw = 0xFFFFFFFF;
 
  while (max--) {
  /* Set the tx word if the transfer's original "tx" is not null */
@@ -406,23 +497,18 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  if (flags & SPI_XFER_BEGIN)
  external_cs_manage(dev, false);
 
- cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
- (priv->mode << SPI_MODE_OFFSET) |
- (priv->tmode << SPI_TMOD_OFFSET);
-
  if (rx && tx)
- priv->tmode = SPI_TMOD_TR;
+ priv->tmode = CTRLR0_TMOD_TR;
  else if (rx)
- priv->tmode = SPI_TMOD_RO;
+ priv->tmode = CTRLR0_TMOD_RO;
  else
  /*
- * In transmit only mode (SPI_TMOD_TO) input FIFO never gets
+ * In transmit only mode (CTRL0_TMOD_TO) input FIFO never gets
  * any data which breaks our logic in poll_transfer() above.
  */
- priv->tmode = SPI_TMOD_TR;
+ priv->tmode = CTRLR0_TMOD_TR;
 
- cr0 &= ~SPI_TMOD_MASK;
- cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
+ cr0 = priv->update_cr0(priv);
 
  priv->len = bitlen >> 3;
 
@@ -476,7 +562,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
 
 static int dw_spi_set_speed(struct udevice *bus, uint speed)
 {
- struct dw_spi_platdata *plat = bus->platdata;
+ struct dw_spi_platdata *plat = dev_get_platdata(bus);
  struct dw_spi_priv *priv = dev_get_priv(bus);
  u16 clk_div;
 
@@ -547,7 +633,35 @@ static const struct dm_spi_ops dw_spi_ops = {
 };
 
 static const struct udevice_id dw_spi_ids[] = {
- { .compatible = "snps,dw-apb-ssi" },
+ /* Generic compatible strings */
+
+ { .compatible = "snps,dw-apb-ssi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "snps,dw-apb-ssi-3.20a", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "snps,dw-apb-ssi-3.22a", .data = (ulong)dw_spi_apb_init },
+ /* First version with SSI_MAX_XFER_SIZE */
+ { .compatible = "snps,dw-apb-ssi-3.23a", .data = (ulong)dw_spi_apb_init },
+ /* First version with Dual/Quad SPI; unused by this driver */
+ { .compatible = "snps,dw-apb-ssi-4.00a", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "snps,dw-apb-ssi-4.01", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "snps,dwc-ssi-1.01a", .data = (ulong)dw_spi_dwc_init },
+
+ /* Compatible strings for specific SoCs */
+
+ /*
+ * Both the Cyclone V and Arria V share a device tree and have the same
+ * version of this device. This compatible string is used for those
+ * devices, and is not used for sofpgas in general.
+ */
+ { .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "canaan,kendryte-k210-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "canaan,kendryte-k210-ssi", .data = (ulong)dw_spi_dwc_init },
+ { .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "mscc,ocelot-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "mscc,jaguar2-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "snps,axs10x-spi", .data = (ulong)dw_spi_apb_init },
+ { .compatible = "snps,hsdk-spi", .data = (ulong)dw_spi_apb_init },
  { }
 };
 
--
2.28.0

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[PATCH v4 10/13] spi: dw: Document devicetree binding

Sean Anderson
In reply to this post by Sean Anderson
This documentation has been taken from Linux commit 3d7db0f11c7a ("spi: dw:
Refactor mid_spi_dma_setup() to separate DMA and IRQ config"), immediately
before the file was deleted and replaced with a yaml version. Additional
compatible strings from newer versions have been added, as well as a few
U-Boot-specific ones.

Signed-off-by: Sean Anderson <[hidden email]>
---

(no changes since v3)

Changes in v3:
- Synchronize compatible strings between docs and driver

Changes in v2:
- Document new compatible strings
- Split off from ctrlr0 commit

 .../spi/snps,dw-apb-ssi.txt                   | 56 +++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt

diff --git a/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
new file mode 100644
index 0000000000..8d2888fbe3
--- /dev/null
+++ b/doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt
@@ -0,0 +1,56 @@
+Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
+and Synopsys DesignWare High Performance Synchronous Serial Interface
+
+Required properties:
+- compatible : One of
+  "altr,socfpga-spi",
+  "altr,socfpga-arria10-spi",
+  "canaan,kendryte-k210-spi",
+  "canaan,kendryte-k210-ssi",
+  "intel,stratix10-spi",
+  "intel,agilex-spi",
+  "mscc,ocelot-spi",
+  or "mscc,jaguar2-spi";
+  and one of
+  "snps,dw-apb-ssi-3.20a",
+  "snps,dw-apb-ssi-3.22a",
+  "snps,dw-apb-ssi-3.23",
+  "snps,dw-apb-ssi-4.00a",
+  "snps,dw-apb-ssi-4.01",
+  or "snps,dwc-ssi-1.01a".
+  "snps,dw-apb-ssi" may also be used, but is deprecated in favor of specific
+  version strings.
+- reg : The register base for the controller. For "mscc,<soc>-spi", a second
+  register set is required (named ICPU_CFG:SPI_MST)
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+- clocks : phandles for the clocks, see the description of clock-names below.
+   The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
+   is optional. If a single clock is specified but no clock-name, it is the
+   "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
+
+Optional properties:
+- clock-names : Contains the names of the clocks:
+    "ssi_clk", for the core clock used to generate the external SPI clock.
+    "pclk", the interface clock, required for register access.
+- cs-gpios : Specifies the gpio pins to be used for chipselects.
+- num-cs : The number of chipselects. If omitted, this will default to 4.
+- reg-io-width : The I/O register width (in bytes) implemented by this
+  device.  Supported values are 2 or 4 (the default).
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi@fff00000 {
+ compatible = "altr,socfpga-arria10-spi",
+     "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 154 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&spi_m_clk>;
+ num-cs = <2>;
+ cs-gpios = <&gpio0 13 0>,
+   <&gpio0 14 0>;
+ };
--
2.28.0

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[PATCH v4 11/13] spi: dw: Add mem_ops

Sean Anderson
In reply to this post by Sean Anderson
The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls.  This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.

This patch also rearranges the headers to conform to U-Boot style.

[1] https://lkml.org/lkml/2015/12/23/132

Signed-off-by: Sean Anderson <[hidden email]>
Tested-by Eugeniy Paltsev <[hidden email]>
---
This patch was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576

Changes in v4:
- Overcome my sloth
- Rearrange headers in designware_spi.c

Changes in v3:
- Use constant 0x10000 instead of SZ_64K. The latter is not included on
  some platforms and I'm too lazy to figure out what the correct header is.

Changes in v2:
- Add external gpio cs support
- Clean up exec_op
- Convert debug to log_*
- Limit data transfers to 64k

 drivers/spi/designware_spi.c | 122 ++++++++++++++++++++++++++++++++---
 1 file changed, 113 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 9e02fce6c6..ce74ac0abc 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -12,21 +12,23 @@
 
 #define LOG_CATEGORY UCLASS_SPI
 #include <common.h>
-#include <log.h>
-#include <asm-generic/gpio.h>
 #include <clk.h>
 #include <dm.h>
-#include <errno.h>
-#include <malloc.h>
-#include <spi.h>
-#include <fdtdec.h>
-#include <reset.h>
 #include <dm/device_compat.h>
-#include <linux/bitops.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
+#include <reset.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
 #include <linux/bitfield.h>
+#include <linux/bitops.h>
 #include <linux/compat.h>
 #include <linux/iopoll.h>
-#include <asm/io.h>
+#include <linux/sizes.h>
 
 /* Register offsets */
 #define DW_SPI_CTRLR0 0x00
@@ -560,6 +562,107 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
  return ret;
 }
 
+/*
+ * This function is necessary for reading SPI flash with the native CS
+ * c.f. https://lkml.org/lkml/2015/12/23/132
+ */
+static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+ bool read = op->data.dir == SPI_MEM_DATA_IN;
+ int pos, i, ret = 0;
+ struct udevice *bus = slave->dev->parent;
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ u8 op_buf[op_len];
+ u32 cr0;
+
+ if (read)
+ priv->tmode = CTRLR0_TMOD_EPROMREAD;
+ else
+ priv->tmode = CTRLR0_TMOD_TO;
+
+ cr0 = priv->update_cr0(priv);
+ dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in,
+ op->data.nbytes);
+
+ dw_write(priv, DW_SPI_SSIENR, 0);
+ dw_write(priv, DW_SPI_CTRLR0, cr0);
+ if (read)
+ dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1);
+ dw_write(priv, DW_SPI_SSIENR, 1);
+
+ /* From spi_mem_exec_op */
+ pos = 0;
+ op_buf[pos++] = op->cmd.opcode;
+ if (op->addr.nbytes) {
+ for (i = 0; i < op->addr.nbytes; i++)
+ op_buf[pos + i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ pos += op->addr.nbytes;
+ }
+ if (op->dummy.nbytes)
+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+ external_cs_manage(slave->dev, false);
+
+ priv->tx = &op_buf;
+ priv->tx_end = priv->tx + op_len;
+ priv->rx = NULL;
+ priv->rx_end = NULL;
+ while (priv->tx != priv->tx_end)
+ dw_writer(priv);
+
+ /*
+ * XXX: The following are tight loops! Enabling debug messages may cause
+ * them to fail because we are not reading/writing the fifo fast enough.
+ */
+ if (read) {
+ priv->rx = op->data.buf.in;
+ priv->rx_end = priv->rx + op->data.nbytes;
+
+ dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
+ while (priv->rx != priv->rx_end)
+ dw_reader(priv);
+ } else {
+ u32 val;
+
+ priv->tx = op->data.buf.out;
+ priv->tx_end = priv->tx + op->data.nbytes;
+
+ /* Fill up the write fifo before starting the transfer */
+ dw_writer(priv);
+ dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
+ while (priv->tx != priv->tx_end)
+ dw_writer(priv);
+
+ if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
+       (val & SR_TF_EMPT) && !(val & SR_BUSY),
+       RX_TIMEOUT * 1000)) {
+ ret = -ETIMEDOUT;
+ }
+ }
+
+ dw_write(priv, DW_SPI_SER, 0);
+ external_cs_manage(slave->dev, true);
+
+ dev_dbg(bus, "%u bytes xfered\n", op->data.nbytes);
+ return ret;
+}
+
+/* The size of ctrl1 limits data transfers to 64K */
+static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
+{
+ op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops dw_spi_mem_ops = {
+ .exec_op = dw_spi_exec_op,
+ .adjust_op_size = dw_spi_adjust_op_size,
+};
+
 static int dw_spi_set_speed(struct udevice *bus, uint speed)
 {
  struct dw_spi_platdata *plat = dev_get_platdata(bus);
@@ -624,6 +727,7 @@ static int dw_spi_remove(struct udevice *bus)
 
 static const struct dm_spi_ops dw_spi_ops = {
  .xfer = dw_spi_xfer,
+ .mem_ops = &dw_spi_mem_ops,
  .set_speed = dw_spi_set_speed,
  .set_mode = dw_spi_set_mode,
  /*
--
2.28.0

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[PATCH v4 12/13] riscv: Add device tree bindings for SPI

Sean Anderson
In reply to this post by Sean Anderson
This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix
Bit.

Signed-off-by: Sean Anderson <[hidden email]>
Acked-by: Rick Chen <[hidden email]>
---
This patch was previously part of
https://patchwork.ozlabs.org/project/uboot/list/?series=161576

(no changes since v2)

Changes in v2:
- Remove broken-wp property (implicit due to no wp gpio)
- Remove ctrl0 field offsets from device tree
- Switch to new compatible strings
- Switch to new pinmux binding style

 arch/riscv/dts/k210-maix-bit.dts | 46 +++++++++++++++++++++++++++++++-
 arch/riscv/dts/k210.dtsi         |  2 ++
 2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
index c2beec602c..e4dea205b2 100644
--- a/arch/riscv/dts/k210-maix-bit.dts
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -152,7 +152,7 @@
  pinmux = <K210_FPIOA(26, K210_PCF_SPI1_D1)>,
  <K210_FPIOA(27, K210_PCF_SPI1_SCLK)>,
  <K210_FPIOA(28, K210_PCF_SPI1_D0)>,
- <K210_FPIOA(29, K210_PCF_GPIOHS13)>;
+ <K210_FPIOA(29, K210_PCF_GPIOHS13)>; /* cs */
  };
 };
 
@@ -160,3 +160,47 @@
  pinctrl-0 = <&fpioa_dvp>;
  pinctrl-names = "default";
 };
+
+&spi0 {
+ pinctrl-0 = <&fpioa_spi0>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ cs-gpios = <&gpio0 20 0>;
+
+ panel@0 {
+ compatible = "sitronix,st7789v";
+ reg = <0>;
+ reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ dc-gpios = <&gpio0 22 0>;
+ spi-max-frequency = <15000000>;
+ status = "disabled";
+ };
+};
+
+&spi1 {
+ pinctrl-0 = <&fpioa_spi1>;
+ pinctrl-names = "default";
+ num-cs = <1>;
+ cs-gpios = <&gpio0 13 0>;
+ status = "okay";
+
+ slot@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ voltage-ranges = <3300 3300>;
+ broken-cd;
+ };
+};
+
+&spi3 {
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ broken-flash-reset;
+ };
+};
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 1ae3bf9bdf..98411e63a4 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -496,6 +496,8 @@
  interrupts = <24>;
  clocks = <&sysclk K210_CLK_DVP>;
  resets = <&sysrst K210_RST_DVP>;
+ kendryte,sysctl = <&sysctl>;
+ kendryte,misc-offset = <K210_SYSCTL_MISC>;
  status = "disabled";
  };
 
--
2.28.0

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[PATCH v4 13/13] riscv: Add support for SPI on Kendryte K210

Sean Anderson
In reply to this post by Sean Anderson
This enables configs necessary for using SPI. The environment is saved to
the very end of SPI flash. This is unlikely to be overwritten unless the
entire flash is reprogrammed.

This also supplies a default bootcommand. It loads an image and device tree
from the first partition of the MMC. This is a minimal/least effort
bootcmd, so suggestions (especially in the form of patches) are welcome. I
didn't set up distro boot because I think it is unlikely that any
general-purpose linux distros will ever be ported to this board.

Signed-off-by: Sean Anderson <[hidden email]>
---

Changes in v4:
- Enable booting from MMC
- Place env in spi flash
- Update documentation

Changes in v3:
- Rebase onto U-Boot master
- Remove env and bootcmd configuration. I'm going to punt on those for now,
  since I haven't worked out the best way to boot with SPI yet. Those
  settings may be added back in a follow-up patch.

Changes in v2:
- Add Gigadevice SPI chips to dependencies

 board/sipeed/maix/Kconfig          |  16 ++
 configs/sipeed_maix_bitm_defconfig |  10 +
 doc/board/sipeed/maix.rst          | 319 ++++++++++++++++++++++++-----
 include/configs/sipeed-maix.h      |   7 +-
 4 files changed, 300 insertions(+), 52 deletions(-)

diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
index 4c42dd2087..2cdea8ea81 100644
--- a/board/sipeed/maix/Kconfig
+++ b/board/sipeed/maix/Kconfig
@@ -53,4 +53,20 @@ config BOARD_SPECIFIC_OPTIONS
  imply CMD_GPIO
  imply LED
  imply LED_GPIO
+ imply SPI
+ imply DESIGNWARE_SPI
+ imply SPI_FLASH_GIGADEVICE
+ imply SPI_FLASH_WINBOND
+ imply DM_MTD
+ imply SPI_FLASH_MTD
+ imply CMD_MTD
+ imply ENV_IS_IN_SPI_FLASH
+ imply MMC
+ imply MMC_BROKEN_CD
+ imply MMC_SPI
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply CMD_PART
+ imply CMD_FS_GENERIC
 endif
diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
index 459bf0d530..cb9824e84e 100644
--- a/configs/sipeed_maix_bitm_defconfig
+++ b/configs/sipeed_maix_bitm_defconfig
@@ -1,8 +1,18 @@
 CONFIG_RISCV=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0xfff000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_TARGET_SIPEED_MAIX=y
 CONFIG_ARCH_RV64I=y
 CONFIG_STACK_SIZE=0x100000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run k210_bootcmd"
+CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
+CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
 # CONFIG_NET is not set
 # CONFIG_INPUT is not set
+CONFIG_SF_DEFAULT_BUS=3
 # CONFIG_DM_ETH is not set
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
 # CONFIG_EFI_LOADER is not set
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
index 92f2d112a9..bf945b3458 100644
--- a/doc/board/sipeed/maix.rst
+++ b/doc/board/sipeed/maix.rst
@@ -70,6 +70,7 @@ console shall be opened immediately. Boot output should look like the following:
     U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
 
     DRAM:  8 MiB
+    MMC:   spi@53000000:slot@0: 0
     In:    serial@38000000
     Out:   serial@38000000
     Err:   serial@38000000
@@ -118,14 +119,115 @@ The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000.
 
 The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin.
 
-Loading Images
-^^^^^^^^^^^^^^
+Booting
+^^^^^^^
 
-To load a kernel, transfer it over serial.
+The default boot process is to load and boot the files ``/uImage`` and
+``/k210.dtb`` off of the first partition of the MMC. For Linux, this will result
+in an output like
 
 .. code-block:: none
 
-    => loady 80000000 1500000
+    U-Boot 2020.10-00691-gd1d651d988-dirty (Oct 16 2020 - 17:05:24 -0400)
+
+    DRAM:  8 MiB
+    MMC:   spi@53000000:slot@0: 0
+    Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    OK
+    In:    serial@38000000
+    Out:   serial@38000000
+    Err:   serial@38000000
+    Hit any key to stop autoboot:  0
+    1827380 bytes read in 1044 ms (1.7 MiB/s)
+    13428 bytes read in 10 ms (1.3 MiB/s)
+    ## Booting kernel from Legacy Image at 80060000 ...
+       Image Name:   linux
+       Image Type:   RISC-V Linux Kernel Image (uncompressed)
+       Data Size:    1827316 Bytes = 1.7 MiB
+       Load Address: 80000000
+       Entry Point:  80000000
+       Verifying Checksum ... OK
+    ## Flattened Device Tree blob at 80400000
+       Booting using the fdt blob at 0x80400000
+       Loading Kernel Image
+       Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
+
+    Starting kernel ...
+
+    [    0.000000] Linux version 5.9.0-00021-g6dcc2f0814c6-dirty (sean@godwin) (riscv64-linux-gnu-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #34 SMP Fri Oct 16 14:40:57 EDT 2020
+    [    0.000000] earlycon: sifive0 at MMIO 0x0000000038000000 (options '115200n8')
+    [    0.000000] printk: bootconsole [sifive0] enabled
+    [    0.000000] Zone ranges:
+    [    0.000000]   DMA32    [mem 0x0000000080000000-0x00000000807fffff]
+    [    0.000000]   Normal   empty
+    [    0.000000] Movable zone start for each node
+    [    0.000000] Early memory node ranges
+    [    0.000000]   node   0: [mem 0x0000000080000000-0x00000000807fffff]
+    [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000807fffff]
+    [    0.000000] riscv: ISA extensions acdfgim
+    [    0.000000] riscv: ELF capabilities acdfim
+    [    0.000000] percpu: max_distance=0x18000 too large for vmalloc space 0x0
+    [    0.000000] percpu: Embedded 12 pages/cpu s18848 r0 d30304 u49152
+    [    0.000000] Built 1 zonelists, mobility grouping off.  Total pages: 2020
+    [    0.000000] Kernel command line: earlycon console=ttySIF0
+    [    0.000000] Dentry cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
+    [    0.000000] Inode-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
+    [    0.000000] Sorting __ex_table...
+    [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+    [    0.000000] Memory: 6004K/8192K available (1139K kernel code, 126K rwdata, 198K rodata, 90K init, 81K bss, 2188K reserved, 0K cma-reserved)
+    [    0.000000] rcu: Hierarchical RCU implementation.
+    [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+    [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
+    [    0.000000] riscv-intc: 64 local interrupts mapped
+    [    0.000000] plic: interrupt-controller@C000000: mapped 65 interrupts with 2 handlers for 2 contexts.
+    [    0.000000] random: get_random_bytes called from 0x00000000800019a8 with crng_init=0
+    [    0.000000] k210-clk: clock-controller
+    [    0.000000] k210-clk: clock-controller: fixed-rate 26 MHz osc base clock
+    [    0.000000] clint: clint@2000000: timer running at 7800000 Hz
+    [    0.000000] clocksource: clint_clocksource: mask: 0xffffffffffffffff max_cycles: 0x3990be68b, max_idle_ns: 881590404272 ns
+    [    0.000014] sched_clock: 64 bits at 7MHz, resolution 128ns, wraps every 4398046511054ns
+    [    0.008450] Console: colour dummy device 80x25
+    [    0.012494] Calibrating delay loop (skipped), value calculated using timer frequency.. 15.60 BogoMIPS (lpj=31200)
+    [    0.022693] pid_max: default: 4096 minimum: 301
+    [    0.027352] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
+    [    0.034428] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
+    [    0.045099] rcu: Hierarchical SRCU implementation.
+    [    0.050048] smp: Bringing up secondary CPUs ...
+    [    0.055417] smp: Brought up 1 node, 2 CPUs
+    [    0.059602] devtmpfs: initialized
+    [    0.082796] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+    [    0.091820] futex hash table entries: 16 (order: -2, 1024 bytes, linear)
+    [    0.098507] pinctrl core: initialized pinctrl subsystem
+    [    0.140938] clocksource: Switched to clocksource clint_clocksource
+    [    0.247216] workingset: timestamp_bits=62 max_order=11 bucket_order=0
+    [    0.277392] k210-fpioa 502b0000.pinmux: K210 FPIOA pin controller
+    [    0.291724] k210-sysctl 50440000.syscon: K210 system controller
+    [    0.305317] k210-rst 50440000.syscon:reset-controller: K210 reset controller
+    [    0.313808] 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0
+    [    0.322712] printk: console [ttySIF0] enabled
+    [    0.322712] printk: console [ttySIF0] enabled
+    [    0.331328] printk: bootconsole [sifive0] disabled
+    [    0.331328] printk: bootconsole [sifive0] disabled
+    [    0.353347] Freeing unused kernel memory: 88K
+    [    0.357004] This architecture does not have kernel memory protection.
+    [    0.363397] Run /init as init process
+
+Loading, Booting, and Storing Images
+------------------------------------
+
+.. _loading:
+
+Loading Images
+^^^^^^^^^^^^^^
+
+Serial
+""""""
+
+Use the ``loady`` command to load images over serial.
+
+.. code-block:: none
+
+    => loady $loadaddr 1500000
     ## Switch baudrate to 1500000 bps and press ENTER ...
 
     *** baud: 1500000
@@ -150,6 +252,61 @@ To load a kernel, transfer it over serial.
     *** baud: 115200 ***
     =>
 
+This command does not set ``$filesize``, so it may need to be set manually.
+
+SPI Flash
+"""""""""
+
+To load an image off of SPI flash, first set up a partition as described in
+:ref:`partitions`. Then, use ``mtd`` to load that partition
+
+.. code-block:: none
+
+    => sf probe
+    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    => mtd read linux $loadaddr
+    Reading 2097152 byte(s) at offset 0x00000000
+
+This command does not set ``$filesize``, so it may need to be set manually.
+
+MMC
+"""
+
+The MMC device number is 0. To list partitions on the device, use ``part``:
+
+.. code-block:: none
+
+    => part list mmc 0
+
+    Partition Map for MMC device 0  --   Partition Type: EFI
+
+    Part    Start LBA       End LBA          Name
+            Attributes
+            Type GUID
+            Partition GUID
+      1     0x00000800      0x039effde      "boot"
+            attrs:  0x0000000000000000
+            type:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
+            guid:   96161f7d-7113-4cc7-9a24-08ab7fc5cb72
+
+To list files, use ``ls``:
+
+.. code-block:: none
+
+    => ls mmc 0:1
+    <DIR>       4096 .
+    <DIR>       4096 ..
+    <DIR>      16384 lost+found
+               13428 k210.dtb
+             1827380 uImage
+
+To load a file, use ``load``:
+
+.. code-block:: none
+
+    => load mmc 0:1 $loadaddr uImage
+    1827380 bytes read in 1049 ms (1.7 MiB/s)
+
 Running Programs
 ^^^^^^^^^^^^^^^^
 
@@ -160,20 +317,6 @@ To run a bare binary, use the ``go`` command:
 
 .. code-block:: none
 
-    => loady
-    ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
-    C
-    *** file: ./examples/standalone/hello_world.bin
-    $ sz -vv ./examples/standalone/hello_world.bin
-    Sending: hello_world.bin
-    Bytes Sent:   4864   BPS:649
-    Sending:
-    Ymodem sectors/kbytes sent:   0/ 0k
-    Transfer complete
-
-    *** exit status: 0 ***
-    (CAN) packets, 5 retries
-    ## Total Size      = 0x000012f8 = 4856 Bytes
     => go 80000000
     ## Starting application at 0x80000000 ...
     Example expects ABI version 9
@@ -184,51 +327,127 @@ To run a bare binary, use the ``go`` command:
     argv[1] = "<NULL>"
     Hit any key to exit ...
 
+Note that this will only start a program on one hart. As-of this writing it is
+only possible to start a program on multiple harts using the ``bootm`` command.
+
 Legacy Images
 """""""""""""
 
-To run legacy images, use the ``bootm`` command:
+To create a legacy image, use ``tools/mkimage``:
 
 .. code-block:: none
 
-    $ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 80000000 -e 80000000 -d examples/standalone/hello_world.bin hello_world.img
-    Image Name:
-    Created:      Thu Mar  5 12:04:10 2020
-    Image Type:   RISC-V U-Boot Standalone Program (uncompressed)
-    Data Size:    4856 Bytes = 4.74 KiB = 0.00 MiB
+    $ tools/mkimage -A riscv -O linux -T kernel -C none -a 0x80000000 -e 0x80000000 -n linux -d ../linux-git/arch/riscv/boot/Image uImage
+    Image Name:   linux
+    Created:      Fri Oct 16 17:36:32 2020
+    Image Type:   RISC-V Linux Kernel Image (uncompressed)
+    Data Size:    1827316 Bytes = 1784.49 KiB = 1.74 MiB
     Load Address: 80000000
     Entry Point:  80000000
 
-    $ picocom -b 115200 /dev/ttyUSB0
-    => loady
-    ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
-    C
-    *** file: hello_world.img
-    $ sz -vv hello_world.img
-    Sending: hello_world.img
-    Bytes Sent:   4992   BPS:665
-    Sending:
-    Ymodem sectors/kbytes sent:   0/ 0k
-    Transfer complete
+The ``bootm`` command also requires an FDT, even if the image doesn't require
+one. After loading the image to ``$loadaddr`` and the FDT to ``$fdt_addr_r``,
+boot with:
 
-    *** exit status: 0 ***
-    CAN) packets, 3 retries
-    ## Total Size      = 0x00001338 = 4920 Bytes
-    => bootm
-    ## Booting kernel from Legacy Image at 80000000 ...
-       Image Name:
-       Image Type:   RISC-V U-Boot Standalone Program (uncompressed)
-       Data Size:    4856 Bytes = 4.7 KiB
+.. code-block:: none
+
+    => bootm $loadaddr - $fdt_addr_r
+    ## Booting kernel from Legacy Image at 80060000 ...
+       Image Name:   linux
+       Image Type:   RISC-V Linux Kernel Image (uncompressed)
+       Data Size:    1827316 Bytes = 1.7 MiB
        Load Address: 80000000
        Entry Point:  80000000
        Verifying Checksum ... OK
-       Loading Standalone Program
-    Example expects ABI version 9
-    Actual U-Boot ABI version 9
-    Hello World
-    argc = 0
-    argv[0] = "<NULL>"
-    Hit any key to exit ...
+    ## Flattened Device Tree blob at 80400000
+       Booting using the fdt blob at 0x80400000
+       Loading Kernel Image
+       Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
+
+    Starting kernel ...
+
+The FDT is verified after the kernel is relocated, so it must be loaded high
+enough so that it won't be overwritten. The default values for ``$loadaddr``
+and ``$fdt_addr_r`` should provide ample headroom for most use-cases.
+
+Flashing Images
+^^^^^^^^^^^^^^^
+
+SPI Flash
+"""""""""
+
+To flash data to SPI flash, first load it using one of the methods in
+:ref:`loading`. Addiotionally, create some partitions as described in
+:ref:`partitions`. Then use the ``mtd`` command:
+
+.. code-block:: none
+
+    => sf probe
+    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
+    => mtd write linux $loadaddr 0 $filesize
+    Writing 2478162 byte(s) at offset 0x00000000
+
+Note that in order to write a bootable image, a header and tailer must be added.
+
+MMC
+"""
+
+MMC writes are unsupported for now.
+
+SPI Flash
+^^^^^^^^^
+
+Sipeed MAIX boards typically provide around 16 MiB of SPI NOR flash. U-Boot is
+stored in the first 1 MiB or so of this flash. U-Boot's environment is stored at
+the end of flash.
+
+.. _partitions:
+
+Partitions
+""""""""""
+
+There is no set data layout. The default partition layout only allocates
+partitions for U-Boot and its default environment
+
+.. code-block:: none
+
+    => mtd list
+    List of MTD devices:
+    * nor0
+      - type: NOR flash
+      - block size: 0x1000 bytes
+      - min I/O: 0x1 bytes
+      - 0x000000000000-0x000001000000 : "nor0"
+          - 0x000000000000-0x000000100000 : "u-boot"
+          - 0x000000fff000-0x000001000000 : "env"
+
+As an example, to allocate 2MiB for Linux and (almost) 13 MiB for other data,
+set the ``mtdparts`` like:
+
+.. code-block:: none
+
+    => env set mtdparts nor0:1M(u-boot),2M(linux),0xcff000(data),0x1000@0xfff000(env)
+    => mtd list
+    List of MTD devices:
+    * nor0
+      - type: NOR flash
+      - block size: 0x1000 bytes
+      - min I/O: 0x1 bytes
+      - 0x000000000000-0x000001000000 : "nor0"
+          - 0x000000000000-0x000000100000 : "u-boot"
+          - 0x000000100000-0x000000300000 : "linux"
+          - 0x000000300000-0x000000fff000 : "data"
+          - 0x000000fff000-0x000001000000 : "env"
+
+To make these changes permanent, save the environment:
+
+.. code-block:: none
+
+    => env save
+    Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
+    OK
+
+U-Boot will always load the environment from the last 4 KiB of flash.
 
 Pin Assignment
 --------------
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
index 36ff522e4b..08acb25075 100644
--- a/include/configs/sipeed-maix.h
+++ b/include/configs/sipeed-maix.h
@@ -24,10 +24,13 @@
 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS \
  "loadaddr=0x80060000\0" \
- "fdt_addr_r=0x80028000\0" \
+ "fdt_addr_r=0x80400000\0" \
  "scriptaddr=0x80020000\0" \
  "kernel_addr_r=0x80060000\0" \
- "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
+ "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "k210_bootcmd=load mmc 0:1 $loadaddr /uImage && " \
+ "load mmc 0:1 $fdt_addr_r /k210.dtb && " \
+ "bootm $loadaddr - $fdt_addr_r\0"
 #endif
 
 #endif /* CONFIGS_SIPEED_MAIX_H */
--
2.28.0

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Re: [PATCH v4 13/13] riscv: Add support for SPI on Kendryte K210

Sean Anderson
On 10/16/20 6:57 PM, Sean Anderson wrote:

> This enables configs necessary for using SPI. The environment is saved to
> the very end of SPI flash. This is unlikely to be overwritten unless the
> entire flash is reprogrammed.
>
> This also supplies a default bootcommand. It loads an image and device tree
> from the first partition of the MMC. This is a minimal/least effort
> bootcmd, so suggestions (especially in the form of patches) are welcome. I
> didn't set up distro boot because I think it is unlikely that any
> general-purpose linux distros will ever be ported to this board.
>
> Signed-off-by: Sean Anderson <[hidden email]>
> ---
>
> Changes in v4:
> - Enable booting from MMC
> - Place env in spi flash
> - Update documentation
>
> Changes in v3:
> - Rebase onto U-Boot master
> - Remove env and bootcmd configuration. I'm going to punt on those for now,
>   since I haven't worked out the best way to boot with SPI yet. Those
>   settings may be added back in a follow-up patch.
>
> Changes in v2:
> - Add Gigadevice SPI chips to dependencies
>
>  board/sipeed/maix/Kconfig          |  16 ++
>  configs/sipeed_maix_bitm_defconfig |  10 +
>  doc/board/sipeed/maix.rst          | 319 ++++++++++++++++++++++++-----
>  include/configs/sipeed-maix.h      |   7 +-
>  4 files changed, 300 insertions(+), 52 deletions(-)
>
> diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
> index 4c42dd2087..2cdea8ea81 100644
> --- a/board/sipeed/maix/Kconfig
> +++ b/board/sipeed/maix/Kconfig
> @@ -53,4 +53,20 @@ config BOARD_SPECIFIC_OPTIONS
>   imply CMD_GPIO
>   imply LED
>   imply LED_GPIO
> + imply SPI
> + imply DESIGNWARE_SPI
> + imply SPI_FLASH_GIGADEVICE
> + imply SPI_FLASH_WINBOND
> + imply DM_MTD
> + imply SPI_FLASH_MTD
> + imply CMD_MTD
> + imply ENV_IS_IN_SPI_FLASH
> + imply MMC
> + imply MMC_BROKEN_CD
> + imply MMC_SPI
> + imply CMD_MMC
> + imply DOS_PARTITION
> + imply EFI_PARTITION
> + imply CMD_PART
> + imply CMD_FS_GENERIC
>  endif
> diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
> index 459bf0d530..cb9824e84e 100644
> --- a/configs/sipeed_maix_bitm_defconfig
> +++ b/configs/sipeed_maix_bitm_defconfig
> @@ -1,8 +1,18 @@
>  CONFIG_RISCV=y
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_ENV_OFFSET=0xfff000
> +CONFIG_ENV_SECT_SIZE=0x1000
>  CONFIG_TARGET_SIPEED_MAIX=y
>  CONFIG_ARCH_RV64I=y
>  CONFIG_STACK_SIZE=0x100000
> +CONFIG_USE_BOOTCOMMAND=y

This is missing CONFIG_HUSH_PARSER to run the bootcmd.

--Sean

> +CONFIG_BOOTCOMMAND="run k210_bootcmd"
> +CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
> +CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
>  # CONFIG_NET is not set
>  # CONFIG_INPUT is not set
> +CONFIG_SF_DEFAULT_BUS=3
>  # CONFIG_DM_ETH is not set
> +CONFIG_FS_EXT4=y
> +CONFIG_FS_FAT=y
>  # CONFIG_EFI_LOADER is not set
> diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
> index 92f2d112a9..bf945b3458 100644
> --- a/doc/board/sipeed/maix.rst
> +++ b/doc/board/sipeed/maix.rst
> @@ -70,6 +70,7 @@ console shall be opened immediately. Boot output should look like the following:
>      U-Boot 2020.04-rc2-00087-g2221cc09c1-dirty (Feb 28 2020 - 13:53:09 -0500)
>  
>      DRAM:  8 MiB
> +    MMC:   spi@53000000:slot@0: 0
>      In:    serial@38000000
>      Out:   serial@38000000
>      Err:   serial@38000000
> @@ -118,14 +119,115 @@ The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000.
>  
>  The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin.
>  
> -Loading Images
> -^^^^^^^^^^^^^^
> +Booting
> +^^^^^^^
>  
> -To load a kernel, transfer it over serial.
> +The default boot process is to load and boot the files ``/uImage`` and
> +``/k210.dtb`` off of the first partition of the MMC. For Linux, this will result
> +in an output like
>  
>  .. code-block:: none
>  
> -    => loady 80000000 1500000
> +    U-Boot 2020.10-00691-gd1d651d988-dirty (Oct 16 2020 - 17:05:24 -0400)
> +
> +    DRAM:  8 MiB
> +    MMC:   spi@53000000:slot@0: 0
> +    Loading Environment from SPIFlash... SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
> +    OK
> +    In:    serial@38000000
> +    Out:   serial@38000000
> +    Err:   serial@38000000
> +    Hit any key to stop autoboot:  0
> +    1827380 bytes read in 1044 ms (1.7 MiB/s)
> +    13428 bytes read in 10 ms (1.3 MiB/s)
> +    ## Booting kernel from Legacy Image at 80060000 ...
> +       Image Name:   linux
> +       Image Type:   RISC-V Linux Kernel Image (uncompressed)
> +       Data Size:    1827316 Bytes = 1.7 MiB
> +       Load Address: 80000000
> +       Entry Point:  80000000
> +       Verifying Checksum ... OK
> +    ## Flattened Device Tree blob at 80400000
> +       Booting using the fdt blob at 0x80400000
> +       Loading Kernel Image
> +       Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
> +
> +    Starting kernel ...
> +
> +    [    0.000000] Linux version 5.9.0-00021-g6dcc2f0814c6-dirty (sean@godwin) (riscv64-linux-gnu-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35) #34 SMP Fri Oct 16 14:40:57 EDT 2020
> +    [    0.000000] earlycon: sifive0 at MMIO 0x0000000038000000 (options '115200n8')
> +    [    0.000000] printk: bootconsole [sifive0] enabled
> +    [    0.000000] Zone ranges:
> +    [    0.000000]   DMA32    [mem 0x0000000080000000-0x00000000807fffff]
> +    [    0.000000]   Normal   empty
> +    [    0.000000] Movable zone start for each node
> +    [    0.000000] Early memory node ranges
> +    [    0.000000]   node   0: [mem 0x0000000080000000-0x00000000807fffff]
> +    [    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x00000000807fffff]
> +    [    0.000000] riscv: ISA extensions acdfgim
> +    [    0.000000] riscv: ELF capabilities acdfim
> +    [    0.000000] percpu: max_distance=0x18000 too large for vmalloc space 0x0
> +    [    0.000000] percpu: Embedded 12 pages/cpu s18848 r0 d30304 u49152
> +    [    0.000000] Built 1 zonelists, mobility grouping off.  Total pages: 2020
> +    [    0.000000] Kernel command line: earlycon console=ttySIF0
> +    [    0.000000] Dentry cache hash table entries: 1024 (order: 1, 8192 bytes, linear)
> +    [    0.000000] Inode-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
> +    [    0.000000] Sorting __ex_table...
> +    [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
> +    [    0.000000] Memory: 6004K/8192K available (1139K kernel code, 126K rwdata, 198K rodata, 90K init, 81K bss, 2188K reserved, 0K cma-reserved)
> +    [    0.000000] rcu: Hierarchical RCU implementation.
> +    [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
> +    [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
> +    [    0.000000] riscv-intc: 64 local interrupts mapped
> +    [    0.000000] plic: interrupt-controller@C000000: mapped 65 interrupts with 2 handlers for 2 contexts.
> +    [    0.000000] random: get_random_bytes called from 0x00000000800019a8 with crng_init=0
> +    [    0.000000] k210-clk: clock-controller
> +    [    0.000000] k210-clk: clock-controller: fixed-rate 26 MHz osc base clock
> +    [    0.000000] clint: clint@2000000: timer running at 7800000 Hz
> +    [    0.000000] clocksource: clint_clocksource: mask: 0xffffffffffffffff max_cycles: 0x3990be68b, max_idle_ns: 881590404272 ns
> +    [    0.000014] sched_clock: 64 bits at 7MHz, resolution 128ns, wraps every 4398046511054ns
> +    [    0.008450] Console: colour dummy device 80x25
> +    [    0.012494] Calibrating delay loop (skipped), value calculated using timer frequency.. 15.60 BogoMIPS (lpj=31200)
> +    [    0.022693] pid_max: default: 4096 minimum: 301
> +    [    0.027352] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
> +    [    0.034428] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear)
> +    [    0.045099] rcu: Hierarchical SRCU implementation.
> +    [    0.050048] smp: Bringing up secondary CPUs ...
> +    [    0.055417] smp: Brought up 1 node, 2 CPUs
> +    [    0.059602] devtmpfs: initialized
> +    [    0.082796] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
> +    [    0.091820] futex hash table entries: 16 (order: -2, 1024 bytes, linear)
> +    [    0.098507] pinctrl core: initialized pinctrl subsystem
> +    [    0.140938] clocksource: Switched to clocksource clint_clocksource
> +    [    0.247216] workingset: timestamp_bits=62 max_order=11 bucket_order=0
> +    [    0.277392] k210-fpioa 502b0000.pinmux: K210 FPIOA pin controller
> +    [    0.291724] k210-sysctl 50440000.syscon: K210 system controller
> +    [    0.305317] k210-rst 50440000.syscon:reset-controller: K210 reset controller
> +    [    0.313808] 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0
> +    [    0.322712] printk: console [ttySIF0] enabled
> +    [    0.322712] printk: console [ttySIF0] enabled
> +    [    0.331328] printk: bootconsole [sifive0] disabled
> +    [    0.331328] printk: bootconsole [sifive0] disabled
> +    [    0.353347] Freeing unused kernel memory: 88K
> +    [    0.357004] This architecture does not have kernel memory protection.
> +    [    0.363397] Run /init as init process
> +
> +Loading, Booting, and Storing Images
> +------------------------------------
> +
> +.. _loading:
> +
> +Loading Images
> +^^^^^^^^^^^^^^
> +
> +Serial
> +""""""
> +
> +Use the ``loady`` command to load images over serial.
> +
> +.. code-block:: none
> +
> +    => loady $loadaddr 1500000
>      ## Switch baudrate to 1500000 bps and press ENTER ...
>  
>      *** baud: 1500000
> @@ -150,6 +252,61 @@ To load a kernel, transfer it over serial.
>      *** baud: 115200 ***
>      =>
>  
> +This command does not set ``$filesize``, so it may need to be set manually.
> +
> +SPI Flash
> +"""""""""
> +
> +To load an image off of SPI flash, first set up a partition as described in
> +:ref:`partitions`. Then, use ``mtd`` to load that partition
> +
> +.. code-block:: none
> +
> +    => sf probe
> +    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
> +    => mtd read linux $loadaddr
> +    Reading 2097152 byte(s) at offset 0x00000000
> +
> +This command does not set ``$filesize``, so it may need to be set manually.
> +
> +MMC
> +"""
> +
> +The MMC device number is 0. To list partitions on the device, use ``part``:
> +
> +.. code-block:: none
> +
> +    => part list mmc 0
> +
> +    Partition Map for MMC device 0  --   Partition Type: EFI
> +
> +    Part    Start LBA       End LBA          Name
> +            Attributes
> +            Type GUID
> +            Partition GUID
> +      1     0x00000800      0x039effde      "boot"
> +            attrs:  0x0000000000000000
> +            type:   c12a7328-f81f-11d2-ba4b-00a0c93ec93b
> +            guid:   96161f7d-7113-4cc7-9a24-08ab7fc5cb72
> +
> +To list files, use ``ls``:
> +
> +.. code-block:: none
> +
> +    => ls mmc 0:1
> +    <DIR>       4096 .
> +    <DIR>       4096 ..
> +    <DIR>      16384 lost+found
> +               13428 k210.dtb
> +             1827380 uImage
> +
> +To load a file, use ``load``:
> +
> +.. code-block:: none
> +
> +    => load mmc 0:1 $loadaddr uImage
> +    1827380 bytes read in 1049 ms (1.7 MiB/s)
> +
>  Running Programs
>  ^^^^^^^^^^^^^^^^
>  
> @@ -160,20 +317,6 @@ To run a bare binary, use the ``go`` command:
>  
>  .. code-block:: none
>  
> -    => loady
> -    ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
> -    C
> -    *** file: ./examples/standalone/hello_world.bin
> -    $ sz -vv ./examples/standalone/hello_world.bin
> -    Sending: hello_world.bin
> -    Bytes Sent:   4864   BPS:649
> -    Sending:
> -    Ymodem sectors/kbytes sent:   0/ 0k
> -    Transfer complete
> -
> -    *** exit status: 0 ***
> -    (CAN) packets, 5 retries
> -    ## Total Size      = 0x000012f8 = 4856 Bytes
>      => go 80000000
>      ## Starting application at 0x80000000 ...
>      Example expects ABI version 9
> @@ -184,51 +327,127 @@ To run a bare binary, use the ``go`` command:
>      argv[1] = "<NULL>"
>      Hit any key to exit ...
>  
> +Note that this will only start a program on one hart. As-of this writing it is
> +only possible to start a program on multiple harts using the ``bootm`` command.
> +
>  Legacy Images
>  """""""""""""
>  
> -To run legacy images, use the ``bootm`` command:
> +To create a legacy image, use ``tools/mkimage``:
>  
>  .. code-block:: none
>  
> -    $ tools/mkimage -A riscv -O u-boot -T standalone -C none -a 80000000 -e 80000000 -d examples/standalone/hello_world.bin hello_world.img
> -    Image Name:
> -    Created:      Thu Mar  5 12:04:10 2020
> -    Image Type:   RISC-V U-Boot Standalone Program (uncompressed)
> -    Data Size:    4856 Bytes = 4.74 KiB = 0.00 MiB
> +    $ tools/mkimage -A riscv -O linux -T kernel -C none -a 0x80000000 -e 0x80000000 -n linux -d ../linux-git/arch/riscv/boot/Image uImage
> +    Image Name:   linux
> +    Created:      Fri Oct 16 17:36:32 2020
> +    Image Type:   RISC-V Linux Kernel Image (uncompressed)
> +    Data Size:    1827316 Bytes = 1784.49 KiB = 1.74 MiB
>      Load Address: 80000000
>      Entry Point:  80000000
>  
> -    $ picocom -b 115200 /dev/ttyUSB0
> -    => loady
> -    ## Ready for binary (ymodem) download to 0x80000000 at 115200 bps...
> -    C
> -    *** file: hello_world.img
> -    $ sz -vv hello_world.img
> -    Sending: hello_world.img
> -    Bytes Sent:   4992   BPS:665
> -    Sending:
> -    Ymodem sectors/kbytes sent:   0/ 0k
> -    Transfer complete
> +The ``bootm`` command also requires an FDT, even if the image doesn't require
> +one. After loading the image to ``$loadaddr`` and the FDT to ``$fdt_addr_r``,
> +boot with:
>  
> -    *** exit status: 0 ***
> -    CAN) packets, 3 retries
> -    ## Total Size      = 0x00001338 = 4920 Bytes
> -    => bootm
> -    ## Booting kernel from Legacy Image at 80000000 ...
> -       Image Name:
> -       Image Type:   RISC-V U-Boot Standalone Program (uncompressed)
> -       Data Size:    4856 Bytes = 4.7 KiB
> +.. code-block:: none
> +
> +    => bootm $loadaddr - $fdt_addr_r
> +    ## Booting kernel from Legacy Image at 80060000 ...
> +       Image Name:   linux
> +       Image Type:   RISC-V Linux Kernel Image (uncompressed)
> +       Data Size:    1827316 Bytes = 1.7 MiB
>         Load Address: 80000000
>         Entry Point:  80000000
>         Verifying Checksum ... OK
> -       Loading Standalone Program
> -    Example expects ABI version 9
> -    Actual U-Boot ABI version 9
> -    Hello World
> -    argc = 0
> -    argv[0] = "<NULL>"
> -    Hit any key to exit ...
> +    ## Flattened Device Tree blob at 80400000
> +       Booting using the fdt blob at 0x80400000
> +       Loading Kernel Image
> +       Loading Device Tree to 00000000803f9000, end 00000000803ff473 ... OK
> +
> +    Starting kernel ...
> +
> +The FDT is verified after the kernel is relocated, so it must be loaded high
> +enough so that it won't be overwritten. The default values for ``$loadaddr``
> +and ``$fdt_addr_r`` should provide ample headroom for most use-cases.
> +
> +Flashing Images
> +^^^^^^^^^^^^^^^
> +
> +SPI Flash
> +"""""""""
> +
> +To flash data to SPI flash, first load it using one of the methods in
> +:ref:`loading`. Addiotionally, create some partitions as described in
> +:ref:`partitions`. Then use the ``mtd`` command:
> +
> +.. code-block:: none
> +
> +    => sf probe
> +    SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB
> +    => mtd write linux $loadaddr 0 $filesize
> +    Writing 2478162 byte(s) at offset 0x00000000
> +
> +Note that in order to write a bootable image, a header and tailer must be added.
> +
> +MMC
> +"""
> +
> +MMC writes are unsupported for now.
> +
> +SPI Flash
> +^^^^^^^^^
> +
> +Sipeed MAIX boards typically provide around 16 MiB of SPI NOR flash. U-Boot is
> +stored in the first 1 MiB or so of this flash. U-Boot's environment is stored at
> +the end of flash.
> +
> +.. _partitions:
> +
> +Partitions
> +""""""""""
> +
> +There is no set data layout. The default partition layout only allocates
> +partitions for U-Boot and its default environment
> +
> +.. code-block:: none
> +
> +    => mtd list
> +    List of MTD devices:
> +    * nor0
> +      - type: NOR flash
> +      - block size: 0x1000 bytes
> +      - min I/O: 0x1 bytes
> +      - 0x000000000000-0x000001000000 : "nor0"
> +          - 0x000000000000-0x000000100000 : "u-boot"
> +          - 0x000000fff000-0x000001000000 : "env"
> +
> +As an example, to allocate 2MiB for Linux and (almost) 13 MiB for other data,
> +set the ``mtdparts`` like:
> +
> +.. code-block:: none
> +
> +    => env set mtdparts nor0:1M(u-boot),2M(linux),0xcff000(data),0x1000@0xfff000(env)
> +    => mtd list
> +    List of MTD devices:
> +    * nor0
> +      - type: NOR flash
> +      - block size: 0x1000 bytes
> +      - min I/O: 0x1 bytes
> +      - 0x000000000000-0x000001000000 : "nor0"
> +          - 0x000000000000-0x000000100000 : "u-boot"
> +          - 0x000000100000-0x000000300000 : "linux"
> +          - 0x000000300000-0x000000fff000 : "data"
> +          - 0x000000fff000-0x000001000000 : "env"
> +
> +To make these changes permanent, save the environment:
> +
> +.. code-block:: none
> +
> +    => env save
> +    Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
> +    OK
> +
> +U-Boot will always load the environment from the last 4 KiB of flash.
>  
>  Pin Assignment
>  --------------
> diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
> index 36ff522e4b..08acb25075 100644
> --- a/include/configs/sipeed-maix.h
> +++ b/include/configs/sipeed-maix.h
> @@ -24,10 +24,13 @@
>  #ifndef CONFIG_EXTRA_ENV_SETTINGS
>  #define CONFIG_EXTRA_ENV_SETTINGS \
>   "loadaddr=0x80060000\0" \
> - "fdt_addr_r=0x80028000\0" \
> + "fdt_addr_r=0x80400000\0" \
>   "scriptaddr=0x80020000\0" \
>   "kernel_addr_r=0x80060000\0" \
> - "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
> + "fdtfile=kendryte/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
> + "k210_bootcmd=load mmc 0:1 $loadaddr /uImage && " \
> + "load mmc 0:1 $fdt_addr_r /k210.dtb && " \
> + "bootm $loadaddr - $fdt_addr_r\0"
>  #endif
>  
>  #endif /* CONFIGS_SIPEED_MAIX_H */
>

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Re: [PATCH v4 00/13] riscv: Add SPI support for Kendryte K210

Jagan Teki-3
In reply to this post by Sean Anderson
On Sat, Oct 17, 2020 at 4:28 AM Sean Anderson <[hidden email]> wrote:

>
> This series adds support for SPI on the Kendryte K210. This covers the MMC
> slot and SPI flash on the Sipeed Maix Bit.
>
> This series makes significant changes to the designware SPI driver. I would
> really appreciate if the maintainers I CC'd could test this series and ensure
> that SPI still works on all their devices. I have tried my best not to affect
> existing devices, but I'd rather find out if this breaks stuff now rather than
> later. In particular, the method of detecting SSI_MAX_XFER_SIZE has changed
> since the last revision, and will need to be re-tested.
>
> This series was previously part of
> https://patchwork.ozlabs.org/project/uboot/list/?series=161576
>
> Changes in v4:
> - Auto-detect SSI_MAX_XFER_SIZE
> - Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
>   short succession.
> - Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
>   name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
>   way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
>   reduce the amount of instructions in those loops, even with logging enabled.
> - Enable booting from MMC
> - Fix MMC transfer errors
> - Place env in spi flash
> - Rearrange headers in designware_spi.c
> - Remove spi_enable_chip
> - Update documentation
>
> Changes in v3:
> - Lower the log level of some messages
> - Prefix user-facing logs with SPI@<address>
> - Rebase onto U-Boot master
> - Remove env and bootcmd configuration. I'm going to punt on those for now,
>   since I haven't worked out the best way to boot with SPI yet. Those
>   settings may be added back in a follow-up patch.
> - Reword error messages as "message (error %d)"
> - Synchronize compatible strings between docs and driver
> - Use constant 0x10000 instead of SZ_64K. The latter is not included on
>   some platforms and I'm too lazy to figure out what the correct header is.
>
> Changes in v2:
> - Add Gigadevice SPI chips to dependencies
> - Add external gpio cs support
> - Clean up exec_op
> - Configure ctrlr0 register layout based on compatible string
> - Convert debug calls to log_ instead of removing the ones which affect
>   timing
> - Document new compatible strings
> - Limit data transfers to 64k
> - Remove broken-wp property (implicit due to no wp gpio)
> - Remove ctrl0 field offsets from device tree
> - Switch to new compatible strings
> - Switch to new pinmux binding style
>
> Sean Anderson (13):
>   spi: dw: Fix driving MOSI low while recieving
>   spi: dw: Convert calls to debug to dev_*
>   spi: dw: Rename "cs-gpio" to "cs-gpios"
>   spi: dw: Use generic function to read reg address
>   spi: dw: Rename registers to match datasheet
>   spi: dw: Remove spi_enable_chip
>   spi: dw: Rearrange struct dw_spi_priv
>   spi: dw: Add SoC-specific compatible strings
>   spi: dw: Add support for multiple CTRLR0 layouts
>   spi: dw: Document devicetree binding
>   spi: dw: Add mem_ops
>   riscv: Add device tree bindings for SPI
>   riscv: Add support for SPI on Kendryte K210

Except for this patch with HUSH PARSER missing rest look fine for me.

Reviewed-by: Jagan Teki <[hidden email]>
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Re: [PATCH v4 00/13] riscv: Add SPI support for Kendryte K210

Jagan Teki-3
On Sat, Oct 24, 2020 at 12:14 AM Jagan Teki <[hidden email]> wrote:

>
> On Sat, Oct 17, 2020 at 4:28 AM Sean Anderson <[hidden email]> wrote:
> >
> > This series adds support for SPI on the Kendryte K210. This covers the MMC
> > slot and SPI flash on the Sipeed Maix Bit.
> >
> > This series makes significant changes to the designware SPI driver. I would
> > really appreciate if the maintainers I CC'd could test this series and ensure
> > that SPI still works on all their devices. I have tried my best not to affect
> > existing devices, but I'd rather find out if this breaks stuff now rather than
> > later. In particular, the method of detecting SSI_MAX_XFER_SIZE has changed
> > since the last revision, and will need to be re-tested.
> >
> > This series was previously part of
> > https://patchwork.ozlabs.org/project/uboot/list/?series=161576
> >
> > Changes in v4:
> > - Auto-detect SSI_MAX_XFER_SIZE
> > - Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
> >   short succession.
> > - Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
> >   name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
> >   way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
> >   reduce the amount of instructions in those loops, even with logging enabled.
> > - Enable booting from MMC
> > - Fix MMC transfer errors
> > - Place env in spi flash
> > - Rearrange headers in designware_spi.c
> > - Remove spi_enable_chip
> > - Update documentation
> >
> > Changes in v3:
> > - Lower the log level of some messages
> > - Prefix user-facing logs with SPI@<address>
> > - Rebase onto U-Boot master
> > - Remove env and bootcmd configuration. I'm going to punt on those for now,
> >   since I haven't worked out the best way to boot with SPI yet. Those
> >   settings may be added back in a follow-up patch.
> > - Reword error messages as "message (error %d)"
> > - Synchronize compatible strings between docs and driver
> > - Use constant 0x10000 instead of SZ_64K. The latter is not included on
> >   some platforms and I'm too lazy to figure out what the correct header is.
> >
> > Changes in v2:
> > - Add Gigadevice SPI chips to dependencies
> > - Add external gpio cs support
> > - Clean up exec_op
> > - Configure ctrlr0 register layout based on compatible string
> > - Convert debug calls to log_ instead of removing the ones which affect
> >   timing
> > - Document new compatible strings
> > - Limit data transfers to 64k
> > - Remove broken-wp property (implicit due to no wp gpio)
> > - Remove ctrl0 field offsets from device tree
> > - Switch to new compatible strings
> > - Switch to new pinmux binding style
> >
> > Sean Anderson (13):
> >   spi: dw: Fix driving MOSI low while recieving
> >   spi: dw: Convert calls to debug to dev_*
> >   spi: dw: Rename "cs-gpio" to "cs-gpios"
> >   spi: dw: Use generic function to read reg address
> >   spi: dw: Rename registers to match datasheet
> >   spi: dw: Remove spi_enable_chip
> >   spi: dw: Rearrange struct dw_spi_priv
> >   spi: dw: Add SoC-specific compatible strings
> >   spi: dw: Add support for multiple CTRLR0 layouts
> >   spi: dw: Document devicetree binding
> >   spi: dw: Add mem_ops
> >   riscv: Add device tree bindings for SPI
> >   riscv: Add support for SPI on Kendryte K210
>
> Except for this patch with HUSH PARSER missing rest look fine for me.
>
> Reviewed-by: Jagan Teki <[hidden email]>

Applied to u-boot-spi/master
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Re: [PATCH v4 00/13] riscv: Add SPI support for Kendryte K210

Sean Anderson
On 10/24/20 10:58 AM, Jagan Teki wrote:

> On Sat, Oct 24, 2020 at 12:14 AM Jagan Teki <[hidden email]> wrote:
>>
>> On Sat, Oct 17, 2020 at 4:28 AM Sean Anderson <[hidden email]> wrote:
>>>
>>> This series adds support for SPI on the Kendryte K210. This covers the MMC
>>> slot and SPI flash on the Sipeed Maix Bit.
>>>
>>> This series makes significant changes to the designware SPI driver. I would
>>> really appreciate if the maintainers I CC'd could test this series and ensure
>>> that SPI still works on all their devices. I have tried my best not to affect
>>> existing devices, but I'd rather find out if this breaks stuff now rather than
>>> later. In particular, the method of detecting SSI_MAX_XFER_SIZE has changed
>>> since the last revision, and will need to be re-tested.
>>>
>>> This series was previously part of
>>> https://patchwork.ozlabs.org/project/uboot/list/?series=161576
>>>
>>> Changes in v4:
>>> - Auto-detect SSI_MAX_XFER_SIZE
>>> - Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
>>>   short succession.
>>> - Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
>>>   name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
>>>   way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
>>>   reduce the amount of instructions in those loops, even with logging enabled.
>>> - Enable booting from MMC
>>> - Fix MMC transfer errors
>>> - Place env in spi flash
>>> - Rearrange headers in designware_spi.c
>>> - Remove spi_enable_chip
>>> - Update documentation
>>>
>>> Changes in v3:
>>> - Lower the log level of some messages
>>> - Prefix user-facing logs with SPI@<address>
>>> - Rebase onto U-Boot master
>>> - Remove env and bootcmd configuration. I'm going to punt on those for now,
>>>   since I haven't worked out the best way to boot with SPI yet. Those
>>>   settings may be added back in a follow-up patch.
>>> - Reword error messages as "message (error %d)"
>>> - Synchronize compatible strings between docs and driver
>>> - Use constant 0x10000 instead of SZ_64K. The latter is not included on
>>>   some platforms and I'm too lazy to figure out what the correct header is.
>>>
>>> Changes in v2:
>>> - Add Gigadevice SPI chips to dependencies
>>> - Add external gpio cs support
>>> - Clean up exec_op
>>> - Configure ctrlr0 register layout based on compatible string
>>> - Convert debug calls to log_ instead of removing the ones which affect
>>>   timing
>>> - Document new compatible strings
>>> - Limit data transfers to 64k
>>> - Remove broken-wp property (implicit due to no wp gpio)
>>> - Remove ctrl0 field offsets from device tree
>>> - Switch to new compatible strings
>>> - Switch to new pinmux binding style
>>>
>>> Sean Anderson (13):
>>>   spi: dw: Fix driving MOSI low while recieving
>>>   spi: dw: Convert calls to debug to dev_*
>>>   spi: dw: Rename "cs-gpio" to "cs-gpios"
>>>   spi: dw: Use generic function to read reg address
>>>   spi: dw: Rename registers to match datasheet
>>>   spi: dw: Remove spi_enable_chip
>>>   spi: dw: Rearrange struct dw_spi_priv
>>>   spi: dw: Add SoC-specific compatible strings
>>>   spi: dw: Add support for multiple CTRLR0 layouts
>>>   spi: dw: Document devicetree binding
>>>   spi: dw: Add mem_ops
>>>   riscv: Add device tree bindings for SPI
>>>   riscv: Add support for SPI on Kendryte K210
>>
>> Except for this patch with HUSH PARSER missing rest look fine for me.

Do you want a follow-up patch for that, or did you add it?

--Sean

>> Reviewed-by: Jagan Teki <[hidden email]>
>
> Applied to u-boot-spi/master
>

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Re: [PATCH v4 00/13] riscv: Add SPI support for Kendryte K210

Jagan Teki-3
On Mon, Oct 26, 2020 at 12:54 AM Sean Anderson <[hidden email]> wrote:

>
> On 10/24/20 10:58 AM, Jagan Teki wrote:
> > On Sat, Oct 24, 2020 at 12:14 AM Jagan Teki <[hidden email]> wrote:
> >>
> >> On Sat, Oct 17, 2020 at 4:28 AM Sean Anderson <[hidden email]> wrote:
> >>>
> >>> This series adds support for SPI on the Kendryte K210. This covers the MMC
> >>> slot and SPI flash on the Sipeed Maix Bit.
> >>>
> >>> This series makes significant changes to the designware SPI driver. I would
> >>> really appreciate if the maintainers I CC'd could test this series and ensure
> >>> that SPI still works on all their devices. I have tried my best not to affect
> >>> existing devices, but I'd rather find out if this breaks stuff now rather than
> >>> later. In particular, the method of detecting SSI_MAX_XFER_SIZE has changed
> >>> since the last revision, and will need to be re-tested.
> >>>
> >>> This series was previously part of
> >>> https://patchwork.ozlabs.org/project/uboot/list/?series=161576
> >>>
> >>> Changes in v4:
> >>> - Auto-detect SSI_MAX_XFER_SIZE
> >>> - Consolidate log messages in dw_spi_xfer. We don't need to print twice in such
> >>>   short succession.
> >>> - Convert most log_xxx messages to dev_xxx. Since ceb70bb870 ("dm: Print device
> >>>   name in dev_xxx like Linux"), dev_xxx can be controlled at runtime in the same
> >>>   way as log_xxx. The log messages in dw_reader/dw_writer are not converted to
> >>>   reduce the amount of instructions in those loops, even with logging enabled.
> >>> - Enable booting from MMC
> >>> - Fix MMC transfer errors
> >>> - Place env in spi flash
> >>> - Rearrange headers in designware_spi.c
> >>> - Remove spi_enable_chip
> >>> - Update documentation
> >>>
> >>> Changes in v3:
> >>> - Lower the log level of some messages
> >>> - Prefix user-facing logs with SPI@<address>
> >>> - Rebase onto U-Boot master
> >>> - Remove env and bootcmd configuration. I'm going to punt on those for now,
> >>>   since I haven't worked out the best way to boot with SPI yet. Those
> >>>   settings may be added back in a follow-up patch.
> >>> - Reword error messages as "message (error %d)"
> >>> - Synchronize compatible strings between docs and driver
> >>> - Use constant 0x10000 instead of SZ_64K. The latter is not included on
> >>>   some platforms and I'm too lazy to figure out what the correct header is.
> >>>
> >>> Changes in v2:
> >>> - Add Gigadevice SPI chips to dependencies
> >>> - Add external gpio cs support
> >>> - Clean up exec_op
> >>> - Configure ctrlr0 register layout based on compatible string
> >>> - Convert debug calls to log_ instead of removing the ones which affect
> >>>   timing
> >>> - Document new compatible strings
> >>> - Limit data transfers to 64k
> >>> - Remove broken-wp property (implicit due to no wp gpio)
> >>> - Remove ctrl0 field offsets from device tree
> >>> - Switch to new compatible strings
> >>> - Switch to new pinmux binding style
> >>>
> >>> Sean Anderson (13):
> >>>   spi: dw: Fix driving MOSI low while recieving
> >>>   spi: dw: Convert calls to debug to dev_*
> >>>   spi: dw: Rename "cs-gpio" to "cs-gpios"
> >>>   spi: dw: Use generic function to read reg address
> >>>   spi: dw: Rename registers to match datasheet
> >>>   spi: dw: Remove spi_enable_chip
> >>>   spi: dw: Rearrange struct dw_spi_priv
> >>>   spi: dw: Add SoC-specific compatible strings
> >>>   spi: dw: Add support for multiple CTRLR0 layouts
> >>>   spi: dw: Document devicetree binding
> >>>   spi: dw: Add mem_ops
> >>>   riscv: Add device tree bindings for SPI
> >>>   riscv: Add support for SPI on Kendryte K210
> >>
> >> Except for this patch with HUSH PARSER missing rest look fine for me.
>
> Do you want a follow-up patch for that, or did you add it?

follow-up patch, please.