[PATCH v3 00/20] Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb

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[PATCH v3 00/20] Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb

David Wu
This serie of patches add rmii interface support, and support more
socs's gmac function, such as rv1108, rk3328 and rk3229.

Implement the "assign-clock-parent" and "assign-clock-rate" for rk3328,
rk3228, rk3288 and rk3368.

This series of patches is based on Philipp's branch:
https://github.com/ptomsich/u-boot-rockchip/tree/assigned-clocks-wip

Changes in v3:
- Add "set parent" for gmac
- Add "set parent" for gmac2io
- Add internal mac clk div_sel for gmac
- Add internal mac clk div_sel for gmac2io
- Fix the wrong define for uart2 iomux
- Fix the wrong define for uart2M0
- New patch
- None
- adhere to the established way of writing this to avoid future confusion
- return error if there was no set_to_rgmii ops at rgmii case
- return error if there was no set_to_rmii ops at rmii case
- set and check clock rate when gmac clock is internal pll.
- use defined symbolic constants for drive-strength

Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Clean the grf offset at gmac_rockchip.c
- New patch
- None
- Use current phy interface to set mac clock rate

David Wu (20):
  rockchip: dts: rk3399-evb: Change the tx/rx delay value for
    transmission quality
  rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb
  rockchip: grf_rv1108.h: Fix the grf offsets
  rockchip: pinctrl: rv1108: Move the iomux definitions into
    pinctrl-driver
  net: gmac_rockchip: Add support for the RV1108 GMAC
  rockchip: pinctrl: rk3328: Move the iomux definitions into
    pinctrl-driver
  rockchip: pinctrl: Add rk3328 gmac pinctrl support
  clk: rockchip: Add rk3328 gamc clock support
  net: gmac_rockchip: Add rk3328 gmac support
  rockchip: configs: Enable GMAC configs for evb-rk3328
  rockchip: dts: rk3328: Add gmac2io support
  rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb
  rockchip: pinctrl: rk322x: Move the iomux definitions into
    pinctrl-driver
  rockchip: pinctrl: Add rk322x gmac pinctrl support
  clk: rockchip: Add rk322x gamc clock support
  net: gmac_rockchip: Add support for the RK3228 GMAC
  config: evb-rk3229: Enable rk gmac configs
  ARM: dts: rk3288: Remove unused LCDC clock assigned
  clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and
    "assign-clock-rate"
  clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

 arch/arm/dts/rk3288.dtsi                        |   7 +-
 arch/arm/dts/rk3328-evb.dts                     |  30 ++
 arch/arm/dts/rk3328.dtsi                        |  19 +
 arch/arm/dts/rk3399-evb.dts                     |   4 +-
 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |   7 +
 arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 ------------------
 arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 114 -----
 arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 405 +---------------
 arch/arm/mach-rockchip/rk322x-board-spl.c       |  22 +-
 arch/arm/mach-rockchip/rk322x-board.c           |  18 +
 board/rockchip/evb_rv1108/evb_rv1108.c          |  17 +
 configs/evb-rk3229_defconfig                    |   5 +
 configs/evb-rk3288_defconfig                    |   1 +
 configs/evb-rk3328_defconfig                    |   5 +
 drivers/clk/rockchip/clk_rk322x.c               | 107 +++++
 drivers/clk/rockchip/clk_rk3288.c               | 106 ++++-
 drivers/clk/rockchip/clk_rk3328.c               | 178 +++++++
 drivers/clk/rockchip/clk_rk3368.c               |  91 +++-
 drivers/net/gmac_rockchip.c                     | 285 ++++++++++-
 drivers/pinctrl/rockchip/pinctrl_rk322x.c       | 601 ++++++++++++++++++++++++
 drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 388 +++++++++++++++
 drivers/pinctrl/rockchip/pinctrl_rv1108.c       | 399 ++++++++++++++++
 include/dt-bindings/clock/rk3288-cru.h          |   1 +
 include/dt-bindings/clock/rk3328-cru.h          |   6 +-
 24 files changed, 2270 insertions(+), 1001 deletions(-)

--
2.7.4


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[PATCH v3 01/20] rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality

David Wu
Give the mac controller the correct tx-delay and rx-delay value
for the rgmii mode transmission. If they are not matched, there
would be Ethernet packets lost, the net feature may not work.

Signed-off-by: David Wu <[hidden email]>
Acked-by: Philipp Tomsich <[hidden email]>
Reviewed-by: Philipp Tomsich <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- None

 arch/arm/dts/rk3399-evb.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index f0567c9..ed0e00e 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -279,7 +279,7 @@
  assigned-clock-parents = <&clkin_gmac>;
  pinctrl-names = "default";
  pinctrl-0 = <&rgmii_pins>;
- tx_delay = <0x10>;
- rx_delay = <0x10>;
+ tx_delay = <0x28>;
+ rx_delay = <0x11>;
  status = "okay";
 };
--
2.7.4


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[PATCH v3 02/20] rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb

David Wu
In reply to this post by David Wu
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.

Signed-off-by: David Wu <[hidden email]>
Acked-by: Philipp Tomsich <[hidden email]>
Reviewed-by: Philipp Tomsich <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- None

 configs/evb-rk3288_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index e944f97..6c67509 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
--
2.7.4


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[PATCH v3 03/20] rockchip: grf_rv1108.h: Fix the grf offsets

David Wu
In reply to this post by David Wu
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.

Signed-off-by: David Wu <[hidden email]>
Reviewed-by: Simon Glass <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index c816a5b..428cf6a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -100,13 +100,17 @@ struct rv1108_grf {
  u32 reserved14[2];
  u32 dma_con0;
  u32 dma_con1;
- u32 reserved15[539];
+ u32 reserved15[59];
  u32 uoc_status;
+ u32 reserved16[2];
  u32 host_status;
+ u32 reserved17[59];
  u32 gmac_con0;
+ u32 reserved18[191];
  u32 chip_id;
 };
-check_member(rv1108_grf, chip_id, 0xf90);
+
+check_member(rv1108_grf, chip_id, 0x0c00);
 
 /* GRF_GPIO1B_IOMUX */
 enum {
--
2.7.4


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[PATCH v3 04/20] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver

David Wu
In reply to this post by David Wu
If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.

Signed-off-by: David Wu <[hidden email]>
Reviewed-by: Philipp Tomsich <[hidden email]>
---

Changes in v3:
- Fix the wrong define for uart2M0

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399 ------------------------
 board/rockchip/evb_rv1108/evb_rv1108.c          |  17 +
 drivers/pinctrl/rockchip/pinctrl_rv1108.c       | 399 ++++++++++++++++++++++++
 3 files changed, 416 insertions(+), 399 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
index 428cf6a..76e742b 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -111,403 +111,4 @@ struct rv1108_grf {
 };
 
 check_member(rv1108_grf, chip_id, 0x0c00);
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_LCDC_D12,
- GPIO1B7_I2S_SDIO2_M0,
- GPIO1B7_GMAC_RXDV,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_LCDC_D13,
- GPIO1B6_I2S_LRCLKTX_M0,
- GPIO1B6_GMAC_RXD1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
- GPIO1B5_GPIO = 0,
- GPIO1B5_LCDC_D14,
- GPIO1B5_I2S_SDIO1_M0,
- GPIO1B5_GMAC_RXD0,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_LCDC_D15,
- GPIO1B4_I2S_MCLK_M0,
- GPIO1B4_GMAC_TXEN,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_LCDC_D16,
- GPIO1B3_I2S_SCLK_M0,
- GPIO1B3_GMAC_TXD1,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_LCDC_D17,
- GPIO1B2_I2S_SDIO_M0,
- GPIO1B2_GMAC_TXD0,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_LCDC_D9,
- GPIO1B1_PWM7,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 3,
- GPIO1B0_GPIO = 0,
- GPIO1B0_LCDC_D8,
- GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_CIF_D5,
- GPIO1C7_I2S_SDIO2_M1,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_CIF_D4,
- GPIO1C6_I2S_LRCLKTX_M1,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_LCDC_CLK,
- GPIO1C5_GMAC_CLK,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_LCDC_HSYNC,
- GPIO1C4_GMAC_MDC,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_LCDC_VSYNC,
- GPIO1C3_GMAC_MDIO,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO = 0,
- GPIO1C2_LCDC_EN,
- GPIO1C2_I2S_SDIO3_M0,
- GPIO1C2_GMAC_RXER,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_LCDC_D10,
- GPIO1C1_I2S_SDI_M0,
- GPIO1C1_PWM4,
-
- GPIO1C0_SHIFT           = 0,
- GPIO1C0_MASK = 3,
- GPIO1C0_GPIO = 0,
- GPIO1C0_LCDC_D11,
- GPIO1C0_I2S_LRCLKRX_M0,
-};
-
-/* GRF_GPIO1D_OIMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_HDMI_CEC,
- GPIO1D7_DSP_RTCK,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_HDMI_HPD_M0,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_UART2_RTSN,
- GPIO1D5_HDMI_SDA_M0,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_UART2_CTSN,
- GPIO1D4_HDMI_SCL_M0,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_UART0_SOUT,
- GPIO1D3_SPI_TXD_M0,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_UART0_SIN,
- GPIO1D2_SPI_RXD_M0,
- GPIO1D2_DSP_TDI,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_UART0_RTSN,
- GPIO1D1_SPI_CSN0_M0,
- GPIO1D1_DSP_TMS,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3,
- GPIO1D0_GPIO = 0,
- GPIO1D0_UART0_CTSN,
- GPIO1D0_SPI_CLK_M0,
- GPIO1D0_DSP_TCK,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_FLASH_D7,
- GPIO2A7_EMMC_D7,
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
- GPIO2A6_GPIO = 0,
- GPIO2A6_FLASH_D6,
- GPIO2A6_EMMC_D6,
-
- GPIO2A5_SHIFT           = 10,
- GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO            = 0,
- GPIO2A5_FLASH_D5,
- GPIO2A5_EMMC_D5,
-
- GPIO2A4_SHIFT           = 8,
- GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO            = 0,
- GPIO2A4_FLASH_D4,
- GPIO2A4_EMMC_D4,
-
- GPIO2A3_SHIFT           = 6,
- GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO            = 0,
- GPIO2A3_FLASH_D3,
- GPIO2A3_EMMC_D3,
- GPIO2A3_SFC_HOLD_IO3,
-
- GPIO2A2_SHIFT           = 4,
- GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO            = 0,
- GPIO2A2_FLASH_D2,
- GPIO2A2_EMMC_D2,
- GPIO2A2_SFC_WP_IO2,
-
- GPIO2A1_SHIFT           = 2,
- GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO            = 0,
- GPIO2A1_FLASH_D1,
- GPIO2A1_EMMC_D1,
- GPIO2A1_SFC_SO_IO1,
-
- GPIO2A0_SHIFT           = 0,
- GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO            = 0,
- GPIO2A0_FLASH_D0,
- GPIO2A0_EMMC_D0,
- GPIO2A0_SFC_SI_IO0,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_FLASH_CS1,
- GPIO2B7_SFC_CLK,
-
- GPIO2B6_SHIFT           = 12,
- GPIO2B6_MASK            = 1 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO            = 0,
- GPIO2B6_EMMC_CLKO,
-
- GPIO2B5_SHIFT           = 10,
- GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO            = 0,
- GPIO2B5_FLASH_CS0,
-
- GPIO2B4_SHIFT           = 8,
- GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO            = 0,
- GPIO2B4_FLASH_RDY,
- GPIO2B4_EMMC_CMD,
- GPIO2B4_SFC_CSN0,
-
- GPIO2B3_SHIFT           = 6,
- GPIO2B3_MASK            = 1 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO            = 0,
- GPIO2B3_FLASH_RDN,
-
- GPIO2B2_SHIFT           = 4,
- GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO            = 0,
- GPIO2B2_FLASH_WRN,
-
- GPIO2B1_SHIFT           = 2,
- GPIO2B1_MASK            = 1 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO            = 0,
- GPIO2B1_FLASH_CLE,
-
- GPIO2B0_SHIFT           = 0,
- GPIO2B0_MASK            = 1 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO            = 0,
- GPIO2B0_FLASH_ALE,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D7_SHIFT = 14,
- GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
- GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO_D0,
-
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
- GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO_CMD,
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
- GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO_CLKO,
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
- GPIO2D4_GPIO = 0,
- GPIO2D4_I2C1_SCL,
-
- GPIO2D3_SHIFT = 6,
- GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
- GPIO2D3_GPIO = 0,
- GPIO2D3_I2C1_SDA,
-
- GPIO2D2_SHIFT = 4,
- GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
- GPIO2D2_GPIO = 0,
- GPIO2D2_UART2_SOUT_M0,
- GPIO2D2_JTAG_TCK,
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART2_SIN_M0,
- GPIO2D1_JTAG_TMS,
- GPIO2D1_DSP_TMS,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_CTSN,
- GPIO2D0_SPI_CLK_M0,
- GPIO2D0_DSP_TCK,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
- GPIO3A7_SHIFT = 14,
- GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
- GPIO3A7_GPIO = 0,
-
- GPIO3A6_SHIFT = 12,
- GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
- GPIO3A6_GPIO = 0,
- GPIO3A6_UART1_SOUT,
-
- GPIO3A5_SHIFT = 10,
- GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
- GPIO3A5_GPIO = 0,
- GPIO3A5_UART1_SIN,
-
- GPIO3A4_SHIFT = 8,
- GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
- GPIO3A4_GPIO = 0,
- GPIO3A4_UART1_CTSN,
-
- GPIO3A3_SHIFT = 6,
- GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
- GPIO3A3_GPIO = 0,
- GPIO3A3_UART1_RTSN,
-
- GPIO3A2_SHIFT = 4,
- GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
- GPIO3A2_GPIO = 0,
- GPIO3A2_SDIO_D3,
-
- GPIO3A1_SHIFT = 2,
- GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
- GPIO3A1_GPIO = 0,
- GPIO3A1_SDIO_D2,
-
- GPIO3A0_SHIFT = 0,
- GPIO3A0_MASK = 1,
- GPIO3A0_GPIO = 0,
- GPIO3A0_SDIO_D1,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C7_SHIFT = 14,
- GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
- GPIO3C7_GPIO = 0,
- GPIO3C7_CIF_CLKI,
-
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_CIF_VSYNC,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_SDMMC_CMD,
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
- GPIO3C4_GPIO = 0,
- GPIO3C4_SDMMC_CLKO,
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
- GPIO3C3_GPIO = 0,
- GPIO3C3_SDMMC_D0,
- GPIO3C3_UART2_SOUT_M1,
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
- GPIO3C2_GPIO = 0,
- GPIO3C2_SDMMC_D1,
- GPIO3C2_UART2_SIN_M1,
-
- GPIOC1_SHIFT = 2,
- GPIOC1_MASK = 1 << GPIOC1_SHIFT,
- GPIOC1_GPIO = 0,
- GPIOC1_SDMMC_D2,
-
- GPIOC0_SHIFT = 0,
- GPIOC0_MASK = 1,
- GPIO3C0_GPIO = 0,
- GPIO3C0_SDMMC_D3,
-};
 #endif
diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c
index fe37eac..54bd08b 100644
--- a/board/rockchip/evb_rv1108/evb_rv1108.c
+++ b/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -16,6 +16,23 @@ int mach_cpu_init(void)
 {
  int node;
  struct rv1108_grf *grf;
+ enum {
+ GPIO3C3_SHIFT           = 6,
+ GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
+
+ GPIO3C2_SHIFT           = 4,
+ GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
+
+ GPIO2D2_SHIFT = 4,
+ GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
+ GPIO2D2_GPIO            = 0,
+ GPIO2D2_UART2_SOUT_M0,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO            = 0,
+ GPIO2D1_UART2_SIN_M0,
+ };
 
  node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
  grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
index cda94f4..035f01a 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
@@ -20,6 +20,405 @@ struct rv1108_pinctrl_priv {
  struct rv1108_grf *grf;
 };
 
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_LCDC_D12,
+ GPIO1B7_I2S_SDIO2_M0,
+ GPIO1B7_GMAC_RXDV,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_LCDC_D13,
+ GPIO1B6_I2S_LRCLKTX_M0,
+ GPIO1B6_GMAC_RXD1,
+
+ GPIO1B5_SHIFT = 10,
+ GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
+ GPIO1B5_GPIO = 0,
+ GPIO1B5_LCDC_D14,
+ GPIO1B5_I2S_SDIO1_M0,
+ GPIO1B5_GMAC_RXD0,
+
+ GPIO1B4_SHIFT = 8,
+ GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
+ GPIO1B4_GPIO = 0,
+ GPIO1B4_LCDC_D15,
+ GPIO1B4_I2S_MCLK_M0,
+ GPIO1B4_GMAC_TXEN,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_LCDC_D16,
+ GPIO1B3_I2S_SCLK_M0,
+ GPIO1B3_GMAC_TXD1,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_LCDC_D17,
+ GPIO1B2_I2S_SDIO_M0,
+ GPIO1B2_GMAC_TXD0,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_LCDC_D9,
+ GPIO1B1_PWM7,
+
+ GPIO1B0_SHIFT = 0,
+ GPIO1B0_MASK = 3,
+ GPIO1B0_GPIO = 0,
+ GPIO1B0_LCDC_D8,
+ GPIO1B0_PWM6,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_SHIFT = 14,
+ GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_CIF_D5,
+ GPIO1C7_I2S_SDIO2_M1,
+
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_CIF_D4,
+ GPIO1C6_I2S_LRCLKTX_M1,
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_LCDC_CLK,
+ GPIO1C5_GMAC_CLK,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_LCDC_HSYNC,
+ GPIO1C4_GMAC_MDC,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_LCDC_VSYNC,
+ GPIO1C3_GMAC_MDIO,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_LCDC_EN,
+ GPIO1C2_I2S_SDIO3_M0,
+ GPIO1C2_GMAC_RXER,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_LCDC_D10,
+ GPIO1C1_I2S_SDI_M0,
+ GPIO1C1_PWM4,
+
+ GPIO1C0_SHIFT           = 0,
+ GPIO1C0_MASK = 3,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_LCDC_D11,
+ GPIO1C0_I2S_LRCLKRX_M0,
+};
+
+/* GRF_GPIO1D_OIMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_HDMI_CEC,
+ GPIO1D7_DSP_RTCK,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_HDMI_HPD_M0,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_UART2_RTSN,
+ GPIO1D5_HDMI_SDA_M0,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_UART2_CTSN,
+ GPIO1D4_HDMI_SCL_M0,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_UART0_SOUT,
+ GPIO1D3_SPI_TXD_M0,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_UART0_SIN,
+ GPIO1D2_SPI_RXD_M0,
+ GPIO1D2_DSP_TDI,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_UART0_RTSN,
+ GPIO1D1_SPI_CSN0_M0,
+ GPIO1D1_DSP_TMS,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_UART0_CTSN,
+ GPIO1D0_SPI_CLK_M0,
+ GPIO1D0_DSP_TCK,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_FLASH_D7,
+ GPIO2A7_EMMC_D7,
+
+ GPIO2A6_SHIFT = 12,
+ GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
+ GPIO2A6_GPIO = 0,
+ GPIO2A6_FLASH_D6,
+ GPIO2A6_EMMC_D6,
+
+ GPIO2A5_SHIFT           = 10,
+ GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO            = 0,
+ GPIO2A5_FLASH_D5,
+ GPIO2A5_EMMC_D5,
+
+ GPIO2A4_SHIFT           = 8,
+ GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO            = 0,
+ GPIO2A4_FLASH_D4,
+ GPIO2A4_EMMC_D4,
+
+ GPIO2A3_SHIFT           = 6,
+ GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO            = 0,
+ GPIO2A3_FLASH_D3,
+ GPIO2A3_EMMC_D3,
+ GPIO2A3_SFC_HOLD_IO3,
+
+ GPIO2A2_SHIFT           = 4,
+ GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO            = 0,
+ GPIO2A2_FLASH_D2,
+ GPIO2A2_EMMC_D2,
+ GPIO2A2_SFC_WP_IO2,
+
+ GPIO2A1_SHIFT           = 2,
+ GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO            = 0,
+ GPIO2A1_FLASH_D1,
+ GPIO2A1_EMMC_D1,
+ GPIO2A1_SFC_SO_IO1,
+
+ GPIO2A0_SHIFT           = 0,
+ GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO            = 0,
+ GPIO2A0_FLASH_D0,
+ GPIO2A0_EMMC_D0,
+ GPIO2A0_SFC_SI_IO0,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_FLASH_CS1,
+ GPIO2B7_SFC_CLK,
+
+ GPIO2B6_SHIFT           = 12,
+ GPIO2B6_MASK            = 1 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO            = 0,
+ GPIO2B6_EMMC_CLKO,
+
+ GPIO2B5_SHIFT           = 10,
+ GPIO2B5_MASK            = 1 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO            = 0,
+ GPIO2B5_FLASH_CS0,
+
+ GPIO2B4_SHIFT           = 8,
+ GPIO2B4_MASK            = 3 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO            = 0,
+ GPIO2B4_FLASH_RDY,
+ GPIO2B4_EMMC_CMD,
+ GPIO2B4_SFC_CSN0,
+
+ GPIO2B3_SHIFT           = 6,
+ GPIO2B3_MASK            = 1 << GPIO2B3_SHIFT,
+ GPIO2B3_GPIO            = 0,
+ GPIO2B3_FLASH_RDN,
+
+ GPIO2B2_SHIFT           = 4,
+ GPIO2B2_MASK            = 1 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO            = 0,
+ GPIO2B2_FLASH_WRN,
+
+ GPIO2B1_SHIFT           = 2,
+ GPIO2B1_MASK            = 1 << GPIO2B1_SHIFT,
+ GPIO2B1_GPIO            = 0,
+ GPIO2B1_FLASH_CLE,
+
+ GPIO2B0_SHIFT           = 0,
+ GPIO2B0_MASK            = 1 << GPIO2B0_SHIFT,
+ GPIO2B0_GPIO            = 0,
+ GPIO2B0_FLASH_ALE,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D7_SHIFT = 14,
+ GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
+ GPIO2D7_GPIO = 0,
+ GPIO2D7_SDIO_D0,
+
+ GPIO2D6_SHIFT = 12,
+ GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
+ GPIO2D6_GPIO = 0,
+ GPIO2D6_SDIO_CMD,
+
+ GPIO2D5_SHIFT = 10,
+ GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
+ GPIO2D5_GPIO = 0,
+ GPIO2D5_SDIO_CLKO,
+
+ GPIO2D4_SHIFT = 8,
+ GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
+ GPIO2D4_GPIO = 0,
+ GPIO2D4_I2C1_SCL,
+
+ GPIO2D3_SHIFT = 6,
+ GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
+ GPIO2D3_GPIO = 0,
+ GPIO2D3_I2C1_SDA,
+
+ GPIO2D2_SHIFT = 4,
+ GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
+ GPIO2D2_GPIO = 0,
+ GPIO2D2_UART2_SOUT_M0,
+ GPIO2D2_JTAG_TCK,
+
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_UART2_SIN_M0,
+ GPIO2D1_JTAG_TMS,
+ GPIO2D1_DSP_TMS,
+
+ GPIO2D0_SHIFT = 0,
+ GPIO2D0_MASK = 3,
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_UART0_CTSN,
+ GPIO2D0_SPI_CLK_M0,
+ GPIO2D0_DSP_TCK,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+ GPIO3A7_SHIFT = 14,
+ GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
+ GPIO3A7_GPIO = 0,
+
+ GPIO3A6_SHIFT = 12,
+ GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
+ GPIO3A6_GPIO = 0,
+ GPIO3A6_UART1_SOUT,
+
+ GPIO3A5_SHIFT = 10,
+ GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
+ GPIO3A5_GPIO = 0,
+ GPIO3A5_UART1_SIN,
+
+ GPIO3A4_SHIFT = 8,
+ GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
+ GPIO3A4_GPIO = 0,
+ GPIO3A4_UART1_CTSN,
+
+ GPIO3A3_SHIFT = 6,
+ GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
+ GPIO3A3_GPIO = 0,
+ GPIO3A3_UART1_RTSN,
+
+ GPIO3A2_SHIFT = 4,
+ GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_SDIO_D3,
+
+ GPIO3A1_SHIFT = 2,
+ GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
+ GPIO3A1_GPIO = 0,
+ GPIO3A1_SDIO_D2,
+
+ GPIO3A0_SHIFT = 0,
+ GPIO3A0_MASK = 1,
+ GPIO3A0_GPIO = 0,
+ GPIO3A0_SDIO_D1,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C7_SHIFT = 14,
+ GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
+ GPIO3C7_GPIO = 0,
+ GPIO3C7_CIF_CLKI,
+
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_CIF_VSYNC,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_SDMMC_CMD,
+
+ GPIO3C4_SHIFT = 8,
+ GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
+ GPIO3C4_GPIO = 0,
+ GPIO3C4_SDMMC_CLKO,
+
+ GPIO3C3_SHIFT = 6,
+ GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
+ GPIO3C3_GPIO = 0,
+ GPIO3C3_SDMMC_D0,
+ GPIO3C3_UART2_SOUT_M1,
+
+ GPIO3C2_SHIFT = 4,
+ GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
+ GPIO3C2_GPIO = 0,
+ GPIO3C2_SDMMC_D1,
+ GPIO3C2_UART2_SIN_M1,
+
+ GPIOC1_SHIFT = 2,
+ GPIOC1_MASK = 1 << GPIOC1_SHIFT,
+ GPIOC1_GPIO = 0,
+ GPIOC1_SDMMC_D2,
+
+ GPIOC0_SHIFT = 0,
+ GPIOC0_MASK = 1,
+ GPIO3C0_GPIO = 0,
+ GPIO3C0_SDMMC_D3,
+};
+
 static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
 {
  switch (uart_id) {
--
2.7.4


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[PATCH v3 05/20] net: gmac_rockchip: Add support for the RV1108 GMAC

David Wu
In reply to this post by David Wu
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- return error if there was no set_to_rgmii ops at rgmii case
- return error if there was no set_to_rmii ops at rmii case
- set and check clock rate when gmac clock is internal pll.

Changes in v2:
- Add check whether the set rgmii/rmii function is a valid function pointer
- Clean the grf offset at gmac_rockchip.c
- Use current phy interface to set mac clock rate

 drivers/net/gmac_rockchip.c | 115 +++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 109 insertions(+), 6 deletions(-)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 586ccbf..cfffe29 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -18,6 +18,7 @@
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
+#include <asm/arch/grf_rv1108.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 #include "designware.h"
@@ -31,12 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 struct gmac_rockchip_platdata {
  struct dw_eth_pdata dw_eth_pdata;
+ bool clock_input;
  int tx_delay;
  int rx_delay;
 };
 
 struct rk_gmac_ops {
  int (*fix_mac_speed)(struct dw_eth_dev *priv);
+ void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
  void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
 };
 
@@ -44,6 +47,13 @@ struct rk_gmac_ops {
 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
 {
  struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
+ const char *string;
+
+ string = dev_read_string(dev, "clock_in_out");
+ if (!strcmp(string, "input"))
+ pdata->clock_input = true;
+ else
+ pdata->clock_input = false;
 
  /* Check the new naming-style first... */
  pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT);
@@ -142,6 +152,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  return 0;
 }
 
+static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
+{
+ struct rv1108_grf *grf;
+ int clk, speed;
+ enum {
+ RV1108_GMAC_SPEED_MASK = BIT(2),
+ RV1108_GMAC_SPEED_10M = 0 << 2,
+ RV1108_GMAC_SPEED_100M = 1 << 2,
+ RV1108_GMAC_CLK_SEL_MASK = BIT(7),
+ RV1108_GMAC_CLK_SEL_2_5M = 0 << 7,
+ RV1108_GMAC_CLK_SEL_25M = 1 << 7,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RV1108_GMAC_CLK_SEL_2_5M;
+ speed = RV1108_GMAC_SPEED_10M;
+ break;
+ case 100:
+ clk = RV1108_GMAC_CLK_SEL_25M;
+ speed = RV1108_GMAC_SPEED_100M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->gmac_con0,
+     RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK,
+     clk | speed);
+
+ return 0;
+}
+
 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
  struct rk3288_grf *grf;
@@ -221,25 +266,76 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
      pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rv1108_grf *grf;
+
+ enum {
+ RV1108_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+ RV1108_GMAC_PHY_INTF_SEL_RMII  = 4 << 4,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->gmac_con0,
+     RV1108_GMAC_PHY_INTF_SEL_MASK,
+     RV1108_GMAC_PHY_INTF_SEL_RMII);
+}
+
 static int gmac_rockchip_probe(struct udevice *dev)
 {
  struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
  struct rk_gmac_ops *ops =
  (struct rk_gmac_ops *)dev_get_driver_data(dev);
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+ struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata;
  struct clk clk;
+ ulong rate;
  int ret;
 
  ret = clk_get_by_index(dev, 0, &clk);
  if (ret)
  return ret;
 
- /* Since mac_clk is fed by an external clock we can use 0 here */
- ret = clk_set_rate(&clk, 0);
- if (ret)
- return ret;
+ switch (eth_pdata->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+ * If the gmac clock is from internal pll, need to set and
+ * check the return value for gmac clock at RGMII mode. If
+ * the gmac clock is from external source, the clock rate
+ * is not set, because of it is bypassed.
+ */
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
+ return -EINVAL;
+ }
+
+ /* Set to RGMII mode */
+ if (ops->set_to_rgmii)
+ ops->set_to_rgmii(pdata);
+ else
+ return -EPERM;
 
- /* Set to RGMII mode */
- ops->set_to_rgmii(pdata);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ /* The commet is the same as RGMII mode */
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 50000000);
+ if (rate != 50000000)
+ return -EINVAL;
+ }
+
+ /* Set to RMII mode */
+ if (ops->set_to_rmii)
+ ops->set_to_rmii(pdata);
+ else
+ return -EPERM;
+
+ break;
+ default:
+ debug("NO interface defined!\n");
+ return -ENXIO;
+ }
 
  return designware_eth_probe(dev);
 }
@@ -289,6 +385,11 @@ const struct rk_gmac_ops rk3399_gmac_ops = {
  .set_to_rgmii = rk3399_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rv1108_gmac_ops = {
+ .fix_mac_speed = rv1108_set_rmii_speed,
+ .set_to_rmii = rv1108_gmac_set_to_rmii,
+};
+
 static const struct udevice_id rockchip_gmac_ids[] = {
  { .compatible = "rockchip,rk3288-gmac",
   .data = (ulong)&rk3288_gmac_ops },
@@ -296,6 +397,8 @@ static const struct udevice_id rockchip_gmac_ids[] = {
   .data = (ulong)&rk3368_gmac_ops },
  { .compatible = "rockchip,rk3399-gmac",
   .data = (ulong)&rk3399_gmac_ops },
+ { .compatible = "rockchip,rv1108-gmac",
+  .data = (ulong)&rv1108_gmac_ops },
  { }
 };
 
--
2.7.4


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[PATCH v3 06/20] rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver

David Wu
In reply to this post by David Wu
Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 ------------------------
 drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 113 ++++++++++++++++++++++++
 2 files changed, 113 insertions(+), 113 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index f0a0781..0c37f2a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,118 +131,5 @@ struct rk3328_sgrf_regs {
 };
 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
 
-enum {
- /* GPIO0A_IOMUX */
- GPIO0A5_SEL_SHIFT = 10,
- GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
- GPIO0A5_I2C3_SCL = 2,
-
- GPIO0A6_SEL_SHIFT = 12,
- GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
- GPIO0A6_I2C3_SDA = 2,
-
- GPIO0A7_SEL_SHIFT = 14,
- GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
- GPIO0A7_EMMC_DATA0 = 2,
-
- /* GPIO0D_IOMUX*/
- GPIO0D6_SEL_SHIFT = 12,
- GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDMMC0_PWRENM1 = 3,
-
- /* GPIO1A_IOMUX */
- GPIO1A0_SEL_SHIFT = 0,
- GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
-
- /* GPIO2A_IOMUX */
- GPIO2A0_SEL_SHIFT = 0,
- GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
- GPIO2A0_UART2_TX_M1 = 1,
-
- GPIO2A1_SEL_SHIFT = 2,
- GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
- GPIO2A1_UART2_RX_M1 = 1,
-
- GPIO2A2_SEL_SHIFT = 4,
- GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
- GPIO2A2_PWM_IR = 1,
-
- GPIO2A4_SEL_SHIFT = 8,
- GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
- GPIO2A4_PWM_0 = 1,
- GPIO2A4_I2C1_SDA,
-
- GPIO2A5_SEL_SHIFT = 10,
- GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
- GPIO2A5_PWM_1 = 1,
- GPIO2A5_I2C1_SCL,
-
- GPIO2A6_SEL_SHIFT = 12,
- GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
- GPIO2A6_PWM_2 = 1,
-
- GPIO2A7_SEL_SHIFT = 14,
- GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_PWRENM0,
-
- /* GPIO2BL_IOMUX */
- GPIO2BL0_SEL_SHIFT = 0,
- GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
- GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
-
- GPIO2BL3_SEL_SHIFT = 6,
- GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
- GPIO2BL3_SPI_CSN0_M0 = 1,
-
- GPIO2BL4_SEL_SHIFT = 8,
- GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
- GPIO2BL4_SPI_CSN1_M0 = 1,
-
- GPIO2BL5_SEL_SHIFT = 10,
- GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
- GPIO2BL5_I2C2_SDA = 1,
-
- GPIO2BL6_SEL_SHIFT = 12,
- GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
- GPIO2BL6_I2C2_SCL = 1,
-
- /* GPIO2D_IOMUX */
- GPIO2D0_SEL_SHIFT = 0,
- GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
- GPIO2D0_I2C0_SCL = 1,
-
- GPIO2D1_SEL_SHIFT = 2,
- GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
- GPIO2D1_I2C0_SDA = 1,
-
- GPIO2D4_SEL_SHIFT = 8,
- GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
- GPIO2D4_EMMC_DATA1234 = 0xaa,
-
- /* GPIO3C_IOMUX */
- GPIO3C0_SEL_SHIFT = 0,
- GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
- GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
-
- /* COM_IOMUX */
- IOMUX_SEL_UART2_SHIFT = 0,
- IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
- IOMUX_SEL_UART2_M0 = 0,
- IOMUX_SEL_UART2_M1,
-
- IOMUX_SEL_SPI_SHIFT = 4,
- IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
- IOMUX_SEL_SPI_M0 = 0,
- IOMUX_SEL_SPI_M1,
- IOMUX_SEL_SPI_M2,
-
- IOMUX_SEL_SDMMC_SHIFT = 7,
- IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
- IOMUX_SEL_SDMMC_M0 = 0,
- IOMUX_SEL_SDMMC_M1,
-};
 
 #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index c74163e..3c2253f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -17,6 +17,119 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+ /* GPIO0A_IOMUX */
+ GPIO0A5_SEL_SHIFT = 10,
+ GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
+ GPIO0A5_I2C3_SCL = 2,
+
+ GPIO0A6_SEL_SHIFT = 12,
+ GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
+ GPIO0A6_I2C3_SDA = 2,
+
+ GPIO0A7_SEL_SHIFT = 14,
+ GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
+ GPIO0A7_EMMC_DATA0 = 2,
+
+ GPIO0D6_SEL_SHIFT = 12,
+ GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_SDMMC0_PWRENM1 = 3,
+
+ /* GPIO1A_IOMUX */
+ GPIO1A0_SEL_SHIFT = 0,
+ GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
+ GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
+
+ /* GPIO2A_IOMUX */
+ GPIO2A0_SEL_SHIFT = 0,
+ GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
+ GPIO2A0_UART2_TX_M1 = 1,
+
+ GPIO2A1_SEL_SHIFT = 2,
+ GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
+ GPIO2A1_UART2_RX_M1 = 1,
+
+ GPIO2A2_SEL_SHIFT = 4,
+ GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
+ GPIO2A2_PWM_IR = 1,
+
+ GPIO2A4_SEL_SHIFT = 8,
+ GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
+ GPIO2A4_PWM_0 = 1,
+ GPIO2A4_I2C1_SDA,
+
+ GPIO2A5_SEL_SHIFT = 10,
+ GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
+ GPIO2A5_PWM_1 = 1,
+ GPIO2A5_I2C1_SCL,
+
+ GPIO2A6_SEL_SHIFT = 12,
+ GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
+ GPIO2A6_PWM_2 = 1,
+
+ GPIO2A7_SEL_SHIFT = 14,
+ GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_SDMMC0_PWRENM0,
+
+ /* GPIO2BL_IOMUX */
+ GPIO2BL0_SEL_SHIFT = 0,
+ GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
+ GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
+
+ GPIO2BL3_SEL_SHIFT = 6,
+ GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
+ GPIO2BL3_SPI_CSN0_M0 = 1,
+
+ GPIO2BL4_SEL_SHIFT = 8,
+ GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
+ GPIO2BL4_SPI_CSN1_M0 = 1,
+
+ GPIO2BL5_SEL_SHIFT = 10,
+ GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
+ GPIO2BL5_I2C2_SDA = 1,
+
+ GPIO2BL6_SEL_SHIFT = 12,
+ GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
+ GPIO2BL6_I2C2_SCL = 1,
+
+ /* GPIO2D_IOMUX */
+ GPIO2D0_SEL_SHIFT = 0,
+ GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
+ GPIO2D0_I2C0_SCL = 1,
+
+ GPIO2D1_SEL_SHIFT = 2,
+ GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
+ GPIO2D1_I2C0_SDA = 1,
+
+ GPIO2D4_SEL_SHIFT = 8,
+ GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
+ GPIO2D4_EMMC_DATA1234 = 0xaa,
+
+ /* GPIO3C_IOMUX */
+ GPIO3C0_SEL_SHIFT = 0,
+ GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
+ GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
+
+ /* COM_IOMUX */
+ IOMUX_SEL_UART2_SHIFT = 0,
+ IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
+ IOMUX_SEL_UART2_M0 = 0,
+ IOMUX_SEL_UART2_M1,
+
+ IOMUX_SEL_SPI_SHIFT = 4,
+ IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
+ IOMUX_SEL_SPI_M0 = 0,
+ IOMUX_SEL_SPI_M1,
+ IOMUX_SEL_SPI_M2,
+
+ IOMUX_SEL_SDMMC_SHIFT = 7,
+ IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
+ IOMUX_SEL_SDMMC_M0 = 0,
+ IOMUX_SEL_SDMMC_M1,
+};
+
 struct rk3328_pinctrl_priv {
  struct rk3328_grf_regs *grf;
 };
--
2.7.4


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[PATCH v3 07/20] rockchip: pinctrl: Add rk3328 gmac pinctrl support

David Wu
In reply to this post by David Wu
Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2
and bit10 at com iomux register. After that, set rgmii m1 tx
pins to 12ma drive-strength, and clean others to 2ma.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rk3328.h |   1 -
 drivers/pinctrl/rockchip/pinctrl_rk3328.c       | 275 ++++++++++++++++++++++++
 2 files changed, 275 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
index 0c37f2a..2776cef 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -131,5 +131,4 @@ struct rk3328_sgrf_regs {
 };
 check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
 
-
 #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
index 3c2253f..fa2356a 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
@@ -31,6 +31,37 @@ enum {
  GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
  GPIO0A7_EMMC_DATA0 = 2,
 
+ /* GPIO0B_IOMUX*/
+ GPIO0B0_SEL_SHIFT = 0,
+ GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT,
+ GPIO0B0_GAMC_CLKTXM0 = 1,
+
+ GPIO0B4_SEL_SHIFT = 8,
+ GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT,
+ GPIO0B4_GAMC_TXENM0 = 1,
+
+ /* GPIO0C_IOMUX*/
+ GPIO0C0_SEL_SHIFT = 0,
+ GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT,
+ GPIO0C0_GAMC_TXD1M0 = 1,
+
+ GPIO0C1_SEL_SHIFT = 2,
+ GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT,
+ GPIO0C1_GAMC_TXD0M0 = 1,
+
+ GPIO0C6_SEL_SHIFT = 12,
+ GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT,
+ GPIO0C6_GAMC_TXD2M0 = 1,
+
+ GPIO0C7_SEL_SHIFT = 14,
+ GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT,
+ GPIO0C7_GAMC_TXD3M0 = 1,
+
+ /* GPIO0D_IOMUX*/
+ GPIO0D0_SEL_SHIFT = 0,
+ GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT,
+ GPIO0D0_GMAC_CLKM0 = 1,
+
  GPIO0D6_SEL_SHIFT = 12,
  GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
  GPIO0D6_GPIO = 0,
@@ -41,6 +72,69 @@ enum {
  GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
  GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
 
+ /* GPIO1B_IOMUX */
+ GPIO1B0_SEL_SHIFT = 0,
+ GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT,
+ GPIO1B0_GMAC_TXD1M1 = 2,
+
+ GPIO1B1_SEL_SHIFT = 2,
+ GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT,
+ GPIO1B1_GMAC_TXD0M1 = 2,
+
+ GPIO1B2_SEL_SHIFT = 4,
+ GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT,
+ GPIO1B2_GMAC_RXD1M1 = 2,
+
+ GPIO1B3_SEL_SHIFT = 6,
+ GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT,
+ GPIO1B3_GMAC_RXD0M1 = 2,
+
+ GPIO1B4_SEL_SHIFT = 8,
+ GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT,
+ GPIO1B4_GMAC_TXCLKM1 = 2,
+
+ GPIO1B5_SEL_SHIFT = 10,
+ GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT,
+ GPIO1B5_GMAC_RXCLKM1 = 2,
+
+ GPIO1B6_SEL_SHIFT = 12,
+ GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT,
+ GPIO1B6_GMAC_RXD3M1 = 2,
+
+ GPIO1B7_SEL_SHIFT = 14,
+ GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT,
+ GPIO1B7_GMAC_RXD2M1 = 2,
+
+ /* GPIO1C_IOMUX */
+ GPIO1C0_SEL_SHIFT = 0,
+ GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT,
+ GPIO1C0_GMAC_TXD3M1 = 2,
+
+ GPIO1C1_SEL_SHIFT = 2,
+ GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT,
+ GPIO1C1_GMAC_TXD2M1 = 2,
+
+ GPIO1C3_SEL_SHIFT = 6,
+ GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT,
+ GPIO1C3_GMAC_MDIOM1 = 2,
+
+ GPIO1C5_SEL_SHIFT = 10,
+ GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT,
+ GPIO1C5_GMAC_CLKM1 = 2,
+
+ GPIO1C6_SEL_SHIFT = 12,
+ GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT,
+ GPIO1C6_GMAC_RXDVM1 = 2,
+
+ GPIO1C7_SEL_SHIFT = 14,
+ GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT,
+ GPIO1C7_GMAC_MDCM1 = 2,
+
+ /* GPIO1D_IOMUX */
+ GPIO1D1_SEL_SHIFT = 2,
+ GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT,
+ GPIO1D1_GMAC_TXENM1 = 2,
+
  /* GPIO2A_IOMUX */
  GPIO2A0_SEL_SHIFT = 0,
  GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
@@ -118,6 +212,11 @@ enum {
  IOMUX_SEL_UART2_M0 = 0,
  IOMUX_SEL_UART2_M1,
 
+ IOMUX_SEL_GMAC_SHIFT = 2,
+ IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT,
+ IOMUX_SEL_GMAC_M0 = 0,
+ IOMUX_SEL_GMAC_M1,
+
  IOMUX_SEL_SPI_SHIFT = 4,
  IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
  IOMUX_SEL_SPI_M0 = 0,
@@ -128,6 +227,55 @@ enum {
  IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
  IOMUX_SEL_SDMMC_M0 = 0,
  IOMUX_SEL_SDMMC_M1,
+
+ IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0,
+ IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
+
+ /* GRF_GPIO1B_E */
+ GRF_GPIO1B0_E_SHIFT = 0,
+ GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT,
+ GRF_GPIO1B1_E_SHIFT = 2,
+ GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT,
+ GRF_GPIO1B2_E_SHIFT = 4,
+ GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT,
+ GRF_GPIO1B3_E_SHIFT = 6,
+ GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT,
+ GRF_GPIO1B4_E_SHIFT = 8,
+ GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT,
+ GRF_GPIO1B5_E_SHIFT = 10,
+ GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT,
+ GRF_GPIO1B6_E_SHIFT = 12,
+ GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT,
+ GRF_GPIO1B7_E_SHIFT = 14,
+ GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT,
+
+ /*  GRF_GPIO1C_E */
+ GRF_GPIO1C0_E_SHIFT = 0,
+ GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT,
+ GRF_GPIO1C1_E_SHIFT = 2,
+ GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT,
+ GRF_GPIO1C3_E_SHIFT = 6,
+ GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT,
+ GRF_GPIO1C5_E_SHIFT = 10,
+ GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT,
+ GRF_GPIO1C6_E_SHIFT = 12,
+ GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT,
+ GRF_GPIO1C7_E_SHIFT = 14,
+ GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT,
+
+ /*  GRF_GPIO1D_E */
+ GRF_GPIO1D1_E_SHIFT = 2,
+ GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT,
+};
+
+/* GPIO Bias drive strength settings */
+enum GPIO_BIAS {
+ GPIO_BIAS_2MA = 0,
+ GPIO_BIAS_4MA,
+ GPIO_BIAS_8MA,
+ GPIO_BIAS_12MA,
 };
 
 struct rk3328_pinctrl_priv {
@@ -313,6 +461,124 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
  }
 }
 
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii m1 pins mux */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+     GPIO1B0_SEL_MASK |
+     GPIO1B1_SEL_MASK |
+     GPIO1B2_SEL_MASK |
+     GPIO1B3_SEL_MASK |
+     GPIO1B4_SEL_MASK |
+     GPIO1B5_SEL_MASK |
+     GPIO1B6_SEL_MASK |
+     GPIO1B7_SEL_MASK,
+     GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |
+     GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |
+     GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |
+     GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |
+     GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |
+     GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |
+     GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |
+     GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_iomux,
+     GPIO1C0_SEL_MASK |
+     GPIO1C1_SEL_MASK |
+     GPIO1C3_SEL_MASK |
+     GPIO1C5_SEL_MASK |
+     GPIO1C6_SEL_MASK |
+     GPIO1C7_SEL_MASK,
+     GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |
+     GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |
+     GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |
+     GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |
+     GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |
+     GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_iomux,
+     GPIO1D1_SEL_MASK,
+     GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);
+
+ /* set rgmii m0 tx pins mux */
+ rk_clrsetreg(&grf->gpio0b_iomux,
+     GPIO0B0_SEL_MASK |
+     GPIO0B4_SEL_MASK,
+     GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |
+     GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0c_iomux,
+     GPIO0C0_SEL_MASK |
+     GPIO0C1_SEL_MASK |
+     GPIO0C6_SEL_MASK |
+     GPIO0C7_SEL_MASK,
+     GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |
+     GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |
+     GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |
+     GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);
+
+ rk_clrsetreg(&grf->gpio0d_iomux,
+     GPIO0D0_SEL_MASK,
+     GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);
+
+ /* set com mux */
+ rk_clrsetreg(&grf->com_iomux,
+     IOMUX_SEL_GMAC_MASK |
+     IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,
+     IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |
+     IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<
+     IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);
+
+ /*
+ * set rgmii m1 tx pins to 12ma drive-strength,
+ * and clean others to 2ma.
+ */
+ rk_clrsetreg(&grf->gpio1b_e,
+     GRF_GPIO1B0_E_MASK |
+     GRF_GPIO1B1_E_MASK |
+     GRF_GPIO1B2_E_MASK |
+     GRF_GPIO1B3_E_MASK |
+     GRF_GPIO1B4_E_MASK |
+     GRF_GPIO1B5_E_MASK |
+     GRF_GPIO1B6_E_MASK |
+     GRF_GPIO1B7_E_MASK,
+     GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1c_e,
+     GRF_GPIO1C0_E_MASK |
+     GRF_GPIO1C1_E_MASK |
+     GRF_GPIO1C3_E_MASK |
+     GRF_GPIO1C5_E_MASK |
+     GRF_GPIO1C6_E_MASK |
+     GRF_GPIO1C7_E_MASK,
+     GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio1d_e,
+     GRF_GPIO1D1_E_MASK,
+     GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT);
+ break;
+ default:
+ debug("gmac id = %d iomux error!\n", gmac_id);
+ break;
+ }
+}
+#endif
+
 static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
 {
  struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
@@ -349,6 +615,11 @@ static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
  case PERIPH_ID_SDMMC1:
  pinctrl_rk3328_sdmmc_config(priv->grf, func);
  break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk3328_gmac_config(priv->grf, func);
+ break;
+#endif
  default:
  return -EINVAL;
  }
@@ -383,6 +654,10 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
  return PERIPH_ID_SDCARD;
  case 14:
  return PERIPH_ID_EMMC;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 24:
+ return PERIPH_ID_GMAC;
+#endif
  }
 
  return -ENOENT;
--
2.7.4


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[PATCH v3 08/20] clk: rockchip: Add rk3328 gamc clock support

David Wu
In reply to this post by David Wu
The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- Add "set parent" for gmac2io
- Add internal mac clk div_sel for gmac2io

Changes in v2:
- New patch

 drivers/clk/rockchip/clk_rk3328.c      | 178 +++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/rk3328-cru.h |   6 +-
 2 files changed, 181 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index fa0c777..2ccc798 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -13,6 +13,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3328.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3328.h>
 #include <asm/io.h>
 #include <dm/lists.h>
 #include <dt-bindings/clock/rk3328-cru.h>
@@ -94,6 +95,14 @@ enum {
  PCLK_DBG_DIV_SHIFT = 0,
  PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
 
+ /* CLKSEL_CON27 */
+ GMAC2IO_PLL_SEL_SHIFT = 7,
+ GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
+ GMAC2IO_PLL_SEL_CPLL = 0,
+ GMAC2IO_PLL_SEL_GPLL = 1,
+ GMAC2IO_CLK_DIV_MASK = 0x1f,
+ GMAC2IO_CLK_DIV_SHIFT = 0,
+
  /* CLKSEL_CON28 */
  ACLK_PERIHP_PLL_SEL_CPLL = 0,
  ACLK_PERIHP_PLL_SEL_GPLL,
@@ -393,6 +402,44 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
  return DIV_TO_RATE(GPLL_HZ, src_clk_div);
 }
 
+static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
+{
+ struct rk3328_grf_regs *grf;
+ ulong ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+ * The RGMII CLK can be derived either from an external "clkin"
+ * or can be generated from internally by a divider from SCLK_MAC.
+ */
+ if (readl(&grf->mac_con[1]) & BIT(10) &&
+    readl(&grf->soc_con[4]) & BIT(14)) {
+ /* An external clock will always generate the right rate... */
+ ret = rate;
+ } else {
+ u32 con = readl(&cru->clksel_con[27]);
+ ulong pll_rate;
+ u8 div;
+
+ if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
+ pll_rate = GPLL_HZ;
+ else
+ pll_rate = CPLL_HZ;
+
+ div = DIV_ROUND_UP(pll_rate, rate) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
+     div << GMAC2IO_CLK_DIV_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
+}
+
 static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
 {
  u32 div, con, con_id;
@@ -558,12 +605,48 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
  case SCLK_I2C3:
  ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
  break;
+ case SCLK_MAC2IO:
+ ret = rk3328_gmac2io_set_clk(priv->cru, rate);
+ break;
  case SCLK_PWM:
  ret = rk3328_pwm_set_clk(priv->cru, rate);
  break;
  case SCLK_SARADC:
  ret = rk3328_saradc_set_clk(priv->cru, rate);
  break;
+ case DCLK_LCDC:
+ case SCLK_PDM:
+ case SCLK_RTC32K:
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_SDIO:
+ case SCLK_TSP:
+ case SCLK_WIFI:
+ case ACLK_BUS_PRE:
+ case HCLK_BUS_PRE:
+ case PCLK_BUS_PRE:
+ case ACLK_PERI_PRE:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ case ACLK_VIO_PRE:
+ case HCLK_VIO_PRE:
+ case ACLK_RGA_PRE:
+ case SCLK_RGA:
+ case ACLK_VOP_PRE:
+ case ACLK_RKVDEC_PRE:
+ case ACLK_RKVENC:
+ case ACLK_VPU_PRE:
+ case SCLK_VDEC_CABAC:
+ case SCLK_VDEC_CORE:
+ case SCLK_VENC_CORE:
+ case SCLK_VENC_DSP:
+ case SCLK_EFUSE:
+ case PCLK_DDR:
+ case ACLK_GMAC:
+ case PCLK_GMAC:
+ case SCLK_USB3OTG_SUSPEND:
+ return 0;
  default:
  return -ENOENT;
  }
@@ -571,9 +654,104 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
  return ret;
 }
 
+static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3328_grf_regs *grf;
+ const char *clock_output_name;
+ int ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
+ debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
+ rk_clrreg(&grf->mac_con[1], BIT(10));
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "gmac_clkin".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+    parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "gmac_clkin", switch to the external clock input */
+ if (!strcmp(clock_output_name, "gmac_clkin")) {
+ debug("%s: switching RGMII to CLKIN\n", __func__);
+ rk_setreg(&grf->mac_con[1], BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3328_grf_regs *grf;
+ const char *clock_output_name;
+ int ret;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
+ debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
+ rk_clrreg(&grf->soc_con[4], BIT(14));
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "gmac_clkin".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+    parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "gmac_clkin", switch to the external clock input */
+ if (!strcmp(clock_output_name, "gmac_clkin")) {
+ debug("%s: switching RGMII to CLKIN\n", __func__);
+ rk_setreg(&grf->soc_con[4], BIT(14));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC2IO:
+ return rk3328_gmac2io_set_parent(clk, parent);
+ case SCLK_MAC2IO_EXT:
+ return rk3328_gmac2io_ext_set_parent(clk, parent);
+ case DCLK_LCDC:
+ case SCLK_PDM:
+ case SCLK_RTC32K:
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ return 0;
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
 static struct clk_ops rk3328_clk_ops = {
  .get_rate = rk3328_clk_get_rate,
  .set_rate = rk3328_clk_set_rate,
+ .set_parent = rk3328_clk_set_parent,
 };
 
 static int rk3328_clk_probe(struct udevice *dev)
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
index 6d8bf13..cdc0b33 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -86,6 +86,9 @@
 #define SCLK_USB3OTG_SUSPEND 97
 #define SCLK_REF_USB3OTG_SRC 98
 #define SCLK_MAC2IO_SRC 99
+#define SCLK_MAC2IO 100
+#define SCLK_MAC2PHY 101
+#define SCLK_MAC2IO_EXT 102
 
 /* dclk gates */
 #define DCLK_LCDC 180
@@ -199,9 +202,6 @@
 
 #define CLK_NR_CLKS (HCLK_HDCP + 1)
 
-#define SCLK_MAC2IO 0
-#define SCLK_MAC2PHY 1
-
 #define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
 
 /* soft-reset indices */
--
2.7.4


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[PATCH v3 09/20] net: gmac_rockchip: Add rk3328 gmac support

David Wu
In reply to this post by David Wu
The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3328-specific logic necessary to reuse this driver.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index cfffe29..551c230 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3328.h>
 #include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
 #include <asm/arch/grf_rv1108.h>
@@ -94,6 +95,39 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
  return 0;
 }
 
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk3328_grf_regs *grf;
+ int clk;
+ enum {
+ RK3328_GMAC_CLK_SEL_SHIFT = 11,
+ RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
+ RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
+ RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
+ RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3328_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3328_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3328_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
  struct rk3368_grf *grf;
@@ -207,6 +241,50 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
      pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3328_grf_regs *grf;
+ enum {
+ RK3328_RMII_MODE_SHIFT = 9,
+ RK3328_RMII_MODE_MASK  = BIT(9),
+
+ RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+ RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+     RK3328_RMII_MODE_MASK |
+     RK3328_GMAC_PHY_INTF_SEL_MASK |
+     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+     RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+     RK3328_GMAC_PHY_INTF_SEL_RGMII |
+     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+     RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(&grf->mac_con[0],
+     RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+     RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+     pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+     pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
  struct rk3368_grf *grf;
@@ -375,6 +453,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
  .set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rk3328_gmac_ops = {
+ .fix_mac_speed = rk3328_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3328_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3368_gmac_ops = {
  .fix_mac_speed = rk3368_gmac_fix_mac_speed,
  .set_to_rgmii = rk3368_gmac_set_to_rgmii,
@@ -393,6 +476,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
 static const struct udevice_id rockchip_gmac_ids[] = {
  { .compatible = "rockchip,rk3288-gmac",
   .data = (ulong)&rk3288_gmac_ops },
+ { .compatible = "rockchip,rk3328-gmac",
+  .data = (ulong)&rk3328_gmac_ops },
  { .compatible = "rockchip,rk3368-gmac",
   .data = (ulong)&rk3368_gmac_ops },
  { .compatible = "rockchip,rk3399-gmac",
--
2.7.4


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[PATCH v3 10/20] rockchip: configs: Enable GMAC configs for evb-rk3328

David Wu
In reply to this post by David Wu
Enable GMAC configs for evb-rk3328

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 configs/evb-rk3328_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index 3b8b104..3d8c04d 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -17,6 +17,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CLK=y
@@ -24,6 +25,10 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ROCKCHIP_RK3328=y
 CONFIG_DM_PMIC=y
--
2.7.4


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[PATCH v3 11/20] rockchip: dts: rk3328: Add gmac2io support

David Wu
In reply to this post by David Wu
Add basic dts configuration for rk3328 gmac2io.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/dts/rk3328.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 0bab1e3..5de1059 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -456,6 +456,25 @@
  status = "disabled";
  };
 
+ gmac2io: ethernet@ff540000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff540000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
+ <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
+ <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
+ <&cru PCLK_MAC2IO>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+      "mac_clk_tx", "clk_mac_ref",
+      "clk_mac_refout", "aclk_mac",
+      "pclk_mac";
+ resets = <&cru SRST_GMAC2IO_A>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+ };
+
  usb_host0_ehci: usb@ff5c0000 {
  compatible = "generic-ehci";
  reg = <0x0 0xff5c0000 0x0 0x10000>;
--
2.7.4


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[PATCH v3 12/20] rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb

David Wu
In reply to this post by David Wu
Add rk3328-evb gmac support.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 arch/arm/dts/rk3328-evb.dts | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 3dd9d81..336c2d5 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -15,6 +15,13 @@
  stdout-path = &uart2;
  };
 
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0>;
+ };
+
  vcc3v3_sdmmc: sdmmc-pwren {
  compatible = "regulator-fixed";
  regulator-name = "vcc3v3";
@@ -40,6 +47,13 @@
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
 };
 
 &saradc {
@@ -74,6 +88,22 @@
  status = "okay";
 };
 
+&gmac2io {
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 50000>;
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
+ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmiim1_pins>;
+ tx_delay = <0x26>;
+ rx_delay = <0x11>;
+ status = "okay";
+};
+
 &usb_host0_ehci {
  status = "okay";
 };
--
2.7.4


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[PATCH v3 13/20] rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver

David Wu
In reply to this post by David Wu
Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- Fix the wrong define for uart2 iomux

Changes in v2:
- New patch

 arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 455 ------------------------
 arch/arm/mach-rockchip/rk322x-board-spl.c       |  22 +-
 arch/arm/mach-rockchip/rk322x-board.c           |  18 +
 drivers/pinctrl/rockchip/pinctrl_rk322x.c       | 453 +++++++++++++++++++++++
 4 files changed, 492 insertions(+), 456 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
index c0c0d84..52e5a0a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -88,461 +88,6 @@ struct rk322x_sgrf {
  unsigned int busdmac_con[4];
 };
 
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A7_SHIFT = 14,
- GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
- GPIO0A7_GPIO = 0,
- GPIO0A7_I2C3_SDA,
- GPIO0A7_HDMI_DDCSDA,
-
- GPIO0A6_SHIFT = 12,
- GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
- GPIO0A6_GPIO = 0,
- GPIO0A6_I2C3_SCL,
- GPIO0A6_HDMI_DDCSCL,
-
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO = 0,
- GPIO0A3_I2C1_SDA,
- GPIO0A3_SDIO_CMD,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO = 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO = 0,
- GPIO0A1_I2C0_SDA,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO = 0,
- GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B7_SHIFT = 14,
- GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
- GPIO0B7_GPIO = 0,
- GPIO0B7_HDMI_HDP,
-
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO = 0,
- GPIO0B6_I2S_SDI,
- GPIO0B6_SPI_CSN0,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO = 0,
- GPIO0B5_I2S_SDO,
- GPIO0B5_SPI_RXD,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO = 0,
- GPIO0B3_I2S1_LRCKRX,
- GPIO0B3_SPI_TXD,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO = 0,
- GPIO0B1_I2S_SCLK,
- GPIO0B1_SPI_CLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK = 3,
- GPIO0B0_GPIO = 0,
- GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO = 0,
- GPIO0C4_HDMI_CECSDA,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO = 0,
- GPIO0C1_UART0_RSTN,
- GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDIO_PWREN,
- GPIO0D6_PWM11,
-
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
- GPIO0D4_GPIO = 0,
- GPIO0D4_PWM2,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
- GPIO0D3_GPIO = 0,
- GPIO0D3_PWM1,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
- GPIO0D2_GPIO = 0,
- GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A7_SHIFT = 14,
- GPIO1A7_MASK = 1,
- GPIO1A7_GPIO = 0,
- GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_SDMMC_CMD,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_SDMMC_PWREN,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_SPI_CSN1,
- GPIO1B4_PWM12,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_UART1_RSTN,
- GPIO1B3_PWM13,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART1_SIN,
- GPIO1B2_UART21_SIN,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART1_SOUT,
- GPIO1B1_UART21_SOUT,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_NAND_CS3,
- GPIO1C7_EMMC_RSTNOUT,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_NAND_CS2,
- GPIO1C6_EMMC_CMD,
-
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_SDMMC_D3,
- GPIO1C5_JTAG_TMS,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_SDMMC_D2,
- GPIO1C4_JTAG_TCK,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_SDMMC_D1,
- GPIO1C3_UART2_SIN,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
- GPIO1C2_GPIO = 0,
- GPIO1C2_SDMMC_D0,
- GPIO1C2_UART2_SOUT,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_SDMMC_DETN,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
- GPIO1C0_GPIO = 0,
- GPIO1C0_SDMMC_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_NAND_D7,
- GPIO1D7_EMMC_D7,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_NAND_D6,
- GPIO1D6_EMMC_D6,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_NAND_D5,
- GPIO1D5_EMMC_D5,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_NAND_D4,
- GPIO1D4_EMMC_D4,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_NAND_D3,
- GPIO1D3_EMMC_D3,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_NAND_D2,
- GPIO1D2_EMMC_D2,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_NAND_D1,
- GPIO1D1_EMMC_D1,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
- GPIO1D0_GPIO = 0,
- GPIO1D0_NAND_D0,
- GPIO1D0_EMMC_D0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_NAND_DQS,
- GPIO2A7_EMMC_CLKOUT,
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO = 0,
- GPIO2A5_NAND_WP,
- GPIO2A5_EMMC_PWREN,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_NAND_RDY,
- GPIO2A4_EMMC_CMD,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_NAND_RDN,
- GPIO2A4_SPI1_CSN1,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_NAND_WRN,
- GPIO2A4_SPI1_CSN0,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_NAND_CLE,
- GPIO2A1_SPI1_TXD,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_NAND_ALE,
- GPIO2A0_SPI1_RXD,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_GMAC_RXER,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_GMAC_CLK,
- GPIO2B6_MAC_LINK,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_GMAC_TXEN,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_GMAC_MDIO,
-
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO = 0,
- GPIO2B3_GMAC_RXCLK,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_GMAC_CRS,
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO = 0,
- GPIO2B1_GMAC_TXCLK,
-
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO = 0,
- GPIO2B0_GMAC_RXDV,
- GPIO2B0_MAC_SPEED_IOUT,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
- GPIO2C7_SHIFT = 14,
- GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
- GPIO2C7_GPIO = 0,
- GPIO2C7_GMAC_TXD3,
-
- GPIO2C6_SHIFT = 12,
- GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
- GPIO2C6_GPIO = 0,
- GPIO2C6_GMAC_TXD2,
-
- GPIO2C5_SHIFT = 10,
- GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
- GPIO2C5_GPIO = 0,
- GPIO2C5_I2C2_SCL,
- GPIO2C5_GMAC_RXD2,
-
- GPIO2C4_SHIFT = 8,
- GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
- GPIO2C4_GPIO = 0,
- GPIO2C4_I2C2_SDA,
- GPIO2C4_GMAC_RXD3,
-
- GPIO2C3_SHIFT = 6,
- GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
- GPIO2C3_GPIO = 0,
- GPIO2C3_GMAC_TXD0,
-
- GPIO2C2_SHIFT = 4,
- GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
- GPIO2C2_GPIO = 0,
- GPIO2C2_GMAC_TXD1,
-
- GPIO2C1_SHIFT = 2,
- GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
- GPIO2C1_GPIO = 0,
- GPIO2C1_GMAC_RXD0,
-
- GPIO2C0_SHIFT = 0,
- GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
- GPIO2C0_GPIO = 0,
- GPIO2C0_GMAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_GMAC_MDC,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_GMAC_COL,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_DRV_VBUS1,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_PWM10,
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
- GPIO3C1_GPIO = 0,
- GPIO3C1_DRV_VBUS,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
- GPIO3D2_SHIFT = 4,
- GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
- GPIO3D2_GPIO = 0,
- GPIO3D2_PWM3,
-};
-
-/* GRF_CON_IOMUX */
-enum {
- CON_IOMUX_GMAC_SHIFT = 15,
- CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
- CON_IOMUX_UART1SEL_SHIFT = 11,
- CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
- CON_IOMUX_UART2SEL_SHIFT = 8,
- CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
- CON_IOMUX_UART2SEL_2 = 0,
- CON_IOMUX_UART2SEL_21,
- CON_IOMUX_EMMCSEL_SHIFT = 7,
- CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
- CON_IOMUX_PWM3SEL_SHIFT = 3,
- CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
- CON_IOMUX_PWM2SEL_SHIFT = 2,
- CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
- CON_IOMUX_PWM1SEL_SHIFT = 1,
- CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
- CON_IOMUX_PWM0SEL_SHIFT = 0,
- CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
-};
-
 /* GRF_MACPHY_CON0 */
 enum {
  MACPHY_CFG_ENABLE_SHIFT = 0,
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
index 35f4f97..206abfa 100644
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -30,7 +30,27 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void board_debug_uart_init(void)
 {
-static struct rk322x_grf * const grf = (void *)GRF_BASE;
+ static struct rk322x_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO            = 0,
+ GPIO1B2_UART1_SIN,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO            = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+ };
+ enum {
+ CON_IOMUX_UART2SEL_SHIFT= 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ };
+
  /* Enable early UART2 channel 1 on the RK322x */
  rk_clrsetreg(&grf->gpio1b_iomux,
      GPIO1B1_MASK | GPIO1B2_MASK,
diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
index e71847d..8642a90 100644
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -34,6 +34,24 @@ int board_init(void)
  /* Enable early UART2 channel 1 on the RK322x */
 #define GRF_BASE 0x11000000
  struct rk322x_grf * const grf = (void *)GRF_BASE;
+ enum {
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO            = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+ };
+ enum {
+ CON_IOMUX_UART2SEL_SHIFT= 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ };
 
  rk_clrsetreg(&grf->gpio1b_iomux,
      GPIO1B1_MASK | GPIO1B2_MASK,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
index 576b037..28d9996 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -17,6 +17,459 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A7_SHIFT = 14,
+ GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
+ GPIO0A7_GPIO = 0,
+ GPIO0A7_I2C3_SDA,
+ GPIO0A7_HDMI_DDCSDA,
+
+ GPIO0A6_SHIFT = 12,
+ GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
+ GPIO0A6_GPIO = 0,
+ GPIO0A6_I2C3_SCL,
+ GPIO0A6_HDMI_DDCSCL,
+
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_I2C1_SDA,
+ GPIO0A3_SDIO_CMD,
+
+ GPIO0A2_SHIFT = 4,
+ GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
+ GPIO0A2_GPIO = 0,
+ GPIO0A2_I2C1_SCL,
+
+ GPIO0A1_SHIFT = 2,
+ GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
+ GPIO0A1_GPIO = 0,
+ GPIO0A1_I2C0_SDA,
+
+ GPIO0A0_SHIFT = 0,
+ GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
+ GPIO0A0_GPIO = 0,
+ GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B7_SHIFT = 14,
+ GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
+ GPIO0B7_GPIO = 0,
+ GPIO0B7_HDMI_HDP,
+
+ GPIO0B6_SHIFT = 12,
+ GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
+ GPIO0B6_GPIO = 0,
+ GPIO0B6_I2S_SDI,
+ GPIO0B6_SPI_CSN0,
+
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_I2S_SDO,
+ GPIO0B5_SPI_RXD,
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_I2S1_LRCKRX,
+ GPIO0B3_SPI_TXD,
+
+ GPIO0B1_SHIFT = 2,
+ GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
+ GPIO0B1_GPIO = 0,
+ GPIO0B1_I2S_SCLK,
+ GPIO0B1_SPI_CLK,
+
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = 3,
+ GPIO0B0_GPIO = 0,
+ GPIO0B0_I2S_MCLK,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_HDMI_CECSDA,
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_UART0_RSTN,
+ GPIO0C1_CLK_OUT1,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_SDIO_PWREN,
+ GPIO0D6_PWM11,
+
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_PWM2,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_PWM1,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A7_SHIFT = 14,
+ GPIO1A7_MASK = 1,
+ GPIO1A7_GPIO = 0,
+ GPIO1A7_SDMMC_WRPRT,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_SDMMC_CMD,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_SDMMC_PWREN,
+
+ GPIO1B4_SHIFT = 8,
+ GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
+ GPIO1B4_GPIO = 0,
+ GPIO1B4_SPI_CSN1,
+ GPIO1B4_PWM12,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_UART1_RSTN,
+ GPIO1B3_PWM13,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART1_SIN,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_SHIFT = 14,
+ GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_NAND_CS3,
+ GPIO1C7_EMMC_RSTNOUT,
+
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_NAND_CS2,
+ GPIO1C6_EMMC_CMD,
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_SDMMC_D3,
+ GPIO1C5_JTAG_TMS,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_SDMMC_D2,
+ GPIO1C4_JTAG_TCK,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_SDMMC_D1,
+ GPIO1C3_UART2_SIN,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_SDMMC_D0,
+ GPIO1C2_UART2_SOUT,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_SDMMC_DETN,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_SDMMC_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_NAND_D7,
+ GPIO1D7_EMMC_D7,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_NAND_D6,
+ GPIO1D6_EMMC_D6,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_NAND_D5,
+ GPIO1D5_EMMC_D5,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_NAND_D4,
+ GPIO1D4_EMMC_D4,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_NAND_D3,
+ GPIO1D3_EMMC_D3,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_NAND_D2,
+ GPIO1D2_EMMC_D2,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_NAND_D1,
+ GPIO1D1_EMMC_D1,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_NAND_D0,
+ GPIO1D0_EMMC_D0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_NAND_DQS,
+ GPIO2A7_EMMC_CLKOUT,
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_NAND_WP,
+ GPIO2A5_EMMC_PWREN,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_NAND_RDY,
+ GPIO2A4_EMMC_CMD,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_NAND_RDN,
+ GPIO2A4_SPI1_CSN1,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_NAND_WRN,
+ GPIO2A4_SPI1_CSN0,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_NAND_CLE,
+ GPIO2A1_SPI1_TXD,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_NAND_ALE,
+ GPIO2A0_SPI1_RXD,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_GMAC_RXER,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_GMAC_CLK,
+ GPIO2B6_MAC_LINK,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_GMAC_TXEN,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_GMAC_MDIO,
+
+ GPIO2B3_SHIFT = 6,
+ GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
+ GPIO2B3_GPIO = 0,
+ GPIO2B3_GMAC_RXCLK,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_GMAC_CRS,
+
+ GPIO2B1_SHIFT = 2,
+ GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
+ GPIO2B1_GPIO = 0,
+ GPIO2B1_GMAC_TXCLK,
+
+ GPIO2B0_SHIFT = 0,
+ GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
+ GPIO2B0_GPIO = 0,
+ GPIO2B0_GMAC_RXDV,
+ GPIO2B0_MAC_SPEED_IOUT,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C7_SHIFT = 14,
+ GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_GMAC_TXD3,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_GMAC_TXD2,
+
+ GPIO2C5_SHIFT = 10,
+ GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_I2C2_SCL,
+ GPIO2C5_GMAC_RXD2,
+
+ GPIO2C4_SHIFT = 8,
+ GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_I2C2_SDA,
+ GPIO2C4_GMAC_RXD3,
+
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_GMAC_TXD0,
+
+ GPIO2C2_SHIFT = 4,
+ GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
+ GPIO2C2_GPIO = 0,
+ GPIO2C2_GMAC_TXD1,
+
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_GMAC_RXD0,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_GMAC_MDC,
+
+ GPIO2D0_SHIFT = 0,
+ GPIO2D0_MASK = 3,
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_GMAC_COL,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_DRV_VBUS1,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_PWM10,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_DRV_VBUS,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+ GPIO3D2_SHIFT = 4,
+ GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_PWM3,
+};
+
+/* GRF_CON_IOMUX */
+enum {
+ CON_IOMUX_GMACSEL_SHIFT = 15,
+ CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
+ CON_IOMUX_GMACSEL_1 = 1,
+ CON_IOMUX_UART1SEL_SHIFT = 11,
+ CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
+ CON_IOMUX_UART2SEL_SHIFT = 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ CON_IOMUX_EMMCSEL_SHIFT = 7,
+ CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
+ CON_IOMUX_PWM3SEL_SHIFT = 3,
+ CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
+ CON_IOMUX_PWM2SEL_SHIFT = 2,
+ CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
+ CON_IOMUX_PWM1SEL_SHIFT = 1,
+ CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
+ CON_IOMUX_PWM0SEL_SHIFT = 0,
+ CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
+};
+
 struct rk322x_pinctrl_priv {
  struct rk322x_grf *grf;
 };
--
2.7.4


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[PATCH v3 14/20] rockchip: pinctrl: Add rk322x gmac pinctrl support

David Wu
In reply to this post by David Wu
Set gmac pins iomux and rgmii tx pins to 12ma drive-strength,
clean others to 2ma.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- adhere to the established way of writing this to avoid future confusion
- use defined symbolic constants for drive-strength

Changes in v2:
- New patch

 drivers/pinctrl/rockchip/pinctrl_rk322x.c | 148 ++++++++++++++++++++++++++++++
 1 file changed, 148 insertions(+)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
index 28d9996..354fea2 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -470,6 +470,56 @@ enum {
  CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
 };
 
+/* GRF_GPIO2B_E */
+enum {
+ GRF_GPIO2B0_E_SHIFT = 0,
+ GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
+ GRF_GPIO2B1_E_SHIFT = 2,
+ GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
+ GRF_GPIO2B3_E_SHIFT = 6,
+ GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
+ GRF_GPIO2B4_E_SHIFT = 8,
+ GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
+ GRF_GPIO2B5_E_SHIFT = 10,
+ GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
+ GRF_GPIO2B6_E_SHIFT = 12,
+ GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
+};
+
+/* GRF_GPIO2C_E */
+enum {
+ GRF_GPIO2C0_E_SHIFT = 0,
+ GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
+ GRF_GPIO2C1_E_SHIFT = 2,
+ GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
+ GRF_GPIO2C2_E_SHIFT = 4,
+ GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
+ GRF_GPIO2C3_E_SHIFT = 6,
+ GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
+ GRF_GPIO2C4_E_SHIFT = 8,
+ GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
+ GRF_GPIO2C5_E_SHIFT = 10,
+ GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
+ GRF_GPIO2C6_E_SHIFT = 12,
+ GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
+ GRF_GPIO2C7_E_SHIFT = 14,
+ GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
+};
+
+/* GRF_GPIO2D_E */
+enum {
+ GRF_GPIO2D1_E_SHIFT = 2,
+ GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
+};
+
+/* GPIO Bias drive strength settings */
+enum GPIO_BIAS {
+ GPIO_BIAS_2MA = 0,
+ GPIO_BIAS_4MA,
+ GPIO_BIAS_8MA,
+ GPIO_BIAS_12MA,
+};
+
 struct rk322x_pinctrl_priv {
  struct rk322x_grf *grf;
 };
@@ -633,6 +683,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
  }
 }
 
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
+{
+ switch (gmac_id) {
+ case PERIPH_ID_GMAC:
+ /* set rgmii pins mux */
+ rk_clrsetreg(&grf->gpio2b_iomux,
+     GPIO2B0_MASK |
+     GPIO2B1_MASK |
+     GPIO2B3_MASK |
+     GPIO2B4_MASK |
+     GPIO2B5_MASK |
+     GPIO2B6_MASK,
+     GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
+     GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
+     GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
+     GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
+     GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
+     GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2c_iomux,
+     GPIO2C0_MASK |
+     GPIO2C1_MASK |
+     GPIO2C2_MASK |
+     GPIO2C3_MASK |
+     GPIO2C4_MASK |
+     GPIO2C5_MASK |
+     GPIO2C6_MASK |
+     GPIO2C7_MASK,
+     GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
+     GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
+     GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
+     GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
+     GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
+     GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
+     GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
+     GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2d_iomux,
+     GPIO2D1_MASK,
+     GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
+
+ /*
+ * set rgmii tx pins to 12ma drive-strength,
+ * clean others with 2ma.
+ */
+ rk_clrsetreg(&grf->gpio2_e[1],
+     GRF_GPIO2B0_E_MASK |
+     GRF_GPIO2B1_E_MASK |
+     GRF_GPIO2B3_E_MASK |
+     GRF_GPIO2B4_E_MASK |
+     GRF_GPIO2B5_E_MASK |
+     GRF_GPIO2B6_E_MASK,
+     GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2_e[2],
+     GRF_GPIO2C0_E_MASK |
+     GRF_GPIO2C1_E_MASK |
+     GRF_GPIO2C2_E_MASK |
+     GRF_GPIO2C3_E_MASK |
+     GRF_GPIO2C4_E_MASK |
+     GRF_GPIO2C5_E_MASK |
+     GRF_GPIO2C6_E_MASK |
+     GRF_GPIO2C7_E_MASK,
+     GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT |
+     GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT |
+     GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT);
+
+ rk_clrsetreg(&grf->gpio2_e[3],
+     GRF_GPIO2D1_E_MASK,
+     GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT);
+ break;
+ default:
+ debug("gmac id = %d iomux error!\n", gmac_id);
+ break;
+ }
+}
+#endif
+
 static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
 {
  struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
@@ -662,6 +801,11 @@ static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
  case PERIPH_ID_SDMMC1:
  pinctrl_rk322x_sdmmc_config(priv->grf, func);
  break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case PERIPH_ID_GMAC:
+ pinctrl_rk322x_gmac_config(priv->grf, func);
+ break;
+#endif
  default:
  return -EINVAL;
  }
@@ -701,6 +845,10 @@ static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
  return PERIPH_ID_UART1;
  case 57:
  return PERIPH_ID_UART2;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+ case 24:
+ return PERIPH_ID_GMAC;
+#endif
  }
  return -ENOENT;
 }
--
2.7.4


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[PATCH v3 15/20] clk: rockchip: Add rk322x gamc clock support

David Wu
In reply to this post by David Wu
Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- Add "set parent" for gmac
- Add internal mac clk div_sel for gmac

Changes in v2:
- New patch

 drivers/clk/rockchip/clk_rk322x.c | 107 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index c8a2413..4e6d2f0 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -239,6 +239,41 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
  return DIV_TO_RATE(src_rate, div) / 2;
 }
 
+static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
+{
+ ulong ret;
+
+ /*
+ * The gmac clock can be derived either from an external clock
+ * or can be generated from internally by a divider from SCLK_MAC.
+ */
+ if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
+ /* An external clock will always generate the right rate... */
+ ret = freq;
+ } else {
+ u32 con = readl(&cru->cru_clksel_con[5]);
+ ulong pll_rate;
+ u8 div;
+
+ if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
+ pll_rate = GPLL_HZ;
+ else
+ /* CPLL is not set */
+ return -EPERM;
+
+ div = DIV_ROUND_UP(pll_rate, freq) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
+     div << CLK_MAC_DIV_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
+}
+
 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
   int periph, uint freq)
 {
@@ -352,6 +387,11 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
  case CLK_DDR:
  new_rate = rk322x_ddr_set_clk(priv->cru, rate);
  break;
+ case SCLK_MAC:
+ new_rate = rk322x_mac_set_clk(priv->cru, rate);
+ break;
+ case PLL_GPLL:
+ return 0;
  default:
  return -ENOENT;
  }
@@ -359,9 +399,76 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
  return new_rate;
 }
 
+static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk322x_cru *cru = priv->cru;
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
+ debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
+ return 0;
+ }
+
+ /*
+ * If the requested parent is in the same clock-controller and the id
+ * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
+ debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_output_name;
+ struct rk322x_cru *cru = priv->cru;
+ int ret;
+
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+    parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ if (!strcmp(clock_output_name, "ext_gmac")) {
+ debug("%s: switching gmac extclk to ext_gmac\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
+ return 0;
+ } else if (!strcmp(clock_output_name, "phy_50m_out")) {
+ debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC:
+ return rk322x_gmac_set_parent(clk, parent);
+ case SCLK_MAC_EXTCLK:
+ return rk322x_gmac_extclk_set_parent(clk, parent);
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
 static struct clk_ops rk322x_clk_ops = {
  .get_rate = rk322x_clk_get_rate,
  .set_rate = rk322x_clk_set_rate,
+ .set_parent = rk322x_clk_set_parent,
 };
 
 static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
--
2.7.4


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[PATCH v3 16/20] net: gmac_rockchip: Add support for the RK3228 GMAC

David Wu
In reply to this post by David Wu
The GMAC in the RK3228 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 551c230..683e820 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -15,6 +15,7 @@
 #include <asm/arch/periph.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk322x.h>
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/grf_rk3328.h>
 #include <asm/arch/grf_rk3368.h>
@@ -69,6 +70,39 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)
  return designware_eth_ofdata_to_platdata(dev);
 }
 
+static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+ struct rk322x_grf *grf;
+ int clk;
+ enum {
+ RK3228_GMAC_CLK_SEL_SHIFT = 8,
+ RK3228_GMAC_CLK_SEL_MASK  = GENMASK(9, 8),
+ RK3228_GMAC_CLK_SEL_125M  = 0 << 8,
+ RK3228_GMAC_CLK_SEL_25M   = 3 << 8,
+ RK3228_GMAC_CLK_SEL_2_5M  = 2 << 8,
+ };
+
+ switch (priv->phydev->speed) {
+ case 10:
+ clk = RK3228_GMAC_CLK_SEL_2_5M;
+ break;
+ case 100:
+ clk = RK3228_GMAC_CLK_SEL_25M;
+ break;
+ case 1000:
+ clk = RK3228_GMAC_CLK_SEL_125M;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phydev->speed);
+ return -EINVAL;
+ }
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk);
+
+ return 0;
+}
+
 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
  struct rk3288_grf *grf;
@@ -221,6 +255,50 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv)
  return 0;
 }
 
+static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk322x_grf *grf;
+ enum {
+ RK3228_RMII_MODE_SHIFT = 10,
+ RK3228_RMII_MODE_MASK  = BIT(10),
+
+ RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4,
+ RK3228_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+ RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+ RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+ RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+ RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+ RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+ };
+ enum {
+ RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+ RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+ RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+ RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ rk_clrsetreg(&grf->mac_con[1],
+     RK3228_RMII_MODE_MASK |
+     RK3228_GMAC_PHY_INTF_SEL_MASK |
+     RK3228_RXCLK_DLY_ENA_GMAC_MASK |
+     RK3228_TXCLK_DLY_ENA_GMAC_MASK,
+     RK3228_GMAC_PHY_INTF_SEL_RGMII |
+     RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
+     RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+ rk_clrsetreg(&grf->mac_con[0],
+     RK3228_CLK_RX_DL_CFG_GMAC_MASK |
+     RK3228_CLK_TX_DL_CFG_GMAC_MASK,
+     pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT |
+     pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
  struct rk3288_grf *grf;
@@ -448,6 +526,11 @@ const struct eth_ops gmac_rockchip_eth_ops = {
  .write_hwaddr = designware_eth_write_hwaddr,
 };
 
+const struct rk_gmac_ops rk3228_gmac_ops = {
+ .fix_mac_speed = rk3228_gmac_fix_mac_speed,
+ .set_to_rgmii = rk3228_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3288_gmac_ops = {
  .fix_mac_speed = rk3288_gmac_fix_mac_speed,
  .set_to_rgmii = rk3288_gmac_set_to_rgmii,
@@ -474,6 +557,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = {
 };
 
 static const struct udevice_id rockchip_gmac_ids[] = {
+ { .compatible = "rockchip,rk3228-gmac",
+  .data = (ulong)&rk3228_gmac_ops },
  { .compatible = "rockchip,rk3288-gmac",
   .data = (ulong)&rk3288_gmac_ops },
  { .compatible = "rockchip,rk3328-gmac",
--
2.7.4


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[PATCH v3 17/20] config: evb-rk3229: Enable rk gmac configs

David Wu
In reply to this post by David Wu
Add gmac config support for rk3229 evb.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- None

Changes in v2:
- New patch

 configs/evb-rk3229_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index b226f66..39469b4 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -21,6 +21,7 @@ CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
@@ -31,6 +32,10 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_ROCKCHIP_RK322X=y
 CONFIG_RAM=y
--
2.7.4


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[PATCH v3 18/20] ARM: dts: rk3288: Remove unused LCDC clock assigned

David Wu
In reply to this post by David Wu
The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
 0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- New patch

Changes in v2: None

 arch/arm/dts/rk3288.dtsi | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index da51878..2c8a616 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -604,19 +604,16 @@
  u-boot,dm-pre-reloc;
  #clock-cells = <1>;
  #reset-cells = <1>;
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
-  <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
   <&cru PCLK_PERI>;
- assigned-clock-rates = <0>, <0>,
-       <594000000>, <400000000>,
+ assigned-clock-rates = <594000000>, <400000000>,
        <500000000>, <300000000>,
        <150000000>, <75000000>,
        <300000000>, <150000000>,
        <75000000>;
- assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
  };
 
  grf: syscon@ff770000 {
--
2.7.4


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[PATCH v3 19/20] clk: rockchip: clk_rk3288: Implement "assign-clock-parent" and "assign-clock-rate"

David Wu
In reply to this post by David Wu
The RK3288 CRU-node assigns rates to a number of clocks that are not
implemented in the RK3288 clock-driver (but which have been
sufficiently initialised from rkclk_init()): for these clocks, we
implement the gmac clock set parent, but simply ignore the
others' set_rate() operation and return 0 to signal success.

Signed-off-by: David Wu <[hidden email]>
---

Changes in v3:
- New patch

Changes in v2: None

 drivers/clk/rockchip/clk_rk3288.c      | 106 ++++++++++++++++++++++++++++++---
 include/dt-bindings/clock/rk3288-cru.h |   1 +
 2 files changed, 99 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index b64c107..baa8122 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -295,15 +295,42 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
  return 0;
 }
 
-static int rockchip_mac_set_clk(struct rk3288_cru *cru,
-  int periph, uint freq)
+static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)
 {
- /* Assuming mac_clk is fed by an external clock */
- rk_clrsetreg(&cru->cru_clksel_con[21],
-     RMII_EXTCLK_MASK,
-     RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+ ulong ret;
 
- return 0;
+ /*
+ * The gmac clock can be derived either from an external clock
+ * or can be generated from internally by a divider from SCLK_MAC.
+ */
+ if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
+ /* An external clock will always generate the right rate... */
+ ret = freq;
+ } else {
+ u32 con = readl(&cru->cru_clksel_con[21]);
+ ulong pll_rate;
+ u8 div;
+
+ if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+    EMAC_PLL_SELECT_GENERAL)
+ pll_rate = GPLL_HZ;
+ else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
+ EMAC_PLL_SELECT_CODEC)
+ pll_rate = CPLL_HZ;
+ else
+ pll_rate = NPLL_HZ;
+
+ div = DIV_ROUND_UP(pll_rate, freq) - 1;
+ if (div <= 0x1f)
+ rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
+     div << MAC_DIV_CON_SHIFT);
+ else
+ debug("Unsupported div for gmac:%d\n", div);
+
+ return DIV_TO_RATE(pll_rate, div);
+ }
+
+ return ret;
 }
 
 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
@@ -744,7 +771,7 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
  break;
 #ifndef CONFIG_SPL_BUILD
  case SCLK_MAC:
- new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
+ new_rate = rockchip_mac_set_clk(priv->cru, rate);
  break;
  case DCLK_VOP0:
  case DCLK_VOP1:
@@ -797,6 +824,17 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
  case SCLK_SARADC:
  new_rate = rockchip_saradc_set_clk(priv->cru, rate);
  break;
+ case PLL_GPLL:
+ case PLL_CPLL:
+ case PLL_NPLL:
+ case ACLK_CPU:
+ case HCLK_CPU:
+ case PCLK_CPU:
+ case ACLK_PERI:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ case SCLK_UART0:
+ return 0;
  default:
  return -ENOENT;
  }
@@ -804,9 +842,61 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
  return new_rate;
 }
 
+static int rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3288_cru *cru = priv->cru;
+ const char *clock_output_name;
+ int ret;
+
+ /*
+ * If the requested parent is in the same clock-controller and
+ * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
+ * clock.
+ */
+ if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
+ debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
+ return 0;
+ }
+
+ /*
+ * Otherwise, we need to check the clock-output-names of the
+ * requested parent to see if the requested id is "ext_gmac".
+ */
+ ret = dev_read_string_index(parent->dev, "clock-output-names",
+    parent->id, &clock_output_name);
+ if (ret < 0)
+ return -ENODATA;
+
+ /* If this is "ext_gmac", switch to the external clock input */
+ if (!strcmp(clock_output_name, "ext_gmac")) {
+ debug("%s: switching GMAC to external clock\n", __func__);
+ rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
+     RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case SCLK_MAC:
+ return rk3288_gmac_set_parent(clk, parent);
+ case SCLK_USBPHY480M_SRC:
+ return 0;
+ }
+
+ debug("%s: unsupported clk %ld\n", __func__, clk->id);
+ return -ENOENT;
+}
+
 static struct clk_ops rk3288_clk_ops = {
  .get_rate = rk3288_clk_get_rate,
  .set_rate = rk3288_clk_set_rate,
+ .set_parent = rk3288_clk_set_parent,
 };
 
 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index 216eee5..e37113a 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -76,6 +76,7 @@
 #define SCLK_PVTM_CORE 123
 #define SCLK_PVTM_GPU 124
 
+#define SCLK_MAC_PLL 150
 #define SCLK_MAC 151
 #define SCLK_MACREF_OUT 152
 
--
2.7.4


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