[PATCH] spi: zynq_qspi: Use clk subsystem to get reference qspi clk

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[PATCH] spi: zynq_qspi: Use clk subsystem to get reference qspi clk

Michal Simek-3
From: T Karthik Reddy <[hidden email]>

Remove fixed reference clk used by plat->frequency and use clk
subsystem to get reference clk. As per spi dt bindings
"spi-max-frequency" property should be used by the slave devices.
This property is read by spi-uclass driver for the slave device.
So avoid reading above property from the platform driver.

Signed-off-by: T Karthik Reddy <[hidden email]>
Signed-off-by: Michal Simek <[hidden email]>
---

 drivers/spi/zynq_qspi.c | 35 +++++++++++++++++++++++++++--------
 1 file changed, 27 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 3f39ef05f2d6..7591164ea986 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -6,6 +6,7 @@
  * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
  */
 
+#include <clk.h>
 #include <common.h>
 #include <dm.h>
 #include <log.h>
@@ -105,14 +106,6 @@ static int zynq_qspi_ofdata_to_platdata(struct udevice *bus)
  plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
       node, "reg");
 
- /* FIXME: Use 166MHz as a suitable default */
- plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
- 166666666);
- plat->speed_hz = plat->frequency / 2;
-
- debug("%s: regs=%p max-frequency=%d\n", __func__,
-      plat->regs, plat->frequency);
-
  return 0;
 }
 
@@ -159,13 +152,39 @@ static int zynq_qspi_probe(struct udevice *bus)
 {
  struct zynq_qspi_platdata *plat = dev_get_platdata(bus);
  struct zynq_qspi_priv *priv = dev_get_priv(bus);
+ struct clk clk;
+ unsigned long clock;
+ int ret;
 
  priv->regs = plat->regs;
  priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
 
+ ret = clk_get_by_name(bus, "ref_clk", &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clock\n");
+ return ret;
+ }
+
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ dev_err(dev, "failed to get rate\n");
+ return clock;
+ }
+
+ ret = clk_enable(&clk);
+ if (ret && ret != -ENOSYS) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
  /* init the zynq spi hw */
  zynq_qspi_init_hw(priv);
 
+ plat->frequency = clock;
+ plat->speed_hz = plat->frequency / 2;
+
+ debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
+
  return 0;
 }
 
--
2.28.0