[PATCH 2/3] nds32: Support AG101P timer DM.

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[PATCH 2/3] nds32: Support AG101P timer DM.

Andes
From: rick <[hidden email]>

Support AG101P timer device tree flow.

Signed-off-by: rick <[hidden email]>
---
 arch/nds32/cpu/n1213/ag101/timer.c |    3 +-
 arch/nds32/dts/ag101p.dts          |    8 +++
 configs/adp-ag101p_defconfig       |    2 +
 drivers/timer/Kconfig              |    6 ++
 drivers/timer/Makefile             |    1 +
 drivers/timer/ag101p_timer.c       |  122 ++++++++++++++++++++++++++++++++++++
 6 files changed, 141 insertions(+), 1 deletion(-)
 create mode 100644 drivers/timer/ag101p_timer.c

diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c
index 758b354..0c03a10 100644
--- a/arch/nds32/cpu/n1213/ag101/timer.c
+++ b/arch/nds32/cpu/n1213/ag101/timer.c
@@ -8,7 +8,7 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
+#ifndef CONFIG_TIMER
 #include <common.h>
 #include <asm/io.h>
 #include <faraday/fttmr010.h>
@@ -189,3 +189,4 @@ ulong get_tbclk(void)
  return CONFIG_SYS_CLK_FREQ;
 #endif
 }
+#endif /* CONFIG_TIMER */
diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts
index 2baa3dc..91314b5 100644
--- a/arch/nds32/dts/ag101p.dts
+++ b/arch/nds32/dts/ag101p.dts
@@ -13,6 +13,7 @@
  /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
  bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
  stdout-path = "uart0:38400n8";
+ tick-timer = &timer0;
  };
 
  memory@0 {
@@ -46,4 +47,11 @@
  no-loopback-test = <1>;
  };
 
+ timer0: timer@98400000 {
+ compatible = "andestech,attmr010";
+ reg = <0x98400000 0x1000>;
+ interrupts = <19 4>;
+ clock-frequency = <15000000>;
+ };
+
 };
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 2a7302f..685a961 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -18,3 +18,5 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_AG101P_TIMER=y
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index e038523..356fa29 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -74,4 +74,10 @@ config ARC_TIMER
   usually at least one of them exists. Either of them is supported
   in U-Boot.
 
+config AG101P_TIMER
+ bool "Ag101p timer support"
+ depends on TIMER
+ help
+  Select this to enable a timer for Ag101p devices.
+
 endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index bfe65fc..3dad956 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
 obj-$(CONFIG_AST_TIMER) += ast_timer.o
 obj-$(CONFIG_STI_TIMER) += sti-timer.o
 obj-$(CONFIG_ARC_TIMER) += arc_timer.o
+obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
diff --git a/drivers/timer/ag101p_timer.c b/drivers/timer/ag101p_timer.c
new file mode 100644
index 0000000..163402f
--- /dev/null
+++ b/drivers/timer/ag101p_timer.c
@@ -0,0 +1,122 @@
+/*
+ * Andestech ATFTMR010 timer driver
+ *
+ * (C) Copyright 2016
+ * Rick Chen, NDS32 Software Engineering, [hidden email]
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <timer.h>
+#include <linux/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Timer Control Register
+ */
+#define T3_UPDOWN (1 << 11)
+#define T2_UPDOWN (1 << 10)
+#define T1_UPDOWN (1 << 9)
+#define T3_OFENABLE (1 << 8)
+#define T3_CLOCK (1 << 7)
+#define T3_ENABLE (1 << 6)
+#define T2_OFENABLE (1 << 5)
+#define T2_CLOCK (1 << 4)
+#define T2_ENABLE (1 << 3)
+#define T1_OFENABLE (1 << 2)
+#define T1_CLOCK (1 << 1)
+#define T1_ENABLE (1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define T3_OVERFLOW (1 << 8)
+#define T3_MATCH2 (1 << 7)
+#define T3_MATCH1 (1 << 6)
+#define T2_OVERFLOW (1 << 5)
+#define T2_MATCH2 (1 << 4)
+#define T2_MATCH1 (1 << 3)
+#define T1_OVERFLOW (1 << 2)
+#define T1_MATCH2 (1 << 1)
+#define T1_MATCH1 (1 << 0)
+
+struct atftmr_timer_regs {
+ u32 t1_counter; /* 0x00 */
+ u32 t1_load; /* 0x04 */
+ u32 t1_match1; /* 0x08 */
+ u32 t1_match2; /* 0x0c */
+ u32 t2_counter; /* 0x10 */
+ u32 t2_load; /* 0x14 */
+ u32 t2_match1; /* 0x18 */
+ u32 t2_match2; /* 0x1c */
+ u32 t3_counter; /* 0x20 */
+ u32 t3_load; /* 0x24 */
+ u32 t3_match1; /* 0x28 */
+ u32 t3_match2; /* 0x2c */
+ u32 cr; /* 0x30 */
+ u32 int_state; /* 0x34 */
+ u32 int_mask; /* 0x38 */
+};
+
+struct atftmr_timer_platdata {
+ struct atftmr_timer_regs *regs;
+};
+
+static int atftmr_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atftmr_timer_regs *const regs = plat->regs;
+ u32 val;
+ val = readl(&regs->t3_counter);
+ *count = timer_conv_64(val);
+ return 0;
+}
+
+static int atftmr_timer_probe(struct udevice *dev)
+{
+ struct atftmr_timer_platdata *plat = dev->platdata;
+ struct atftmr_timer_regs *const regs = plat->regs;
+ u32 cr;
+ writel(0, &regs->t3_load);
+ writel(0, &regs->t3_counter);
+ writel(TIMER_LOAD_VAL, &regs->t3_match1);
+ writel(TIMER_LOAD_VAL, &regs->t3_match2);
+ /* disable interrupts */
+ writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , &regs->int_mask);
+ cr = readl(&regs->cr);
+ cr |= (T3_ENABLE|T3_UPDOWN);
+ writel(cr, &regs->cr);
+ return 0;
+}
+
+static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
+ plat->regs = map_physmem(dev_get_addr(dev),
+ sizeof(struct atftmr_timer_regs),
+ MAP_NOCACHE);
+ return 0;
+}
+
+static const struct timer_ops ag101p_timer_ops = {
+ .get_count = atftmr_timer_get_count,
+};
+
+static const struct udevice_id ag101p_timer_ids[] = {
+ { .compatible = "andestech,attmr010" },
+ {}
+};
+
+U_BOOT_DRIVER(altera_timer) = {
+ .name = "ag101p_timer",
+ .id = UCLASS_TIMER,
+ .of_match = ag101p_timer_ids,
+ .ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
+ .probe = atftmr_timer_probe,
+ .ops = &ag101p_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
1.7.9.5

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