[PATCH 1/4] mmc: octeontx_hsmmc.c: Remove test debug message

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[PATCH 1/4] mmc: octeontx_hsmmc.c: Remove test debug message

Stefan Roese
Remove a left-over debug test message from the Octeon TX / TX2
MMC driver.

Signed-off-by: Stefan Roese <[hidden email]>
Cc: Aaron Williams <[hidden email]>
Cc: Suneel Garapati <[hidden email]>
Cc: Chandrakala Chavva <[hidden email]>
---
 drivers/mmc/octeontx_hsmmc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c
index ddc36694e1..38ca373684 100644
--- a/drivers/mmc/octeontx_hsmmc.c
+++ b/drivers/mmc/octeontx_hsmmc.c
@@ -3638,7 +3638,6 @@ static int octeontx_mmc_slot_probe(struct udevice *dev)
  struct mmc *mmc;
  int err;
 
- printk("%s (%d)\n", __func__, __LINE__); // test-only
  debug("%s(%s)\n", __func__, dev->name);
  if (!host_probed) {
  pr_err("%s(%s): Error: host not probed yet\n",
--
2.28.0

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[PATCH 2/4] arm: octeontx: Select CLK

Stefan Roese
Clock support is needed for all Octeon TX/TX2 boards. This patch selects
CONFIG_CLK so that it is available.

Signed-off-by: Stefan Roese <[hidden email]>
Cc: Aaron Williams <[hidden email]>
Cc: Suneel Garapati <[hidden email]>
Cc: Chandrakala Chavva <[hidden email]>
---
 arch/arm/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80702c23d3..c8362b8a56 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1739,6 +1739,7 @@ config ARCH_ROCKCHIP
 
 config ARCH_OCTEONTX
  bool "Support OcteonTX SoCs"
+ select CLK
  select DM
  select ARM64
  select OF_CONTROL
@@ -1748,6 +1749,7 @@ config ARCH_OCTEONTX
 
 config ARCH_OCTEONTX2
  bool "Support OcteonTX2 SoCs"
+ select CLK
  select DM
  select ARM64
  select OF_CONTROL
--
2.28.0

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[PATCH 3/4] watchdog: octeontx_wdt: Add support for start and stop

Stefan Roese
In reply to this post by Stefan Roese
From: Suneel Garapati <[hidden email]>

This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
the WDT. With this changes, the "wdt" command is now also supported
on these platforms.

Signed-off-by: Suneel Garapati <[hidden email]>
Signed-off-by: Stefan Roese <[hidden email]>
Cc: Aaron Williams <[hidden email]>
Cc: Suneel Garapati <[hidden email]>
Cc: Chandrakala Chavva <[hidden email]>
---
 drivers/watchdog/octeontx_wdt.c | 88 +++++++++++++++++++++++++++++++--
 1 file changed, 83 insertions(+), 5 deletions(-)

diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
index 1e0670e0c5..88708dc5e1 100644
--- a/drivers/watchdog/octeontx_wdt.c
+++ b/drivers/watchdog/octeontx_wdt.c
@@ -5,25 +5,90 @@
  * https://spdx.org/licenses
  */
 
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <wdt.h>
 #include <asm/io.h>
+#include <linux/bitfield.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CORE0_WDOG_OFFSET 0x40000
 #define CORE0_POKE_OFFSET 0x50000
 #define CORE0_POKE_OFFSET_MASK 0xfffffULL
 
+#define WDOG_MODE GENMASK_ULL(1, 0)
+#define WDOG_LEN GENMASK_ULL(19, 4)
+#define WDOG_CNT GENMASK_ULL(43, 20)
+
 struct octeontx_wdt {
  void __iomem *reg;
+ struct clk clk;
 };
 
+static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct octeontx_wdt *priv = dev_get_priv(dev);
+ u64 clk_rate, val;
+ u64 tout_wdog;
+
+ clk_rate = clk_get_rate(&priv->clk);
+ if (IS_ERR_VALUE(clk_rate))
+ return -EINVAL;
+
+ /* Watchdog counts in 1024 cycle steps */
+ tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
+
+ /*
+ * We can only specify the upper 16 bits of a 24 bit value.
+ * Round up
+ */
+ tout_wdog = (tout_wdog + 0xff) >> 8;
+
+ /* If the timeout overflows the hardware limit, set max */
+ if (tout_wdog >= 0x10000)
+ tout_wdog = 0xffff;
+
+ val = FIELD_PREP(WDOG_MODE, 0x3) |
+ FIELD_PREP(WDOG_LEN, tout_wdog) |
+ FIELD_PREP(WDOG_CNT, tout_wdog << 8);
+ writeq(val, priv->reg + CORE0_WDOG_OFFSET);
+
+ return 0;
+}
+
+static int octeontx_wdt_stop(struct udevice *dev)
+{
+ struct octeontx_wdt *priv = dev_get_priv(dev);
+
+ writeq(0, priv->reg + CORE0_WDOG_OFFSET);
+
+ return 0;
+}
+
+static int octeontx_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ octeontx_wdt_stop(dev);
+
+ /* Start with 100ms timeout to expire immediately */
+ octeontx_wdt_start(dev, 100, flags);
+
+ return 0;
+}
+
 static int octeontx_wdt_reset(struct udevice *dev)
 {
  struct octeontx_wdt *priv = dev_get_priv(dev);
 
- writeq(~0ULL, priv->reg);
+ writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
+
+ return 0;
+}
+
+static int octeontx_wdt_remove(struct udevice *dev)
+{
+ octeontx_wdt_stop(dev);
 
  return 0;
 }
@@ -31,24 +96,35 @@ static int octeontx_wdt_reset(struct udevice *dev)
 static int octeontx_wdt_probe(struct udevice *dev)
 {
  struct octeontx_wdt *priv = dev_get_priv(dev);
+ int ret;
 
  priv->reg = dev_remap_addr(dev);
  if (!priv->reg)
  return -EINVAL;
 
  /*
- * Save core poke register address in reg (its not 0xa0000 as
- * extracted from the DT but 0x50000 instead)
+ * Save base register address in reg masking lower 20 bits
+ * as 0xa0000 appears when extracted from the DT
  */
  priv->reg = (void __iomem *)(((u64)priv->reg &
-      ~CORE0_POKE_OFFSET_MASK) |
-     CORE0_POKE_OFFSET);
+      ~CORE0_POKE_OFFSET_MASK));
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret)
+ return ret;
 
  return 0;
 }
 
 static const struct wdt_ops octeontx_wdt_ops = {
  .reset = octeontx_wdt_reset,
+ .start = octeontx_wdt_start,
+ .stop = octeontx_wdt_stop,
+ .expire_now = octeontx_wdt_expire_now,
 };
 
 static const struct udevice_id octeontx_wdt_ids[] = {
@@ -63,4 +139,6 @@ U_BOOT_DRIVER(wdt_octeontx) = {
  .ops = &octeontx_wdt_ops,
  .priv_auto_alloc_size = sizeof(struct octeontx_wdt),
  .probe = octeontx_wdt_probe,
+ .remove = octeontx_wdt_remove,
+ .flags = DM_FLAG_OS_PREPARE,
 };
--
2.28.0

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[PATCH 4/4] arm: octeontx: Add CMD_WDT

Stefan Roese
In reply to this post by Stefan Roese
Enable WDT command for Octeon TX/TX2 boards.

Signed-off-by: Stefan Roese <[hidden email]>
Cc: Aaron Williams <[hidden email]>
Cc: Suneel Garapati <[hidden email]>
Cc: Chandrakala Chavva <[hidden email]>
---
 configs/octeontx2_95xx_defconfig | 1 +
 configs/octeontx2_96xx_defconfig | 1 +
 configs/octeontx_81xx_defconfig  | 1 +
 configs/octeontx_83xx_defconfig  | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index 047cb45a21..a17e5521d9 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -41,6 +41,7 @@ CONFIG_CMD_BKOPS_ENABLE=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index 7b5a1243a7..2e6cef0684 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -42,6 +42,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index ca3286b901..ff24e6e1e8 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -43,6 +43,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index e7dd3f6b73..ab38d007ea 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -41,6 +41,7 @@ CONFIG_CMD_PART=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_TFTPSRV=y
--
2.28.0

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Re: [PATCH 1/4] mmc: octeontx_hsmmc.c: Remove test debug message

Stefan Roese
In reply to this post by Stefan Roese
On 23.09.20 11:01, Stefan Roese wrote:
> Remove a left-over debug test message from the Octeon TX / TX2
> MMC driver.
>
> Signed-off-by: Stefan Roese <[hidden email]>
> Cc: Aaron Williams <[hidden email]>
> Cc: Suneel Garapati <[hidden email]>
> Cc: Chandrakala Chavva <[hidden email]>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
>   drivers/mmc/octeontx_hsmmc.c | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/drivers/mmc/octeontx_hsmmc.c b/drivers/mmc/octeontx_hsmmc.c
> index ddc36694e1..38ca373684 100644
> --- a/drivers/mmc/octeontx_hsmmc.c
> +++ b/drivers/mmc/octeontx_hsmmc.c
> @@ -3638,7 +3638,6 @@ static int octeontx_mmc_slot_probe(struct udevice *dev)
>   struct mmc *mmc;
>   int err;
>  
> - printk("%s (%d)\n", __func__, __LINE__); // test-only
>   debug("%s(%s)\n", __func__, dev->name);
>   if (!host_probed) {
>   pr_err("%s(%s): Error: host not probed yet\n",
>


Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: [hidden email]
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Re: [PATCH 2/4] arm: octeontx: Select CLK

Stefan Roese
In reply to this post by Stefan Roese
On 23.09.20 11:01, Stefan Roese wrote:
> Clock support is needed for all Octeon TX/TX2 boards. This patch selects
> CONFIG_CLK so that it is available.
>
> Signed-off-by: Stefan Roese <[hidden email]>
> Cc: Aaron Williams <[hidden email]>
> Cc: Suneel Garapati <[hidden email]>
> Cc: Chandrakala Chavva <[hidden email]>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
>   arch/arm/Kconfig | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 80702c23d3..c8362b8a56 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1739,6 +1739,7 @@ config ARCH_ROCKCHIP
>  
>   config ARCH_OCTEONTX
>   bool "Support OcteonTX SoCs"
> + select CLK
>   select DM
>   select ARM64
>   select OF_CONTROL
> @@ -1748,6 +1749,7 @@ config ARCH_OCTEONTX
>  
>   config ARCH_OCTEONTX2
>   bool "Support OcteonTX2 SoCs"
> + select CLK
>   select DM
>   select ARM64
>   select OF_CONTROL
>


Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: [hidden email]
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Re: [PATCH 3/4] watchdog: octeontx_wdt: Add support for start and stop

Stefan Roese
In reply to this post by Stefan Roese
On 23.09.20 11:01, Stefan Roese wrote:

> From: Suneel Garapati <[hidden email]>
>
> This patch enhances the Octeon TX/TX2 watchdog driver to fully enable
> the WDT. With this changes, the "wdt" command is now also supported
> on these platforms.
>
> Signed-off-by: Suneel Garapati <[hidden email]>
> Signed-off-by: Stefan Roese <[hidden email]>
> Cc: Aaron Williams <[hidden email]>
> Cc: Suneel Garapati <[hidden email]>
> Cc: Chandrakala Chavva <[hidden email]>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
>   drivers/watchdog/octeontx_wdt.c | 88 +++++++++++++++++++++++++++++++--
>   1 file changed, 83 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/watchdog/octeontx_wdt.c b/drivers/watchdog/octeontx_wdt.c
> index 1e0670e0c5..88708dc5e1 100644
> --- a/drivers/watchdog/octeontx_wdt.c
> +++ b/drivers/watchdog/octeontx_wdt.c
> @@ -5,25 +5,90 @@
>    * https://spdx.org/licenses
>    */
>  
> +#include <clk.h>
>   #include <dm.h>
>   #include <errno.h>
>   #include <wdt.h>
>   #include <asm/io.h>
> +#include <linux/bitfield.h>
>  
>   DECLARE_GLOBAL_DATA_PTR;
>  
> +#define CORE0_WDOG_OFFSET 0x40000
>   #define CORE0_POKE_OFFSET 0x50000
>   #define CORE0_POKE_OFFSET_MASK 0xfffffULL
>  
> +#define WDOG_MODE GENMASK_ULL(1, 0)
> +#define WDOG_LEN GENMASK_ULL(19, 4)
> +#define WDOG_CNT GENMASK_ULL(43, 20)
> +
>   struct octeontx_wdt {
>   void __iomem *reg;
> + struct clk clk;
>   };
>  
> +static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
> +{
> + struct octeontx_wdt *priv = dev_get_priv(dev);
> + u64 clk_rate, val;
> + u64 tout_wdog;
> +
> + clk_rate = clk_get_rate(&priv->clk);
> + if (IS_ERR_VALUE(clk_rate))
> + return -EINVAL;
> +
> + /* Watchdog counts in 1024 cycle steps */
> + tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
> +
> + /*
> + * We can only specify the upper 16 bits of a 24 bit value.
> + * Round up
> + */
> + tout_wdog = (tout_wdog + 0xff) >> 8;
> +
> + /* If the timeout overflows the hardware limit, set max */
> + if (tout_wdog >= 0x10000)
> + tout_wdog = 0xffff;
> +
> + val = FIELD_PREP(WDOG_MODE, 0x3) |
> + FIELD_PREP(WDOG_LEN, tout_wdog) |
> + FIELD_PREP(WDOG_CNT, tout_wdog << 8);
> + writeq(val, priv->reg + CORE0_WDOG_OFFSET);
> +
> + return 0;
> +}
> +
> +static int octeontx_wdt_stop(struct udevice *dev)
> +{
> + struct octeontx_wdt *priv = dev_get_priv(dev);
> +
> + writeq(0, priv->reg + CORE0_WDOG_OFFSET);
> +
> + return 0;
> +}
> +
> +static int octeontx_wdt_expire_now(struct udevice *dev, ulong flags)
> +{
> + octeontx_wdt_stop(dev);
> +
> + /* Start with 100ms timeout to expire immediately */
> + octeontx_wdt_start(dev, 100, flags);
> +
> + return 0;
> +}
> +
>   static int octeontx_wdt_reset(struct udevice *dev)
>   {
>   struct octeontx_wdt *priv = dev_get_priv(dev);
>  
> - writeq(~0ULL, priv->reg);
> + writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
> +
> + return 0;
> +}
> +
> +static int octeontx_wdt_remove(struct udevice *dev)
> +{
> + octeontx_wdt_stop(dev);
>  
>   return 0;
>   }
> @@ -31,24 +96,35 @@ static int octeontx_wdt_reset(struct udevice *dev)
>   static int octeontx_wdt_probe(struct udevice *dev)
>   {
>   struct octeontx_wdt *priv = dev_get_priv(dev);
> + int ret;
>  
>   priv->reg = dev_remap_addr(dev);
>   if (!priv->reg)
>   return -EINVAL;
>  
>   /*
> - * Save core poke register address in reg (its not 0xa0000 as
> - * extracted from the DT but 0x50000 instead)
> + * Save base register address in reg masking lower 20 bits
> + * as 0xa0000 appears when extracted from the DT
>   */
>   priv->reg = (void __iomem *)(((u64)priv->reg &
> -      ~CORE0_POKE_OFFSET_MASK) |
> -     CORE0_POKE_OFFSET);
> +      ~CORE0_POKE_OFFSET_MASK));
> +
> + ret = clk_get_by_index(dev, 0, &priv->clk);
> + if (ret < 0)
> + return ret;
> +
> + ret = clk_enable(&priv->clk);
> + if (ret)
> + return ret;
>  
>   return 0;
>   }
>  
>   static const struct wdt_ops octeontx_wdt_ops = {
>   .reset = octeontx_wdt_reset,
> + .start = octeontx_wdt_start,
> + .stop = octeontx_wdt_stop,
> + .expire_now = octeontx_wdt_expire_now,
>   };
>  
>   static const struct udevice_id octeontx_wdt_ids[] = {
> @@ -63,4 +139,6 @@ U_BOOT_DRIVER(wdt_octeontx) = {
>   .ops = &octeontx_wdt_ops,
>   .priv_auto_alloc_size = sizeof(struct octeontx_wdt),
>   .probe = octeontx_wdt_probe,
> + .remove = octeontx_wdt_remove,
> + .flags = DM_FLAG_OS_PREPARE,
>   };
>


Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: [hidden email]
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Re: [PATCH 4/4] arm: octeontx: Add CMD_WDT

Stefan Roese
In reply to this post by Stefan Roese
On 23.09.20 11:01, Stefan Roese wrote:
> Enable WDT command for Octeon TX/TX2 boards.
>
> Signed-off-by: Stefan Roese <[hidden email]>
> Cc: Aaron Williams <[hidden email]>
> Cc: Suneel Garapati <[hidden email]>
> Cc: Chandrakala Chavva <[hidden email]>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
>   configs/octeontx2_95xx_defconfig | 1 +
>   configs/octeontx2_96xx_defconfig | 1 +
>   configs/octeontx_81xx_defconfig  | 1 +
>   configs/octeontx_83xx_defconfig  | 1 +
>   4 files changed, 4 insertions(+)
>
> diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
> index 047cb45a21..a17e5521d9 100644
> --- a/configs/octeontx2_95xx_defconfig
> +++ b/configs/octeontx2_95xx_defconfig
> @@ -41,6 +41,7 @@ CONFIG_CMD_BKOPS_ENABLE=y
>   CONFIG_CMD_PART=y
>   CONFIG_CMD_PCI=y
>   CONFIG_CMD_SF_TEST=y
> +CONFIG_CMD_WDT=y
>   CONFIG_CMD_DHCP=y
>   CONFIG_CMD_TFTPPUT=y
>   CONFIG_CMD_TFTPSRV=y
> diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
> index 7b5a1243a7..2e6cef0684 100644
> --- a/configs/octeontx2_96xx_defconfig
> +++ b/configs/octeontx2_96xx_defconfig
> @@ -42,6 +42,7 @@ CONFIG_CMD_PART=y
>   CONFIG_CMD_PCI=y
>   CONFIG_CMD_SF_TEST=y
>   CONFIG_CMD_USB=y
> +CONFIG_CMD_WDT=y
>   CONFIG_CMD_DHCP=y
>   CONFIG_CMD_TFTPPUT=y
>   CONFIG_CMD_TFTPSRV=y
> diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
> index ca3286b901..ff24e6e1e8 100644
> --- a/configs/octeontx_81xx_defconfig
> +++ b/configs/octeontx_81xx_defconfig
> @@ -43,6 +43,7 @@ CONFIG_CMD_PART=y
>   CONFIG_CMD_PCI=y
>   CONFIG_CMD_SF_TEST=y
>   CONFIG_CMD_USB=y
> +CONFIG_CMD_WDT=y
>   CONFIG_CMD_DHCP=y
>   CONFIG_CMD_TFTPPUT=y
>   CONFIG_CMD_TFTPSRV=y
> diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
> index e7dd3f6b73..ab38d007ea 100644
> --- a/configs/octeontx_83xx_defconfig
> +++ b/configs/octeontx_83xx_defconfig
> @@ -41,6 +41,7 @@ CONFIG_CMD_PART=y
>   CONFIG_CMD_PCI=y
>   CONFIG_CMD_SF_TEST=y
>   CONFIG_CMD_USB=y
> +CONFIG_CMD_WDT=y
>   CONFIG_CMD_DHCP=y
>   CONFIG_CMD_TFTPPUT=y
>   CONFIG_CMD_TFTPSRV=y
>


Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: [hidden email]