[PATCH 1/3] imx: mx7: fix build warning when CONFIG_IMX_RDC not enabled

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[PATCH 1/3] imx: mx7: fix build warning when CONFIG_IMX_RDC not enabled

Peng Fan-4
Fix build warning when CONFIG_IMX_RDC not defined in defconfig.

Signed-off-by: Peng Fan <[hidden email]>
Cc: Stefano Babic <[hidden email]>
Cc: Fabio Estevam <[hidden email]>
---
 arch/arm/mach-imx/mx7/soc.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 4cf977e..ec74b4c 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -31,7 +31,7 @@ U_BOOT_DEVICE(imx7_thermal) = {
 };
 #endif
 
-#ifdef CONFIG_IMX_RDC
+#if CONFIG_IS_ENABLED(IMX_RDC)
 /*
  * In current design, if any peripheral was assigned to both A7 and M4,
  * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
@@ -245,8 +245,9 @@ int arch_cpu_init(void)
  mxs_dma_init();
 #endif
 
- if (IS_ENABLED(CONFIG_IMX_RDC))
- isolate_resource();
+#if CONFIG_IS_ENABLED(IMX_RDC)
+ isolate_resource();
+#endif
 
  return 0;
 }
--
2.6.2

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[PATCH 2/3] imx: Enable ACTLR.SMP bit for Cortex-A7 platforms

Peng Fan-4
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode,
it is not set. Here we set it for mx6/7/7ulp. The code will check whether
the PE is A7 or not.

Signed-off-by: Peng Fan <[hidden email]>
Cc: Stefano Babic <[hidden email]>
Cc: Fabio Estevam <[hidden email]>
---
 arch/arm/include/asm/mach-imx/sys_proto.h |  1 +
 arch/arm/mach-imx/cache.c                 | 28 ++++++++++++++++++++++++++++
 arch/arm/mach-imx/mx6/soc.c               |  2 ++
 arch/arm/mach-imx/mx7/soc.c               |  9 ++-------
 arch/arm/mach-imx/mx7ulp/soc.c            |  2 ++
 5 files changed, 35 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 046df62..26db1cc 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -87,6 +87,7 @@ static inline u8 imx6_is_bmode_from_gpr9(void)
 u32 imx6_src_get_boot_mode(void);
 #endif /* CONFIG_MX6 */
 
+void enable_actlr_smp(void);
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
 u32 get_cpu_speed_grade_hz(void);
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index c5279a7..e02f1a5 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -10,6 +10,34 @@
 #include <asm/io.h>
 #include <asm/mach-imx/sys_proto.h>
 
+void enable_actlr_smp(void)
+{
+ uint32_t val;
+
+ /* Read MIDR */
+ asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
+ val = (val >> 4);
+ val &= 0xf;
+
+ /* Only set the SMP for Cortex A7 */
+ if (val == 0x7) {
+ /* Read auxiliary control register */
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+
+ if (val & (1 << 6))
+ return;
+
+ /* Enable SMP */
+ val |= (1 << 6);
+
+ /* Write auxiliary control register */
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+
+ DSB;
+ ISB;
+ }
+}
+
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index af31673..0ef4b29 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -576,6 +576,8 @@ void s_init(void)
  u32 mask528;
  u32 reg, periph1, periph2;
 
+ enable_actlr_smp();
+
  if (is_mx6sx() || is_mx6ul() || is_mx6ull())
  return;
 
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index ec74b4c..4307ae0 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -447,13 +447,8 @@ int mmc_get_env_dev(void)
 
 void s_init(void)
 {
-#if !defined CONFIG_SPL_BUILD
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-#endif
+ enable_actlr_smp();
+
  /* clock configuration. */
  clock_init();
 
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 454665a..71bfe36 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -100,6 +100,8 @@ void init_wdog(void)
 
 void s_init(void)
 {
+ enable_actlr_smp();
+
  /* Disable wdog */
  init_wdog();
 
--
2.6.2

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[PATCH 3/3] mx7: add epdc qos settings

Peng Fan-4
In reply to this post by Peng Fan-4
This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.

Signed-off-by: Peng Fan <[hidden email]>
Cc: Stefano Babic <[hidden email]>
Cc: Fabio Estevam <[hidden email]>
---
 arch/arm/include/asm/arch-mx7/imx-regs.h |  5 +++++
 arch/arm/mach-imx/mx7/soc.c              | 38 ++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index aab3a9a..a6b2091 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -152,6 +152,11 @@
 #define IP2APB_AXIMON_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR+0x1E0000)
 #define QOSC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x1F0000)
 
+#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR
+#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400)
+#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00)
+#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00)
+
 /* AIPS_TZ#3  - Global enable (0) */
 #define ECSPI1_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x20000)
 #define ECSPI2_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x30000)
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 4307ae0..6b37848 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -230,6 +230,42 @@ static void imx_enet_mdio_fixup(void)
  }
 }
 
+static void set_epdc_qos(void)
+{
+ /* Disable clkgate & soft_reset */
+ writel(0, REGS_QOS_BASE);
+ /* Enable all masters */
+ writel(0, REGS_QOS_BASE + 0x60);
+ /* Disable clkgate & soft_reset */
+ writel(0, REGS_QOS_EPDC);
+ /* Disable clkgate & soft_reset */
+ writel(0, REGS_QOS_PXP0);
+ /* Disable clkgate & soft_reset */
+ writel(0, REGS_QOS_PXP1);
+ /* WR, init = 7 with red flag */
+ writel(0x0f020722, REGS_QOS_EPDC + 0xd0);
+ /* RD,  init = 7 with red flag */
+ writel(0x0f020722, REGS_QOS_EPDC + 0xe0);
+ /* OT_CTRL_EN =1 */
+ writel(1, REGS_QOS_PXP0);
+ /* OT_CTRL_EN =1 */
+ writel(1, REGS_QOS_PXP1);
+ /* WR,  init = 2 with red flag */
+ writel(0x0f020222, REGS_QOS_PXP0 + 0x50);
+ /* WR,  init = 2 with red flag */
+ writel(0x0f020222, REGS_QOS_PXP1 + 0x50);
+ /* rD,  init = 2 with red flag */
+ writel(0x0f020222, REGS_QOS_PXP0 + 0x60);
+ /* rD,  init = 2 with red flag */
+ writel(0x0f020222, REGS_QOS_PXP1 + 0x60);
+ /* tOTAL,  init = 4 with red flag */
+ writel(0x0f020422, REGS_QOS_PXP0 + 0x70);
+ /* TOTAL,  init = 4 with red flag */
+ writel(0x0f020422, REGS_QOS_PXP1 + 0x70);
+ /* EPDC AW/AR CACHE ENABLE */
+ writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034);
+}
+
 int arch_cpu_init(void)
 {
  init_aips();
@@ -240,6 +276,8 @@ int arch_cpu_init(void)
 
  imx_enet_mdio_fixup();
 
+ set_epdc_qos();
+
 #ifdef CONFIG_APBH_DMA
  /* Start APBH DMA */
  mxs_dma_init();
--
2.6.2

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Re: [PATCH 1/3] imx: mx7: fix build warning when CONFIG_IMX_RDC not enabled

Stefano Babic
In reply to this post by Peng Fan-4
On 12/08/2017 16:10, Peng Fan wrote:

> Fix build warning when CONFIG_IMX_RDC not defined in defconfig.
>
> Signed-off-by: Peng Fan <[hidden email]>
> Cc: Stefano Babic <[hidden email]>
> Cc: Fabio Estevam <[hidden email]>
> ---
>  arch/arm/mach-imx/mx7/soc.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
> index 4cf977e..ec74b4c 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -31,7 +31,7 @@ U_BOOT_DEVICE(imx7_thermal) = {
>  };
>  #endif
>  
> -#ifdef CONFIG_IMX_RDC
> +#if CONFIG_IS_ENABLED(IMX_RDC)
>  /*
>   * In current design, if any peripheral was assigned to both A7 and M4,
>   * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
> @@ -245,8 +245,9 @@ int arch_cpu_init(void)
>   mxs_dma_init();
>  #endif
>  
> - if (IS_ENABLED(CONFIG_IMX_RDC))
> - isolate_resource();
> +#if CONFIG_IS_ENABLED(IMX_RDC)
> + isolate_resource();
> +#endif
>  
>   return 0;
>  }
>

Applied to u-boot-imx, -master, thanks !

Best regards,
Stefano Babic




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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [hidden email]
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Re: [PATCH 3/3] mx7: add epdc qos settings

Stefano Babic
In reply to this post by Peng Fan-4
On 12/08/2017 16:10, Peng Fan wrote:

> This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.
>
> Signed-off-by: Peng Fan <[hidden email]>
> Cc: Stefano Babic <[hidden email]>
> Cc: Fabio Estevam <[hidden email]>
> ---
>  arch/arm/include/asm/arch-mx7/imx-regs.h |  5 +++++
>  arch/arm/mach-imx/mx7/soc.c              | 38 ++++++++++++++++++++++++++++++++
>  2 files changed, 43 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
> index aab3a9a..a6b2091 100644
> --- a/arch/arm/include/asm/arch-mx7/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
> @@ -152,6 +152,11 @@
>  #define IP2APB_AXIMON_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR+0x1E0000)
>  #define QOSC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x1F0000)
>  
> +#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR
> +#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400)
> +#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00)
> +#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00)
> +
>  /* AIPS_TZ#3  - Global enable (0) */
>  #define ECSPI1_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x20000)
>  #define ECSPI2_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x30000)
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
> index 4307ae0..6b37848 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -230,6 +230,42 @@ static void imx_enet_mdio_fixup(void)
>   }
>  }
>  
> +static void set_epdc_qos(void)
> +{
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_BASE);
> + /* Enable all masters */
> + writel(0, REGS_QOS_BASE + 0x60);
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_EPDC);
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_PXP0);
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_PXP1);
> + /* WR, init = 7 with red flag */
> + writel(0x0f020722, REGS_QOS_EPDC + 0xd0);
> + /* RD,  init = 7 with red flag */
> + writel(0x0f020722, REGS_QOS_EPDC + 0xe0);
> + /* OT_CTRL_EN =1 */
> + writel(1, REGS_QOS_PXP0);
> + /* OT_CTRL_EN =1 */
> + writel(1, REGS_QOS_PXP1);
> + /* WR,  init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP0 + 0x50);
> + /* WR,  init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP1 + 0x50);
> + /* rD,  init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP0 + 0x60);
> + /* rD,  init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP1 + 0x60);
> + /* tOTAL,  init = 4 with red flag */
> + writel(0x0f020422, REGS_QOS_PXP0 + 0x70);
> + /* TOTAL,  init = 4 with red flag */
> + writel(0x0f020422, REGS_QOS_PXP1 + 0x70);
> + /* EPDC AW/AR CACHE ENABLE */
> + writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034);
> +}

Comments are xhaustive, but can you set appropriate #define for all
constants ?

Best regards,
Stefano Babic


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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [hidden email]
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