[PATCH 06/18] mips: mtmips: add two reference boards for mt7620

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[PATCH 06/18] mips: mtmips: add two reference boards for mt7620

Weijie Gao-2
The mt7620_rfb board supports integrated 10/100M PHYs plus two external
giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.

The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
16MB SPI-NOR flash.

Signed-off-by: Weijie Gao <[hidden email]>
---
 arch/mips/dts/Makefile                       |   2 +
 arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts | 100 +++++++++++++++++++
 arch/mips/dts/mediatek,mt7620-rfb.dts        |  97 ++++++++++++++++++
 arch/mips/mach-mtmips/mt7620/Kconfig         |  17 ++++
 board/mediatek/mt7620/Kconfig                |  20 ++++
 board/mediatek/mt7620/MAINTAINERS            |   9 ++
 board/mediatek/mt7620/Makefile               |   3 +
 board/mediatek/mt7620/board.c                |   8 ++
 configs/mt7620_mt7530_rfb_defconfig          |  52 ++++++++++
 configs/mt7620_rfb_defconfig                 |  68 +++++++++++++
 10 files changed, 376 insertions(+)
 create mode 100644 arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
 create mode 100644 arch/mips/dts/mediatek,mt7620-rfb.dts
 create mode 100644 board/mediatek/mt7620/Kconfig
 create mode 100644 board/mediatek/mt7620/MAINTAINERS
 create mode 100644 board/mediatek/mt7620/Makefile
 create mode 100644 board/mediatek/mt7620/board.c
 create mode 100644 configs/mt7620_mt7530_rfb_defconfig
 create mode 100644 configs/mt7620_rfb_defconfig

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index e82f96d4e4..7c42923134 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -14,6 +14,8 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
+dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
 dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
 dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
 dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
diff --git a/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
new file mode 100644
index 0000000000..8bc3b1673a
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao <[hidden email]>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "mt7620.dtsi"
+
+/ {
+ compatible = "mediatek,mt7620-mt7530-rfb", "mediatek,mt7620-soc";
+ model = "MediaTek MT7620-MT7530 RFB (MTKC712)";
+
+ aliases {
+ serial0 = &uartlite;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = &uartlite;
+ };
+};
+
+&uartlite {
+ status = "okay";
+};
+
+&pinctrl {
+ state_default: pin_state {
+ pleds {
+ groups = "ephy led", "wled";
+ function = "led";
+ };
+
+ gpios {
+ groups = "pa", "uartf";
+ function = "gpio";
+ };
+ };
+
+ gsw_pins: gsw_pins {
+ mdio {
+ groups = "mdio";
+ function = "mdio";
+ };
+
+ rgmii1 {
+ groups = "rgmii1";
+ function = "rgmii1";
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
+
+&gpio0 {
+ pa0_pull_low {
+ gpio-hog;
+ output-low;
+ gpios = <20 GPIO_ACTIVE_HIGH>;
+ };
+
+ pa1_pull_low {
+ gpio-hog;
+ output-low;
+ gpios = <21 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&eth {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsw_pins>;
+
+ port5 {
+ phy-mode = "rgmii";
+ phy-addr = <5>;
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ mediatek,mt7530;
+ mediatek,mt7530-reset = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
diff --git a/arch/mips/dts/mediatek,mt7620-rfb.dts b/arch/mips/dts/mediatek,mt7620-rfb.dts
new file mode 100644
index 0000000000..616903e554
--- /dev/null
+++ b/arch/mips/dts/mediatek,mt7620-rfb.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc.
+ *
+ * Author: Weijie Gao <[hidden email]>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "mt7620.dtsi"
+
+/ {
+ compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc";
+ model = "MediaTek MT7620 RFB (WS2120)";
+
+ aliases {
+ serial0 = &uartlite;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = &uartlite;
+ };
+};
+
+&uartlite {
+ status = "okay";
+};
+
+&pinctrl {
+ state_default: pin_state {
+ pleds {
+ groups = "ephy led", "wled";
+ function = "led";
+ };
+
+ gpios {
+ groups = "uartf";
+ function = "gpio";
+ };
+ };
+
+ gsw_pins: gsw_pins {
+ mdio {
+ groups = "mdio";
+ function = "mdio";
+ };
+
+ rgmii1 {
+ groups = "rgmii1";
+ function = "rgmii1";
+ };
+
+ rgmii2 {
+ groups = "rgmii2";
+ function = "rgmii2";
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <2>;
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <25000000>;
+ reg = <0>;
+ };
+};
+
+&eth {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gsw_pins>;
+
+ port4 {
+ phy-mode = "rgmii";
+ phy-addr = <4>;
+ };
+
+ port5 {
+ phy-mode = "rgmii";
+ phy-addr = <5>;
+ };
+};
+
+&mmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+
+ status = "okay";
+};
diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig
index aa7cf1d3c1..5db83eb9d9 100644
--- a/arch/mips/mach-mtmips/mt7620/Kconfig
+++ b/arch/mips/mach-mtmips/mt7620/Kconfig
@@ -7,6 +7,21 @@ config DEBUG_UART_BOARD_INIT
 choice
  prompt "Board select"
 
+config BOARD_MT7620_RFB
+ bool "MediaTek MT7620 RFB"
+ help
+  The reference design of MT7620A (WS2120). The board has 64 MiB DDR2,
+  8 MiB SPI-NOR flash, 1 built-in 6 port switch (two GE PHYs and five
+  FE PHYs,one port can be configured to use either FE PHY or GE PHY),
+  1 UART, 1 USB host, 1 SDXC, 1 PCIe socket and JTAG pins.
+
+config BOARD_MT7620_MT7530_RFB
+ bool "MediaTek MT7620-MT7530 RFB"
+ help
+  The reference design of MT7620DA (MTKC712). The board has 64 MiB
+  intergrated DDR2 KGD, 16 MiB SPI-NOR flash, an external 5-port giga
+  switch MT7530 and 1 UART.
+
 endchoice
 
 choice
@@ -51,4 +66,6 @@ config CPU_FREQ_MULTI
  default 6 if CPU_FREQ_600MHZ
  default 7 if CPU_FREQ_620MHZ
 
+source "board/mediatek/mt7620/Kconfig"
+
 endif
diff --git a/board/mediatek/mt7620/Kconfig b/board/mediatek/mt7620/Kconfig
new file mode 100644
index 0000000000..db72332cb4
--- /dev/null
+++ b/board/mediatek/mt7620/Kconfig
@@ -0,0 +1,20 @@
+if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
+
+config SYS_BOARD
+ default "mt7620"
+
+config SYS_VENDOR
+ default "mediatek"
+
+config SYS_CONFIG_NAME
+ default "mt7620"
+
+config MT7620_UART1_BASE
+ hex
+ default 0xb0000c00
+
+config MT7620_UART1_CLK
+ int
+ default 40000000
+
+endif
diff --git a/board/mediatek/mt7620/MAINTAINERS b/board/mediatek/mt7620/MAINTAINERS
new file mode 100644
index 0000000000..05db777ced
--- /dev/null
+++ b/board/mediatek/mt7620/MAINTAINERS
@@ -0,0 +1,9 @@
+MT7620_RFB BOARD
+M: Weijie Gao <[hidden email]>
+S: Maintained
+F: board/mediatek/mt7620
+F: include/configs/mt7620.h
+F: configs/mt7620_rfb_defconfig
+F: configs/mt7620_mt7530_rfb_defconfig
+F: arch/mips/dts/mediatek,mt7620-rfb.dts
+F: arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
diff --git a/board/mediatek/mt7620/Makefile b/board/mediatek/mt7620/Makefile
new file mode 100644
index 0000000000..db129c5aba
--- /dev/null
+++ b/board/mediatek/mt7620/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += board.o
diff --git a/board/mediatek/mt7620/board.c b/board/mediatek/mt7620/board.c
new file mode 100644
index 0000000000..f837a06fbb
--- /dev/null
+++ b/board/mediatek/mt7620/board.c
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <[hidden email]>
+ */
+
+#include <common.h>
diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig
new file mode 100644
index 0000000000..ea10f5d5f3
--- /dev/null
+++ b/configs/mt7620_mt7530_rfb_defconfig
@@ -0,0 +1,52 @@
+CONFIG_MIPS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x30000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xb0000c00
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ARCH_MTMIPS=y
+CONFIG_BOARD_MT7620_MT7530_RFB=y
+CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb"
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_GPIO_HOG=y
+# CONFIG_INPUT is not set
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_MT7620_ETH=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SPI=y
+CONFIG_MT7620_SPI=y
+CONFIG_LZMA=y
+CONFIG_SPL_LZMA=y
diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig
new file mode 100644
index 0000000000..8cc82bc36b
--- /dev/null
+++ b/configs/mt7620_rfb_defconfig
@@ -0,0 +1,68 @@
+CONFIG_MIPS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x30000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xb0000c00
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_ARCH_MTMIPS=y
+CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb"
+CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_SPL_NOR_SUPPORT=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_DM is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_GPIO_HOG=y
+# CONFIG_INPUT is not set
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_MMC_QUIRKS is not set
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_MTK=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_MT7620_ETH=y
+CONFIG_PHY=y
+CONFIG_MT7620_USB_PHY=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SPI=y
+CONFIG_MT7620_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_LZMA=y
+CONFIG_SPL_LZMA=y
--
2.17.1
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Re: [PATCH 06/18] mips: mtmips: add two reference boards for mt7620

Daniel Schwierzeck-2
Am Freitag, den 16.10.2020, 15:35 +0800 schrieb Weijie Gao:

> The mt7620_rfb board supports integrated 10/100M PHYs plus two external
> giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
>
> The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
> 16MB SPI-NOR flash.
>
> Signed-off-by: Weijie Gao <[hidden email]>
> ---
>  arch/mips/dts/Makefile                       |   2 +
>  arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts | 100 +++++++++++++++++++
>  arch/mips/dts/mediatek,mt7620-rfb.dts        |  97 ++++++++++++++++++
>  arch/mips/mach-mtmips/mt7620/Kconfig         |  17 ++++
>  board/mediatek/mt7620/Kconfig                |  20 ++++
>  board/mediatek/mt7620/MAINTAINERS            |   9 ++
>  board/mediatek/mt7620/Makefile               |   3 +
>  board/mediatek/mt7620/board.c                |   8 ++
>  configs/mt7620_mt7530_rfb_defconfig          |  52 ++++++++++
>  configs/mt7620_rfb_defconfig                 |  68 +++++++++++++
>  10 files changed, 376 insertions(+)
>  create mode 100644 arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
>  create mode 100644 arch/mips/dts/mediatek,mt7620-rfb.dts
>  create mode 100644 board/mediatek/mt7620/Kconfig
>  create mode 100644 board/mediatek/mt7620/MAINTAINERS
>  create mode 100644 board/mediatek/mt7620/Makefile
>  create mode 100644 board/mediatek/mt7620/board.c
>  create mode 100644 configs/mt7620_mt7530_rfb_defconfig
>  create mode 100644 configs/mt7620_rfb_defconfig
>
> diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> index e82f96d4e4..7c42923134 100644
> --- a/arch/mips/dts/Makefile
> +++ b/arch/mips/dts/Makefile
> @@ -14,6 +14,8 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
>  dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
>  dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
>  dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
> +dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
> +dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
>  dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
>  dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
>  dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
> diff --git a/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
> new file mode 100644
> index 0000000000..8bc3b1673a
> --- /dev/null
> +++ b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 MediaTek Inc.
> + *
> + * Author: Weijie Gao <[hidden email]>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "mt7620.dtsi"
> +
> +/ {
> + compatible = "mediatek,mt7620-mt7530-rfb", "mediatek,mt7620-soc";
> + model = "MediaTek MT7620-MT7530 RFB (MTKC712)";
> +
> + aliases {
> + serial0 = &uartlite;
> + spi0 = &spi0;
> + };
> +
> + chosen {
> + stdout-path = &uartlite;
> + };
> +};
> +
> +&uartlite {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + state_default: pin_state {
> + pleds {
> + groups = "ephy led", "wled";
> + function = "led";
> + };
> +
> + gpios {
> + groups = "pa", "uartf";
> + function = "gpio";
> + };
> + };
> +
> + gsw_pins: gsw_pins {
> + mdio {
> + groups = "mdio";
> + function = "mdio";
> + };
> +
> + rgmii1 {
> + groups = "rgmii1";
> + function = "rgmii1";
> + };
> + };
> +};
> +
> +&spi0 {
> + status = "okay";
> + num-cs = <2>;
> +
> + spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <25000000>;
> + reg = <0>;
> + };
> +};
> +
> +&gpio0 {
> + pa0_pull_low {
> + gpio-hog;
> + output-low;
> + gpios = <20 GPIO_ACTIVE_HIGH>;
> + };
> +
> + pa1_pull_low {
> + gpio-hog;
> + output-low;
> + gpios = <21 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&eth {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&gsw_pins>;
> +
> + port5 {
> + phy-mode = "rgmii";
> + phy-addr = <5>;
> + fixed-link {
> + full-duplex;
> + speed = <1000>;
> + mediatek,mt7530;
> + mediatek,mt7530-reset = <&gpio0 10 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> diff --git a/arch/mips/dts/mediatek,mt7620-rfb.dts b/arch/mips/dts/mediatek,mt7620-rfb.dts
> new file mode 100644
> index 0000000000..616903e554
> --- /dev/null
> +++ b/arch/mips/dts/mediatek,mt7620-rfb.dts
> @@ -0,0 +1,97 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 MediaTek Inc.
> + *
> + * Author: Weijie Gao <[hidden email]>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include "mt7620.dtsi"
> +
> +/ {
> + compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc";
> + model = "MediaTek MT7620 RFB (WS2120)";
> +
> + aliases {
> + serial0 = &uartlite;
> + spi0 = &spi0;
> + };
> +
> + chosen {
> + stdout-path = &uartlite;
> + };
> +};
> +
> +&uartlite {
> + status = "okay";
> +};
> +
> +&pinctrl {
> + state_default: pin_state {
> + pleds {
> + groups = "ephy led", "wled";
> + function = "led";
> + };
> +
> + gpios {
> + groups = "uartf";
> + function = "gpio";
> + };
> + };
> +
> + gsw_pins: gsw_pins {
> + mdio {
> + groups = "mdio";
> + function = "mdio";
> + };
> +
> + rgmii1 {
> + groups = "rgmii1";
> + function = "rgmii1";
> + };
> +
> + rgmii2 {
> + groups = "rgmii2";
> + function = "rgmii2";
> + };
> + };
> +};
> +
> +&spi0 {
> + status = "okay";
> + num-cs = <2>;
> +
> + spi-flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <25000000>;
> + reg = <0>;
> + };
> +};
> +
> +&eth {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&gsw_pins>;
> +
> + port4 {
> + phy-mode = "rgmii";
> + phy-addr = <4>;
> + };
> +
> + port5 {
> + phy-mode = "rgmii";
> + phy-addr = <5>;
> + };
> +};
> +
> +&mmc {
> + bus-width = <4>;
> + cap-sd-highspeed;
> +
> + status = "okay";
> +};
> diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig
> index aa7cf1d3c1..5db83eb9d9 100644
> --- a/arch/mips/mach-mtmips/mt7620/Kconfig
> +++ b/arch/mips/mach-mtmips/mt7620/Kconfig
> @@ -7,6 +7,21 @@ config DEBUG_UART_BOARD_INIT
>  choice
>   prompt "Board select"
>  
> +config BOARD_MT7620_RFB
> + bool "MediaTek MT7620 RFB"
> + help
> +  The reference design of MT7620A (WS2120). The board has 64 MiB DDR2,
> +  8 MiB SPI-NOR flash, 1 built-in 6 port switch (two GE PHYs and five
> +  FE PHYs,one port can be configured to use either FE PHY or GE PHY),
> +  1 UART, 1 USB host, 1 SDXC, 1 PCIe socket and JTAG pins.
> +
> +config BOARD_MT7620_MT7530_RFB
> + bool "MediaTek MT7620-MT7530 RFB"
> + help
> +  The reference design of MT7620DA (MTKC712). The board has 64 MiB
> +  intergrated DDR2 KGD, 16 MiB SPI-NOR flash, an external 5-port giga
> +  switch MT7530 and 1 UART.
> +
>  endchoice
>  
>  choice
> @@ -51,4 +66,6 @@ config CPU_FREQ_MULTI
>   default 6 if CPU_FREQ_600MHZ
>   default 7 if CPU_FREQ_620MHZ
>  
> +source "board/mediatek/mt7620/Kconfig"
> +
>  endif
> diff --git a/board/mediatek/mt7620/Kconfig b/board/mediatek/mt7620/Kconfig
> new file mode 100644
> index 0000000000..db72332cb4
> --- /dev/null
> +++ b/board/mediatek/mt7620/Kconfig
> @@ -0,0 +1,20 @@
> +if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
> +
> +config SYS_BOARD
> + default "mt7620"
> +
> +config SYS_VENDOR
> + default "mediatek"
> +
> +config SYS_CONFIG_NAME
> + default "mt7620"
> +
> +config MT7620_UART1_BASE
> + hex
> + default 0xb0000c00
> +
> +config MT7620_UART1_CLK
> + int
> + default 40000000

why and where do you need those? This looks redundant
CONFIG_DEBUG_UART_BASE and CONFIG_DEBUG_UART_CLOCK.

> +
> +endif
> diff --git a/board/mediatek/mt7620/MAINTAINERS b/board/mediatek/mt7620/MAINTAINERS
> new file mode 100644
> index 0000000000..05db777ced
> --- /dev/null
> +++ b/board/mediatek/mt7620/MAINTAINERS
> @@ -0,0 +1,9 @@
> +MT7620_RFB BOARD
> +M: Weijie Gao <[hidden email]>
> +S: Maintained
> +F: board/mediatek/mt7620
> +F: include/configs/mt7620.h
> +F: configs/mt7620_rfb_defconfig
> +F: configs/mt7620_mt7530_rfb_defconfig
> +F: arch/mips/dts/mediatek,mt7620-rfb.dts
> +F: arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
> diff --git a/board/mediatek/mt7620/Makefile b/board/mediatek/mt7620/Makefile
> new file mode 100644
> index 0000000000..db129c5aba
> --- /dev/null
> +++ b/board/mediatek/mt7620/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += board.o
> diff --git a/board/mediatek/mt7620/board.c b/board/mediatek/mt7620/board.c
> new file mode 100644
> index 0000000000..f837a06fbb
> --- /dev/null
> +++ b/board/mediatek/mt7620/board.c
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
> + *
> + * Author: Weijie Gao <[hidden email]>
> + */
> +
> +#include <common.h>
> diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig
> new file mode 100644
> index 0000000000..ea10f5d5f3
> --- /dev/null
> +++ b/configs/mt7620_mt7530_rfb_defconfig
> @@ -0,0 +1,52 @@
> +CONFIG_MIPS=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_ENV_OFFSET=0x30000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
> +CONFIG_SPL=y
> +CONFIG_DEBUG_UART_BASE=0xb0000c00
> +CONFIG_DEBUG_UART_CLOCK=40000000
> +CONFIG_ARCH_MTMIPS=y
> +CONFIG_BOARD_MT7620_MT7530_RFB=y
> +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb"
> +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
> +CONFIG_MIPS_BOOT_FDT=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
> +CONFIG_SPL_NOR_SUPPORT=y
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_CRC32 is not set
> +# CONFIG_CMD_DM is not set
> +CONFIG_CMD_GPIO=y
> +# CONFIG_CMD_LOADS is not set
> +CONFIG_CMD_SPI=y
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_MII=y
> +# CONFIG_CMD_MDIO is not set
> +# CONFIG_PARTITIONS is not set
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_GPIO_HOG=y
> +# CONFIG_INPUT is not set
> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> +CONFIG_SPI_FLASH_EON=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_ISSI=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_XMC=y
> +CONFIG_MT7620_ETH=y
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SPI=y
> +CONFIG_MT7620_SPI=y
> +CONFIG_LZMA=y
> +CONFIG_SPL_LZMA=y
> diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig
> new file mode 100644
> index 0000000000..8cc82bc36b
> --- /dev/null
> +++ b/configs/mt7620_rfb_defconfig
> @@ -0,0 +1,68 @@
> +CONFIG_MIPS=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_ENV_OFFSET=0x30000
> +CONFIG_ENV_SECT_SIZE=0x10000
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
> +CONFIG_SPL=y
> +CONFIG_DEBUG_UART_BASE=0xb0000c00
> +CONFIG_DEBUG_UART_CLOCK=40000000
> +CONFIG_ARCH_MTMIPS=y
> +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb"
> +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
> +CONFIG_MIPS_BOOT_FDT=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
> +CONFIG_SPL_NOR_SUPPORT=y
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_XIMG is not set
> +# CONFIG_CMD_CRC32 is not set
> +# CONFIG_CMD_DM is not set
> +CONFIG_CMD_GPIO=y
> +# CONFIG_CMD_LOADS is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_MII=y
> +# CONFIG_CMD_MDIO is not set
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_EFI_PARTITION=y
> +# CONFIG_SPL_EFI_PARTITION is not set
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_GPIO_HOG=y
> +# CONFIG_INPUT is not set
> +CONFIG_MMC=y
> +CONFIG_DM_MMC=y
> +# CONFIG_MMC_QUIRKS is not set
> +# CONFIG_MMC_HW_PARTITIONING is not set
> +CONFIG_MMC_MTK=y
> +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> +CONFIG_SPI_FLASH_EON=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_ISSI=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_STMICRO=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_XMC=y
> +CONFIG_MT7620_ETH=y
> +CONFIG_PHY=y
> +CONFIG_MT7620_USB_PHY=y
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SPI=y
> +CONFIG_MT7620_SPI=y
> +CONFIG_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_LZMA=y
> +CONFIG_SPL_LZMA=y
> --
> 2.17.1
--
- Daniel

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Re: [PATCH 06/18] mips: mtmips: add two reference boards for mt7620

Weijie Gao-2
On Mon, 2020-10-26 at 14:06 +0100, Daniel Schwierzeck wrote:

> Am Freitag, den 16.10.2020, 15:35 +0800 schrieb Weijie Gao:
> > The mt7620_rfb board supports integrated 10/100M PHYs plus two external
> > giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB.
> >
> > The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a
> > 16MB SPI-NOR flash.
> >
> > Signed-off-by: Weijie Gao <[hidden email]>
> > ---
> >  arch/mips/dts/Makefile                       |   2 +
> >  arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts | 100 +++++++++++++++++++
> >  arch/mips/dts/mediatek,mt7620-rfb.dts        |  97 ++++++++++++++++++
> >  arch/mips/mach-mtmips/mt7620/Kconfig         |  17 ++++
> >  board/mediatek/mt7620/Kconfig                |  20 ++++
> >  board/mediatek/mt7620/MAINTAINERS            |   9 ++
> >  board/mediatek/mt7620/Makefile               |   3 +
> >  board/mediatek/mt7620/board.c                |   8 ++
> >  configs/mt7620_mt7530_rfb_defconfig          |  52 ++++++++++
> >  configs/mt7620_rfb_defconfig                 |  68 +++++++++++++
> >  10 files changed, 376 insertions(+)
> >  create mode 100644 arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
> >  create mode 100644 arch/mips/dts/mediatek,mt7620-rfb.dts
> >  create mode 100644 board/mediatek/mt7620/Kconfig
> >  create mode 100644 board/mediatek/mt7620/MAINTAINERS
> >  create mode 100644 board/mediatek/mt7620/Makefile
> >  create mode 100644 board/mediatek/mt7620/board.c
> >  create mode 100644 configs/mt7620_mt7530_rfb_defconfig
> >  create mode 100644 configs/mt7620_rfb_defconfig
> >
> > diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
> > index e82f96d4e4..7c42923134 100644
> > --- a/arch/mips/dts/Makefile
> > +++ b/arch/mips/dts/Makefile
> > @@ -14,6 +14,8 @@ dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
> >  dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
> >  dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
> >  dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
> > +dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
> > +dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
> >  dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
> >  dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
> >  dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
> > diff --git a/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
> > new file mode 100644
> > index 0000000000..8bc3b1673a
> > --- /dev/null
> > +++ b/arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
> > @@ -0,0 +1,100 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 MediaTek Inc.
> > + *
> > + * Author: Weijie Gao <[hidden email]>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include "mt7620.dtsi"
> > +
> > +/ {
> > + compatible = "mediatek,mt7620-mt7530-rfb", "mediatek,mt7620-soc";
> > + model = "MediaTek MT7620-MT7530 RFB (MTKC712)";
> > +
> > + aliases {
> > + serial0 = &uartlite;
> > + spi0 = &spi0;
> > + };
> > +
> > + chosen {
> > + stdout-path = &uartlite;
> > + };
> > +};
> > +
> > +&uartlite {
> > + status = "okay";
> > +};
> > +
> > +&pinctrl {
> > + state_default: pin_state {
> > + pleds {
> > + groups = "ephy led", "wled";
> > + function = "led";
> > + };
> > +
> > + gpios {
> > + groups = "pa", "uartf";
> > + function = "gpio";
> > + };
> > + };
> > +
> > + gsw_pins: gsw_pins {
> > + mdio {
> > + groups = "mdio";
> > + function = "mdio";
> > + };
> > +
> > + rgmii1 {
> > + groups = "rgmii1";
> > + function = "rgmii1";
> > + };
> > + };
> > +};
> > +
> > +&spi0 {
> > + status = "okay";
> > + num-cs = <2>;
> > +
> > + spi-flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-max-frequency = <25000000>;
> > + reg = <0>;
> > + };
> > +};
> > +
> > +&gpio0 {
> > + pa0_pull_low {
> > + gpio-hog;
> > + output-low;
> > + gpios = <20 GPIO_ACTIVE_HIGH>;
> > + };
> > +
> > + pa1_pull_low {
> > + gpio-hog;
> > + output-low;
> > + gpios = <21 GPIO_ACTIVE_HIGH>;
> > + };
> > +};
> > +
> > +&eth {
> > + status = "okay";
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&gsw_pins>;
> > +
> > + port5 {
> > + phy-mode = "rgmii";
> > + phy-addr = <5>;
> > + fixed-link {
> > + full-duplex;
> > + speed = <1000>;
> > + mediatek,mt7530;
> > + mediatek,mt7530-reset = <&gpio0 10 GPIO_ACTIVE_HIGH>;
> > + };
> > + };
> > +};
> > diff --git a/arch/mips/dts/mediatek,mt7620-rfb.dts b/arch/mips/dts/mediatek,mt7620-rfb.dts
> > new file mode 100644
> > index 0000000000..616903e554
> > --- /dev/null
> > +++ b/arch/mips/dts/mediatek,mt7620-rfb.dts
> > @@ -0,0 +1,97 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 MediaTek Inc.
> > + *
> > + * Author: Weijie Gao <[hidden email]>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include "mt7620.dtsi"
> > +
> > +/ {
> > + compatible = "mediatek,mt7620-rfb", "mediatek,mt7620-soc";
> > + model = "MediaTek MT7620 RFB (WS2120)";
> > +
> > + aliases {
> > + serial0 = &uartlite;
> > + spi0 = &spi0;
> > + };
> > +
> > + chosen {
> > + stdout-path = &uartlite;
> > + };
> > +};
> > +
> > +&uartlite {
> > + status = "okay";
> > +};
> > +
> > +&pinctrl {
> > + state_default: pin_state {
> > + pleds {
> > + groups = "ephy led", "wled";
> > + function = "led";
> > + };
> > +
> > + gpios {
> > + groups = "uartf";
> > + function = "gpio";
> > + };
> > + };
> > +
> > + gsw_pins: gsw_pins {
> > + mdio {
> > + groups = "mdio";
> > + function = "mdio";
> > + };
> > +
> > + rgmii1 {
> > + groups = "rgmii1";
> > + function = "rgmii1";
> > + };
> > +
> > + rgmii2 {
> > + groups = "rgmii2";
> > + function = "rgmii2";
> > + };
> > + };
> > +};
> > +
> > +&spi0 {
> > + status = "okay";
> > + num-cs = <2>;
> > +
> > + spi-flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + spi-max-frequency = <25000000>;
> > + reg = <0>;
> > + };
> > +};
> > +
> > +&eth {
> > + status = "okay";
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&gsw_pins>;
> > +
> > + port4 {
> > + phy-mode = "rgmii";
> > + phy-addr = <4>;
> > + };
> > +
> > + port5 {
> > + phy-mode = "rgmii";
> > + phy-addr = <5>;
> > + };
> > +};
> > +
> > +&mmc {
> > + bus-width = <4>;
> > + cap-sd-highspeed;
> > +
> > + status = "okay";
> > +};
> > diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig
> > index aa7cf1d3c1..5db83eb9d9 100644
> > --- a/arch/mips/mach-mtmips/mt7620/Kconfig
> > +++ b/arch/mips/mach-mtmips/mt7620/Kconfig
> > @@ -7,6 +7,21 @@ config DEBUG_UART_BOARD_INIT
> >  choice
> >   prompt "Board select"
> >  
> > +config BOARD_MT7620_RFB
> > + bool "MediaTek MT7620 RFB"
> > + help
> > +  The reference design of MT7620A (WS2120). The board has 64 MiB DDR2,
> > +  8 MiB SPI-NOR flash, 1 built-in 6 port switch (two GE PHYs and five
> > +  FE PHYs,one port can be configured to use either FE PHY or GE PHY),
> > +  1 UART, 1 USB host, 1 SDXC, 1 PCIe socket and JTAG pins.
> > +
> > +config BOARD_MT7620_MT7530_RFB
> > + bool "MediaTek MT7620-MT7530 RFB"
> > + help
> > +  The reference design of MT7620DA (MTKC712). The board has 64 MiB
> > +  intergrated DDR2 KGD, 16 MiB SPI-NOR flash, an external 5-port giga
> > +  switch MT7530 and 1 UART.
> > +
> >  endchoice
> >  
> >  choice
> > @@ -51,4 +66,6 @@ config CPU_FREQ_MULTI
> >   default 6 if CPU_FREQ_600MHZ
> >   default 7 if CPU_FREQ_620MHZ
> >  
> > +source "board/mediatek/mt7620/Kconfig"
> > +
> >  endif
> > diff --git a/board/mediatek/mt7620/Kconfig b/board/mediatek/mt7620/Kconfig
> > new file mode 100644
> > index 0000000000..db72332cb4
> > --- /dev/null
> > +++ b/board/mediatek/mt7620/Kconfig
> > @@ -0,0 +1,20 @@
> > +if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB
> > +
> > +config SYS_BOARD
> > + default "mt7620"
> > +
> > +config SYS_VENDOR
> > + default "mediatek"
> > +
> > +config SYS_CONFIG_NAME
> > + default "mt7620"
> > +
> > +config MT7620_UART1_BASE
> > + hex
> > + default 0xb0000c00
> > +
> > +config MT7620_UART1_CLK
> > + int
> > + default 40000000
>
> why and where do you need those? This looks redundant
> CONFIG_DEBUG_UART_BASE and CONFIG_DEBUG_UART_CLOCK.

This config is used for the mt7620 uart driver (non-DM mode) in SPL.
This option is similar to the CONFIG_SYS_NS16550_CLK. But since mt7620
uart driver is not compatible with the ns16550a driver, I have to define
new configs for it.

Please refer to [PATCH 08/18] serial: add uart driver for MediaTek
MT7620 SoC

>
> > +
> > +endif
> > diff --git a/board/mediatek/mt7620/MAINTAINERS b/board/mediatek/mt7620/MAINTAINERS
> > new file mode 100644
> > index 0000000000..05db777ced
> > --- /dev/null
> > +++ b/board/mediatek/mt7620/MAINTAINERS
> > @@ -0,0 +1,9 @@
> > +MT7620_RFB BOARD
> > +M: Weijie Gao <[hidden email]>
> > +S: Maintained
> > +F: board/mediatek/mt7620
> > +F: include/configs/mt7620.h
> > +F: configs/mt7620_rfb_defconfig
> > +F: configs/mt7620_mt7530_rfb_defconfig
> > +F: arch/mips/dts/mediatek,mt7620-rfb.dts
> > +F: arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts
> > diff --git a/board/mediatek/mt7620/Makefile b/board/mediatek/mt7620/Makefile
> > new file mode 100644
> > index 0000000000..db129c5aba
> > --- /dev/null
> > +++ b/board/mediatek/mt7620/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +obj-y += board.o
> > diff --git a/board/mediatek/mt7620/board.c b/board/mediatek/mt7620/board.c
> > new file mode 100644
> > index 0000000000..f837a06fbb
> > --- /dev/null
> > +++ b/board/mediatek/mt7620/board.c
> > @@ -0,0 +1,8 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
> > + *
> > + * Author: Weijie Gao <[hidden email]>
> > + */
> > +
> > +#include <common.h>
> > diff --git a/configs/mt7620_mt7530_rfb_defconfig b/configs/mt7620_mt7530_rfb_defconfig
> > new file mode 100644
> > index 0000000000..ea10f5d5f3
> > --- /dev/null
> > +++ b/configs/mt7620_mt7530_rfb_defconfig
> > @@ -0,0 +1,52 @@
> > +CONFIG_MIPS=y
> > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > +CONFIG_NR_DRAM_BANKS=1
> > +CONFIG_ENV_SIZE=0x1000
> > +CONFIG_ENV_OFFSET=0x30000
> > +CONFIG_ENV_SECT_SIZE=0x10000
> > +CONFIG_SPL_SERIAL_SUPPORT=y
> > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
> > +CONFIG_SPL=y
> > +CONFIG_DEBUG_UART_BASE=0xb0000c00
> > +CONFIG_DEBUG_UART_CLOCK=40000000
> > +CONFIG_ARCH_MTMIPS=y
> > +CONFIG_BOARD_MT7620_MT7530_RFB=y
> > +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-mt7530-rfb"
> > +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
> > +CONFIG_MIPS_BOOT_FDT=y
> > +CONFIG_DEBUG_UART=y
> > +CONFIG_FIT=y
> > +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
> > +CONFIG_SPL_NOR_SUPPORT=y
> > +# CONFIG_CMD_ELF is not set
> > +# CONFIG_CMD_XIMG is not set
> > +# CONFIG_CMD_CRC32 is not set
> > +# CONFIG_CMD_DM is not set
> > +CONFIG_CMD_GPIO=y
> > +# CONFIG_CMD_LOADS is not set
> > +CONFIG_CMD_SPI=y
> > +# CONFIG_CMD_NFS is not set
> > +CONFIG_CMD_MII=y
> > +# CONFIG_CMD_MDIO is not set
> > +# CONFIG_PARTITIONS is not set
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> > +CONFIG_NET_RANDOM_ETHADDR=y
> > +CONFIG_GPIO_HOG=y
> > +# CONFIG_INPUT is not set
> > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> > +CONFIG_SPI_FLASH_EON=y
> > +CONFIG_SPI_FLASH_GIGADEVICE=y
> > +CONFIG_SPI_FLASH_ISSI=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_SPI_FLASH_WINBOND=y
> > +CONFIG_SPI_FLASH_XMC=y
> > +CONFIG_MT7620_ETH=y
> > +CONFIG_DEBUG_UART_SHIFT=2
> > +CONFIG_SPI=y
> > +CONFIG_MT7620_SPI=y
> > +CONFIG_LZMA=y
> > +CONFIG_SPL_LZMA=y
> > diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig
> > new file mode 100644
> > index 0000000000..8cc82bc36b
> > --- /dev/null
> > +++ b/configs/mt7620_rfb_defconfig
> > @@ -0,0 +1,68 @@
> > +CONFIG_MIPS=y
> > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > +CONFIG_NR_DRAM_BANKS=1
> > +CONFIG_ENV_SIZE=0x1000
> > +CONFIG_ENV_OFFSET=0x30000
> > +CONFIG_ENV_SECT_SIZE=0x10000
> > +CONFIG_SPL_SERIAL_SUPPORT=y
> > +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
> > +CONFIG_SPL=y
> > +CONFIG_DEBUG_UART_BASE=0xb0000c00
> > +CONFIG_DEBUG_UART_CLOCK=40000000
> > +CONFIG_ARCH_MTMIPS=y
> > +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7620-rfb"
> > +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
> > +CONFIG_MIPS_BOOT_FDT=y
> > +CONFIG_DEBUG_UART=y
> > +CONFIG_FIT=y
> > +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
> > +CONFIG_SPL_NOR_SUPPORT=y
> > +# CONFIG_CMD_ELF is not set
> > +# CONFIG_CMD_XIMG is not set
> > +# CONFIG_CMD_CRC32 is not set
> > +# CONFIG_CMD_DM is not set
> > +CONFIG_CMD_GPIO=y
> > +# CONFIG_CMD_LOADS is not set
> > +CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +# CONFIG_CMD_NFS is not set
> > +CONFIG_CMD_MII=y
> > +# CONFIG_CMD_MDIO is not set
> > +CONFIG_CMD_FAT=y
> > +CONFIG_CMD_FS_GENERIC=y
> > +# CONFIG_ISO_PARTITION is not set
> > +CONFIG_EFI_PARTITION=y
> > +# CONFIG_SPL_EFI_PARTITION is not set
> > +CONFIG_ENV_IS_IN_SPI_FLASH=y
> > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> > +CONFIG_NET_RANDOM_ETHADDR=y
> > +CONFIG_GPIO_HOG=y
> > +# CONFIG_INPUT is not set
> > +CONFIG_MMC=y
> > +CONFIG_DM_MMC=y
> > +# CONFIG_MMC_QUIRKS is not set
> > +# CONFIG_MMC_HW_PARTITIONING is not set
> > +CONFIG_MMC_MTK=y
> > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
> > +CONFIG_SPI_FLASH_EON=y
> > +CONFIG_SPI_FLASH_GIGADEVICE=y
> > +CONFIG_SPI_FLASH_ISSI=y
> > +CONFIG_SPI_FLASH_MACRONIX=y
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_SPI_FLASH_WINBOND=y
> > +CONFIG_SPI_FLASH_XMC=y
> > +CONFIG_MT7620_ETH=y
> > +CONFIG_PHY=y
> > +CONFIG_MT7620_USB_PHY=y
> > +CONFIG_DEBUG_UART_SHIFT=2
> > +CONFIG_SPI=y
> > +CONFIG_MT7620_SPI=y
> > +CONFIG_USB=y
> > +CONFIG_DM_USB=y
> > +CONFIG_USB_EHCI_HCD=y
> > +CONFIG_USB_EHCI_GENERIC=y
> > +CONFIG_LZMA=y
> > +CONFIG_SPL_LZMA=y
> > --
> > 2.17.1