[PATCH 01/15] gpio: mpc8xxx_gpio: fix a bug on ls1046ardb

classic Classic list List threaded Threaded
16 messages Options
Reply | Threaded
Open this post in threaded view
|

[PATCH 01/15] gpio: mpc8xxx_gpio: fix a bug on ls1046ardb

Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Fix a bug as belows,
=> gpio status -a
"Synchronous Abort" handler, esr 0x96000061
elr: 0000000082047964 lr : 0000000082047960 (reloc)
elr: 00000000fbd72964 lr : 00000000fbd72960
x0 : 00000000ffffffff x1 : 000000000000000a
x2 : 0000000000000020 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 0000000000000030
x6 : 0000000000000020 x7 : 0000000000000002
x8 : 00000000ffffffe0 x9 : 0000000000000008
x10: 0000000000000010 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000000230
x14: 00000000fbc23e9c x15: 00000000ffffffff
...
reseting

Signed-off-by: Biwen Li <[hidden email]>
---
 .../asm/arch-fsl-layerscape/immap_lsch3.h     | 10 +++++
 drivers/gpio/mpc8xxx_gpio.c                   | 45 +++----------------
 2 files changed, 17 insertions(+), 38 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index baa9fa8529..3d02004036 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -589,5 +589,15 @@ struct ccsr_serdes {
  u8 res5[0x19fc - 0xa00];
 };
 
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+ u32 gpibe;
+};
+
 #endif /*__ASSEMBLY__ */
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 27881a7322..e7fc45d4f5 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -16,16 +16,6 @@
 #include <asm/io.h>
 #include <dm/of_access.h>
 
-struct ccsr_gpio {
- u32 gpdir;
- u32 gpodr;
- u32 gpdat;
- u32 gpier;
- u32 gpimr;
- u32 gpicr;
- u32 gpibe;
-};
-
 struct mpc8xxx_gpio_data {
  /* The bank's register base in memory */
  struct ccsr_gpio __iomem *base;
@@ -187,32 +177,11 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
 {
  struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
  struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
- fdt_addr_t addr;
- u32 i;
- u32 reg[4];
 
- if (ofnode_read_bool(dev->node, "little-endian"))
+ if (dev_read_bool(dev, "little-endian"))
  data->little_endian = true;
 
- if (data->little_endian)
- dev_read_u32_array(dev, "reg", reg, 4);
- else
- dev_read_u32_array(dev, "reg", reg, 2);
-
- if (data->little_endian) {
- for (i = 0; i < 2; i++)
- reg[i] = be32_to_cpu(reg[i]);
- }
-
- addr = dev_translate_address(dev, reg);
-
- plat->addr = addr;
-
- if (data->little_endian)
- plat->size = reg[3];
- else
- plat->size = reg[1];
-
+ plat->addr = (ulong)dev_read_addr_size_index(dev, 0 , (fdt_size_t *)&plat->size);
  plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
 
  return 0;
@@ -257,11 +226,11 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
  if (!str)
  return -ENOMEM;
 
- if (ofnode_device_is_compatible(dev->node, "fsl,qoriq-gpio")) {
- unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio)
- - sizeof(u32);
-
- out_be32((unsigned int *)gpibe, 0xffffffff);
+ if (device_is_compatible(dev, "fsl,qoriq-gpio")) {
+ if (data->little_endian)
+ out_le32(&data->base->gpibe, 0xffffffff);
+ else
+ out_be32(&data->base->gpibe, 0xffffffff);
  }
 
  uc_priv->bank_name = str;
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 02/15] arm: dts: ls1021a: add gpio node

Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Add gpio node for SoC LS1021A

Signed-off-by: Biwen Li <[hidden email]>
---
 arch/arm/dts/ls1021a.dtsi | 40 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 0eeec43ccc..7b99ce02b3 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -98,6 +98,46 @@
  bus-width = <4>;
  };
 
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
  scfg: scfg@1570000 {
  compatible = "fsl,ls1021a-scfg", "syscon";
  reg = <0x1570000 0x10000>;
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 03/15] arm64: dts: ls1012a: add gpio node

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Add gpio node for SoC LS1012A

Signed-off-by: Biwen Li <[hidden email]>
---
 arch/arm/dts/fsl-ls1012a.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 2d70c82a72..b1a616ed84 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -70,6 +70,26 @@
  bus-width = <4>;
  };
 
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
  i2c0: i2c@2180000 {
  compatible = "fsl,vf610-i2c";
  #address-cells = <1>;
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 04/15] arm64: dts: ls1028a: add gpio node

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Add gpio node for SoC LS1028A

Signed-off-by: Biwen Li <[hidden email]>
---
 arch/arm/dts/fsl-ls1028a.dtsi | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index bf6373d5ec..64e75c637d 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -380,6 +380,39 @@
  status = "disabled";
  };
 
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+ };
+
  sata: sata@3200000 {
  compatible = "fsl,ls1028a-ahci";
  reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 05/15] arm64: dts: ls1043a: add gpio node

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Add gpio node for SoC LS1043A

Signed-off-by: Biwen Li <[hidden email]>
---
 arch/arm/dts/fsl-ls1043a.dtsi | 40 +++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index f7db44c0fa..96286104f2 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -78,6 +78,46 @@
  bus-width = <4>;
  };
 
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
  ifc: ifc@1530000 {
  compatible = "fsl,ifc", "simple-bus";
  reg = <0x0 0x1530000 0x0 0x10000>;
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 06/15] arm64: dts: ls1046a: add gpio node

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Add gpio node for SoC LS1046A

Signed-off-by: Biwen Li <[hidden email]>
---
 arch/arm/dts/fsl-ls1046a.dtsi | 40 +++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 3f11d6cd18..bffa6d1469 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -78,6 +78,46 @@
  bus-width = <4>;
  };
 
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 66 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 67 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 68 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 134 4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
  ifc: ifc@1530000 {
  compatible = "fsl,ifc", "simple-bus";
  reg = <0x0 0x1530000 0x0 0x10000>;
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 07/15] arm64: dts: ls1088a: add gpio node

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Add gpio node for SoC LS1088A

Signed-off-by: Biwen Li <[hidden email]>
---
 arch/arm/dts/fsl-ls1088a.dtsi | 46 +++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index 6653794d1c..3e5b310437 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -3,7 +3,9 @@
  * NXP ls1088a SOC common device tree source
  *
  * Copyright 2017 NXP
+ * Copyright 2020 NXP
  */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
  compatible = "fsl,ls1088a";
@@ -115,6 +117,50 @@
  bus-width = <4>;
  };
 
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
  ifc: ifc@1530000 {
  compatible = "fsl,ifc", "simple-bus";
  reg = <0x0 0x2240000 0x0 0x20000>;
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 08/15] arm64: dts: ls208xa: add gpio node

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Add gpio node for SoC LS208xA

Signed-off-by: Biwen Li <[hidden email]>
---
 arch/arm/dts/fsl-ls2080a.dtsi | 45 +++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 6b7bf8eb16..155caf4721 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -3,6 +3,7 @@
  * Freescale ls2080a SOC common device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 / {
@@ -119,6 +120,50 @@
  bus-width = <4>;
  };
 
+ gpio0: gpio@2300000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
  usb0: usb3@3100000 {
  compatible = "fsl,layerscape-dwc3";
  reg = <0x0 0x3100000 0x0 0x10000>;
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 09/15] configs: ls1012a: enable CONFIG_MPC8XXX_GPIO

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Enable CONFIG_MPC8XXX_GPIO for SoC LS1012A

Signed-off-by: Biwen Li <[hidden email]>
---
 include/configs/ls1012a_common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 6cf6a31d76..5105f00992 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -62,6 +62,16 @@
 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
 #endif
 
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#ifndef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
+#endif
+#endif
+
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 10/15] configs: ls1043a: enable CONFIG_MPC8XXX_GPIO

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Enable CONFIG_MPC8XXX_GPIO for SoC LS1043A

Signed-off-by: Biwen Li <[hidden email]>
---
 include/configs/ls1043a_common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 96fdd6417e..76252a5c67 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -119,6 +119,16 @@
 
 #endif
 
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#ifndef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
+#endif
+#endif
+
 /* IFC */
 #ifndef SPL_NO_IFC
 #if defined(CONFIG_TFABOOT) || \
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 11/15] configs: ls1028a: enable CONFIG_MPC8XXX_GPIO

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Enable CONFIG_MPC8XXX_GPIO for SoC LS1028A

Signed-off-by: Biwen Li <[hidden email]>
---
 include/configs/ls1028a_common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 8345cd7acf..c89e7b5f3d 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -36,6 +36,16 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
 
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#ifndef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
+#endif
+#endif
+
 /* I2C */
 #ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 12/15] configs: ls1088a: enable CONFIG_MPC8XXX_GPIO

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Enable CONFIG_MPC8XXX_GPIO for LS1088A

Signed-off-by: Biwen Li <[hidden email]>
---
 include/configs/ls1088a_common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index f9e349871c..4ef840d89e 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -53,6 +53,16 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
 
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#ifndef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
+#endif
+#endif
+
 /* I2C */
 #ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 13/15] configs: ls208xa: enable CONFIG_MPC8XXX_GPIO

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Enable CONFIG_MPC8XXX_GPIO for LS208xA

Signed-off-by: Biwen Li <[hidden email]>
---
 include/configs/ls2080a_common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 444bb8c3b5..3631418f29 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -66,6 +66,16 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
 
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#ifndef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
+#endif
+#endif
+
 /* I2C */
 #ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 14/15] configs: lx2160a: enable CONFIG_MPC8XXX_GPIO

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Enable CONFIG_MPC8XXX_GPIO for SoC LX2160A

Signed-off-by: Biwen Li <[hidden email]>
---
 include/configs/lx2160a_common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 0017ac5773..fe79d91f33 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -158,6 +158,16 @@
 #define NXP_FSPI_FLASH_NUM 1
 #endif
 
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#ifndef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
+#endif
+#endif
+
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
 unsigned long get_board_ddr_clk(void);
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

[PATCH 15/15] configs: ls1046a: enable MPC8XXX_GPIO

Biwen Li (OSS)
In reply to this post by Biwen Li (OSS)
From: Biwen Li <[hidden email]>

Enable MPC8XXX_GPIO for SoC LS1046A

Signed-off-by: Biwen Li <[hidden email]>
---
 include/configs/ls1046a_common.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index d44a7f105e..06b4d91676 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -126,6 +126,16 @@
 #define CONFIG_SYS_MONITOR_LEN 0xa0000
 #endif
 
+/* GPIO */
+#ifdef CONFIG_DM_GPIO
+#ifndef CONFIG_MPC8XXX_GPIO
+#define CONFIG_MPC8XXX_GPIO
+#endif
+#ifndef CONFIG_CMD_GPIO
+#define CONFIG_CMD_GPIO
+#endif
+#endif
+
 /* I2C */
 #ifndef CONFIG_DM_I2C
 #define CONFIG_SYS_I2C
--
2.17.1

Reply | Threaded
Open this post in threaded view
|

RE: [PATCH 01/15] gpio: mpc8xxx_gpio: fix a bug on ls1046ardb

Biwen Li
In reply to this post by Biwen Li (OSS)
Hi Priyanka,

These patches depend on the patch("[V3] gpio: mpc8xxx: support fsl-layerscape platform"
, https://patchwork.ozlabs.org/project/uboot/patch/20200924134050.8618-1-hui.song_1@.../),

Best Regads,
Biwen Li

> To: Priyanka Jain <[hidden email]>
> Cc: Jiafei Pan <[hidden email]>; [hidden email]; Xiaobo Xie
> <[hidden email]>; Biwen Li <[hidden email]>
> Subject: [PATCH 01/15] gpio: mpc8xxx_gpio: fix a bug on ls1046ardb
>
> From: Biwen Li <[hidden email]>
>
> Fix a bug as belows,
> => gpio status -a
> "Synchronous Abort" handler, esr 0x96000061
> elr: 0000000082047964 lr : 0000000082047960 (reloc)
> elr: 00000000fbd72964 lr : 00000000fbd72960
> x0 : 00000000ffffffff x1 : 000000000000000a
> x2 : 0000000000000020 x3 : 0000000000000001
> x4 : 0000000000000000 x5 : 0000000000000030
> x6 : 0000000000000020 x7 : 0000000000000002
> x8 : 00000000ffffffe0 x9 : 0000000000000008
> x10: 0000000000000010 x11: 0000000000000006
> x12: 000000000001869f x13: 0000000000000230
> x14: 00000000fbc23e9c x15: 00000000ffffffff ...
> reseting
>
> Signed-off-by: Biwen Li <[hidden email]>
> ---
>  .../asm/arch-fsl-layerscape/immap_lsch3.h     | 10 +++++
>  drivers/gpio/mpc8xxx_gpio.c                   | 45 +++----------------
>  2 files changed, 17 insertions(+), 38 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index baa9fa8529..3d02004036 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -589,5 +589,15 @@ struct ccsr_serdes {
>   u8 res5[0x19fc - 0xa00];
>  };
>
> +struct ccsr_gpio {
> + u32 gpdir;
> + u32 gpodr;
> + u32 gpdat;
> + u32 gpier;
> + u32 gpimr;
> + u32 gpicr;
> + u32 gpibe;
> +};
> +
>  #endif /*__ASSEMBLY__ */
>  #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
> diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index
> 27881a7322..e7fc45d4f5 100644
> --- a/drivers/gpio/mpc8xxx_gpio.c
> +++ b/drivers/gpio/mpc8xxx_gpio.c
> @@ -16,16 +16,6 @@
>  #include <asm/io.h>
>  #include <dm/of_access.h>
>
> -struct ccsr_gpio {
> - u32 gpdir;
> - u32 gpodr;
> - u32 gpdat;
> - u32 gpier;
> - u32 gpimr;
> - u32 gpicr;
> - u32 gpibe;
> -};
> -
>  struct mpc8xxx_gpio_data {
>   /* The bank's register base in memory */
>   struct ccsr_gpio __iomem *base;
> @@ -187,32 +177,11 @@ static int mpc8xxx_gpio_ofdata_to_platdata(struct
> udevice *dev)  {
>   struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
>   struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
> - fdt_addr_t addr;
> - u32 i;
> - u32 reg[4];
>
> - if (ofnode_read_bool(dev->node, "little-endian"))
> + if (dev_read_bool(dev, "little-endian"))
>   data->little_endian = true;
>
> - if (data->little_endian)
> - dev_read_u32_array(dev, "reg", reg, 4);
> - else
> - dev_read_u32_array(dev, "reg", reg, 2);
> -
> - if (data->little_endian) {
> - for (i = 0; i < 2; i++)
> - reg[i] = be32_to_cpu(reg[i]);
> - }
> -
> - addr = dev_translate_address(dev, reg);
> -
> - plat->addr = addr;
> -
> - if (data->little_endian)
> - plat->size = reg[3];
> - else
> - plat->size = reg[1];
> -
> + plat->addr = (ulong)dev_read_addr_size_index(dev, 0 , (fdt_size_t
> +*)&plat->size);
>   plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
>
>   return 0;
> @@ -257,11 +226,11 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
>   if (!str)
>   return -ENOMEM;
>
> - if (ofnode_device_is_compatible(dev->node, "fsl,qoriq-gpio")) {
> - unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio)
> - - sizeof(u32);
> -
> - out_be32((unsigned int *)gpibe, 0xffffffff);
> + if (device_is_compatible(dev, "fsl,qoriq-gpio")) {
> + if (data->little_endian)
> + out_le32(&data->base->gpibe, 0xffffffff);
> + else
> + out_be32(&data->base->gpibe, 0xffffffff);
>   }
>
>   uc_priv->bank_name = str;
> --
> 2.17.1