[PATCH 0/6] mmc: fsl_esdhc: add ADMA2 support

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[PATCH 0/6] mmc: fsl_esdhc: add ADMA2 support

Michael Walle-2
Add ADMA2 support mainly because it supports 64bit DMA addresses. These are
for example used if you use EFI on a LS1028A board which has more than 2GB
of RAM, because only the lower 2GB are mapped into the lower 32bit address
space.

Patches 1-4 clean the fsl_esdhc driver up. Patch 5 moves ADMA2 table
handling code out of the sdhci core code. Patch 6 finally adds the ADMA2
support to the fsl_esdhc driver.

This was tested on a custom board LS1028A board.

A passing travis-ci build is available at:
  https://travis-ci.org/github/mwalle/u-boot/builds/729431087

Michael Walle (6):
  mmc: fsl_esdhc: simplify 64bit check for SDMA transfers
  mmc: fsl_esdhc: use dma-mapping API
  mmc: fsl_esdhc: simplify esdhc_setup_data()
  mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()
  mmc: sdhci: move the ADMA2 table handling into own module
  mmc: fsl_esdhc: add ADMA2 support

 drivers/mmc/Kconfig      |  13 ++
 drivers/mmc/Makefile     |   1 +
 drivers/mmc/fsl_esdhc.c  | 267 ++++++++++++++++++++-------------------
 drivers/mmc/sdhci-adma.c |  73 +++++++++++
 drivers/mmc/sdhci.c      |  63 ++-------
 include/fsl_esdhc.h      |  14 ++
 include/sdhci.h          |   8 +-
 7 files changed, 252 insertions(+), 187 deletions(-)
 create mode 100644 drivers/mmc/sdhci-adma.c

--
2.20.1

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[PATCH 1/6] mmc: fsl_esdhc: simplify 64bit check for SDMA transfers

Michael Walle-2
SDMA can only do DMA with 32 bit addresses. This is true for all
architectures (just doesn't apply to 32 bit ones). Simplify the code and
remove unnecessary CONFIG_FSL_LAYERSCAPE.

Also make the error message more concise.

Signed-off-by: Michael Walle <[hidden email]>
---
 drivers/mmc/fsl_esdhc.c | 29 ++++++-----------------------
 1 file changed, 6 insertions(+), 23 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index de9fe01bc5..3ac4c76e22 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -202,9 +202,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 {
  int timeout;
  struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE)
  dma_addr_t addr;
-#endif
  uint wml_value;
 
  wml_value = data->blocksize/4;
@@ -215,15 +213,10 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 
  esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE)
  addr = virt_to_phys((void *)(data->dest));
  if (upper_32_bits(addr))
- printf("Error found for upper 32 bits\n");
- else
- esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
-#else
- esdhc_write32(&regs->dsaddr, (u32)data->dest);
-#endif
+ printf("Cannot use 64 bit addresses with SDMA\n");
+ esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 #endif
  } else {
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
@@ -242,15 +235,10 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE)
  addr = virt_to_phys((void *)(data->src));
  if (upper_32_bits(addr))
- printf("Error found for upper 32 bits\n");
- else
- esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
-#else
- esdhc_write32(&regs->dsaddr, (u32)data->src);
-#endif
+ printf("Cannot use 64 bit addresses with SDMA\n");
+ esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
 #endif
  }
 
@@ -307,17 +295,12 @@ static void check_and_invalidate_dcache_range
  unsigned end = 0;
  unsigned size = roundup(ARCH_DMA_MINALIGN,
  data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE)
  dma_addr_t addr;
 
  addr = virt_to_phys((void *)(data->dest));
  if (upper_32_bits(addr))
- printf("Error found for upper 32 bits\n");
- else
- start = lower_32_bits(addr);
-#else
- start = (unsigned)data->dest;
-#endif
+ printf("Cannot use 64 bit addresses with SDMA\n");
+ start = lower_32_bits(addr);
  end = start + size;
  invalidate_dcache_range(start, end);
 }
--
2.20.1

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[PATCH 2/6] mmc: fsl_esdhc: use dma-mapping API

Michael Walle-2
In reply to this post by Michael Walle-2
Use the dma_{map,unmap}_single() calls. These will take care of the
flushing and invalidation of caches.

Signed-off-by: Michael Walle <[hidden email]>
---
 drivers/mmc/fsl_esdhc.c | 49 ++++++++++++-----------------------------
 1 file changed, 14 insertions(+), 35 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3ac4c76e22..f5624371ce 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -26,6 +26,7 @@
 #include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -91,6 +92,7 @@ struct fsl_esdhc_priv {
  struct mmc *mmc;
 #endif
  struct udevice *dev;
+ dma_addr_t dma_addr;
 };
 
 /* Return the XFERTYP flags for a given command and data packet */
@@ -201,8 +203,8 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
     struct mmc_data *data)
 {
  int timeout;
+ uint trans_bytes = data->blocksize * data->blocks;
  struct fsl_esdhc *regs = priv->esdhc_regs;
- dma_addr_t addr;
  uint wml_value;
 
  wml_value = data->blocksize/4;
@@ -213,17 +215,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 
  esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
- addr = virt_to_phys((void *)(data->dest));
- if (upper_32_bits(addr))
+ priv->dma_addr = dma_map_single(data->dest, trans_bytes,
+ mmc_get_dma_dir(data));
+ if (upper_32_bits(priv->dma_addr))
  printf("Cannot use 64 bit addresses with SDMA\n");
- esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+ esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
 #endif
  } else {
-#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
- flush_dcache_range((ulong)data->src,
-   (ulong)data->src+data->blocks
- *data->blocksize);
-#endif
  if (wml_value > WML_WR_WML_MAX)
  wml_value = WML_WR_WML_MAX_VAL;
 
@@ -235,10 +233,11 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
- addr = virt_to_phys((void *)(data->src));
- if (upper_32_bits(addr))
+ priv->dma_addr = dma_map_single((void *)data->src, trans_bytes,
+ mmc_get_dma_dir(data));
+ if (upper_32_bits(priv->dma_addr))
  printf("Cannot use 64 bit addresses with SDMA\n");
- esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+ esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
 #endif
  }
 
@@ -288,23 +287,6 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  return 0;
 }
 
-static void check_and_invalidate_dcache_range
- (struct mmc_cmd *cmd,
- struct mmc_data *data) {
- unsigned start = 0;
- unsigned end = 0;
- unsigned size = roundup(ARCH_DMA_MINALIGN,
- data->blocks*data->blocksize);
- dma_addr_t addr;
-
- addr = virt_to_phys((void *)(data->dest));
- if (upper_32_bits(addr))
- printf("Cannot use 64 bit addresses with SDMA\n");
- start = lower_32_bits(addr);
- end = start + size;
- invalidate_dcache_range(start, end);
-}
-
 /*
  * Sends a command out on the bus.  Takes the mmc pointer,
  * a command pointer, and an optional data pointer.
@@ -348,9 +330,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  err = esdhc_setup_data(priv, mmc, data);
  if(err)
  return err;
-
- if (data->flags & MMC_DATA_READ)
- check_and_invalidate_dcache_range(cmd, data);
  }
 
  /* Figure out the transfer arguments */
@@ -441,9 +420,9 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  * cache-fill during the DMA operations such as the
  * speculative pre-fetching etc.
  */
- if (data->flags & MMC_DATA_READ) {
- check_and_invalidate_dcache_range(cmd, data);
- }
+ dma_unmap_single(priv->dma_addr,
+ data->blocks * data->blocksize,
+ mmc_get_dma_dir(data));
 #endif
  }
 
--
2.20.1

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[PATCH 3/6] mmc: fsl_esdhc: simplify esdhc_setup_data()

Michael Walle-2
In reply to this post by Michael Walle-2
First, we need the waterlevel setting for PIO mode only. Secondy, both DMA
setup code is identical for both directions, except for the data pointer.
Thus, unify them.

Signed-off-by: Michael Walle <[hidden email]>
---
 drivers/mmc/fsl_esdhc.c | 69 +++++++++++++++++++++++++----------------
 1 file changed, 42 insertions(+), 27 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index f5624371ce..0f9eea86d5 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -199,49 +199,64 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
 }
 #endif
 
-static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
-    struct mmc_data *data)
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
+ struct mmc_data *data)
 {
- int timeout;
- uint trans_bytes = data->blocksize * data->blocks;
  struct fsl_esdhc *regs = priv->esdhc_regs;
- uint wml_value;
-
- wml_value = data->blocksize/4;
+ uint wml_value = data->blocksize / 4;
 
  if (data->flags & MMC_DATA_READ) {
  if (wml_value > WML_RD_WML_MAX)
  wml_value = WML_RD_WML_MAX_VAL;
 
  esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
-#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
- priv->dma_addr = dma_map_single(data->dest, trans_bytes,
- mmc_get_dma_dir(data));
- if (upper_32_bits(priv->dma_addr))
- printf("Cannot use 64 bit addresses with SDMA\n");
- esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
-#endif
  } else {
  if (wml_value > WML_WR_WML_MAX)
  wml_value = WML_WR_WML_MAX_VAL;
 
- if (!(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
- printf("Can not write to locked SD card.\n");
- return -EINVAL;
- }
-
  esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
- wml_value << 16);
-#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
- priv->dma_addr = dma_map_single((void *)data->src, trans_bytes,
- mmc_get_dma_dir(data));
- if (upper_32_bits(priv->dma_addr))
- printf("Cannot use 64 bit addresses with SDMA\n");
- esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
-#endif
+   wml_value << 16);
  }
+}
+#endif
+
+static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
+{
+ uint trans_bytes = data->blocksize * data->blocks;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+ void *buf;
+
+ if (data->flags & MMC_DATA_WRITE)
+ buf = (void *)data->src;
+ else
+ buf = data->dest;
 
+ priv->dma_addr = dma_map_single(buf, trans_bytes,
+ mmc_get_dma_dir(data));
+ if (upper_32_bits(priv->dma_addr))
+ printf("Cannot use 64 bit addresses with SDMA\n");
+ esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
  esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
+}
+
+static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+    struct mmc_data *data)
+{
+ int timeout;
+ bool is_write = data->flags & MMC_DATA_WRITE;
+ struct fsl_esdhc *regs = priv->esdhc_regs;
+
+ if (is_write && !(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
+ printf("Can not write to locked SD card.\n");
+ return -EINVAL;
+ }
+
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ esdhc_setup_watermark_level(priv, data);
+#else
+ esdhc_setup_dma(priv, data);
+#endif
 
  /* Calculate the timeout period for data transactions */
  /*
--
2.20.1

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[PATCH 4/6] mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()

Michael Walle-2
In reply to this post by Michael Walle-2
Make the code cleaner and drop the old-style #ifdef constructs where it is
possible.

Signed-off-by: Michael Walle <[hidden email]>
---
 drivers/mmc/fsl_esdhc.c | 128 +++++++++++++++++++---------------------
 1 file changed, 60 insertions(+), 68 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0f9eea86d5..c4acfe10dc 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -102,15 +102,13 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 
  if (data) {
  xfertyp |= XFERTYP_DPSEL;
-#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
- xfertyp |= XFERTYP_DMAEN;
-#endif
+ if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
+ xfertyp |= XFERTYP_DMAEN;
  if (data->blocks > 1) {
  xfertyp |= XFERTYP_MSBSEL;
  xfertyp |= XFERTYP_BCEN;
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
- xfertyp |= XFERTYP_AC12EN;
-#endif
+ if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
+ xfertyp |= XFERTYP_AC12EN;
  }
 
  if (data->flags & MMC_DATA_READ)
@@ -134,7 +132,6 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
-#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 /*
  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  */
@@ -197,9 +194,7 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  }
  }
 }
-#endif
 
-#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
  struct mmc_data *data)
 {
@@ -219,7 +214,6 @@ static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
    wml_value << 16);
  }
 }
-#endif
 
 static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
 {
@@ -252,11 +246,10 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  return -EINVAL;
  }
 
-#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
- esdhc_setup_watermark_level(priv, data);
-#else
- esdhc_setup_dma(priv, data);
-#endif
+ if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
+ esdhc_setup_watermark_level(priv, data);
+ else
+ esdhc_setup_dma(priv, data);
 
  /* Calculate the timeout period for data transactions */
  /*
@@ -289,14 +282,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  if (timeout < 0)
  timeout = 0;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
- if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+ if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
+    (timeout == 4 || timeout == 8 || timeout == 12))
  timeout++;
-#endif
 
-#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
- timeout = 0xE;
-#endif
+ if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
+ timeout = 0xE;
+
  esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
 
  return 0;
@@ -316,10 +308,9 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  struct fsl_esdhc *regs = priv->esdhc_regs;
  unsigned long start;
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
- if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
+    cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  return 0;
-#endif
 
  esdhc_write32(&regs->irqstat, -1);
 
@@ -413,32 +404,32 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 
  /* Wait until all of the blocks are transferred */
  if (data) {
-#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
- esdhc_pio_read_write(priv, data);
-#else
- do {
- irqstat = esdhc_read32(&regs->irqstat);
+ if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
+ esdhc_pio_read_write(priv, data);
+ } else {
+ do {
+ irqstat = esdhc_read32(&regs->irqstat);
 
- if (irqstat & IRQSTAT_DTOE) {
- err = -ETIMEDOUT;
- goto out;
- }
+ if (irqstat & IRQSTAT_DTOE) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
 
- if (irqstat & DATA_ERR) {
- err = -ECOMM;
- goto out;
- }
- } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
-
- /*
- * Need invalidate the dcache here again to avoid any
- * cache-fill during the DMA operations such as the
- * speculative pre-fetching etc.
- */
- dma_unmap_single(priv->dma_addr,
- data->blocks * data->blocksize,
- mmc_get_dma_dir(data));
-#endif
+ if (irqstat & DATA_ERR) {
+ err = -ECOMM;
+ goto out;
+ }
+ } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
+
+ /*
+ * Need invalidate the dcache here again to avoid any
+ * cache-fill during the DMA operations such as the
+ * speculative pre-fetching etc.
+ */
+ dma_unmap_single(priv->dma_addr,
+ data->blocks * data->blocksize,
+ mmc_get_dma_dir(data));
+ }
  }
 
 out:
@@ -625,12 +616,10 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
  u32 caps;
 
  caps = esdhc_read32(&regs->hostcapblt);
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
- caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
-#endif
-#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
- caps |= HOSTCAPBLT_VS33;
-#endif
+ if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
+ caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
+ if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
+ caps |= HOSTCAPBLT_VS33;
  if (caps & HOSTCAPBLT_VS18)
  cfg->voltages |= MMC_VDD_165_195;
  if (caps & HOSTCAPBLT_VS30)
@@ -651,19 +640,18 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
 #ifdef CONFIG_OF_LIBFDT
 __weak int esdhc_status_fixup(void *blob, const char *compat)
 {
-#ifdef CONFIG_FSL_ESDHC_PIN_MUX
- if (!hwconfig("esdhc")) {
+ if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
  do_fixup_by_compat(blob, compat, "status", "disabled",
  sizeof("disabled"), 1);
  return 1;
  }
-#endif
+
  return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
-static int fsl_esdhc_get_cd(struct udevice *dev);
 
+#if CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_get_cd(struct udevice *dev);
 static void esdhc_disable_for_no_card(void *blob)
 {
  struct udevice *dev;
@@ -682,6 +670,10 @@ static void esdhc_disable_for_no_card(void *blob)
  sizeof("disabled"), 1);
  }
 }
+#else
+static void esdhc_disable_for_no_card(void *blob)
+{
+}
 #endif
 
 void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
@@ -690,9 +682,10 @@ void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
 
  if (esdhc_status_fixup(blob, compat))
  return;
-#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
- esdhc_disable_for_no_card(blob);
-#endif
+
+ if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
+ esdhc_disable_for_no_card(blob);
+
  do_fixup_by_compat_u32(blob, compat, "clock-frequency",
        gd->arch.sdhc_clk, 1);
 }
@@ -774,10 +767,9 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
  printf("No max bus width provided. Assume 8-bit supported.\n");
  }
 
-#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
- if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+ if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
  mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
-#endif
+
  mmc_cfg->ops = &esdhc_ops;
 
  fsl_esdhc_get_cfg_common(priv, mmc_cfg);
@@ -849,10 +841,10 @@ static int fsl_esdhc_probe(struct udevice *dev)
  if (ret)
  return ret;
 
-#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
- if (!fsl_esdhc_get_cd(dev))
+ if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
+    !fsl_esdhc_get_cd(dev))
  esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
-#endif
+
  return 0;
 }
 
--
2.20.1

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[PATCH 5/6] mmc: sdhci: move the ADMA2 table handling into own module

Michael Walle-2
In reply to this post by Michael Walle-2
There are other (non-SDHCI) controllers which supports ADMA2 descriptor
tables, namely the Freescale eSDHC. Instead of copying the code, move it
into an own module.

Signed-off-by: Michael Walle <[hidden email]>
---
 drivers/mmc/Kconfig      |  5 +++
 drivers/mmc/Makefile     |  1 +
 drivers/mmc/sdhci-adma.c | 73 ++++++++++++++++++++++++++++++++++++++++
 drivers/mmc/sdhci.c      | 63 +++++-----------------------------
 include/sdhci.h          |  8 +++--
 5 files changed, 92 insertions(+), 58 deletions(-)
 create mode 100644 drivers/mmc/sdhci-adma.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0c252e34c7..88582db58c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -46,6 +46,9 @@ config SPL_DM_MMC
 
 if MMC
 
+config MMC_SDHCI_ADMA_HELPERS
+ bool
+
 config MMC_SPI
  bool "Support for SPI-based MMC controller"
  depends on DM_MMC && DM_SPI
@@ -445,6 +448,7 @@ config MMC_SDHCI_SDMA
 config MMC_SDHCI_ADMA
  bool "Support SDHCI ADMA2"
  depends on MMC_SDHCI
+ select MMC_SDHCI_ADMA_HELPERS
  help
   This enables support for the ADMA (Advanced DMA) defined
   in the SD Host Controller Standard Specification Version 3.00
@@ -452,6 +456,7 @@ config MMC_SDHCI_ADMA
 config SPL_MMC_SDHCI_ADMA
  bool "Support SDHCI ADMA2 in SPL"
  depends on MMC_SDHCI
+ select MMC_SDHCI_ADMA_HELPERS
  help
   This enables support for the ADMA (Advanced DMA) defined
   in the SD Host Controller Standard Specification Version 3.00 in SPL.
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 22266ec8ec..1c849cbab2 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -6,6 +6,7 @@
 obj-y += mmc.o
 obj-$(CONFIG_$(SPL_)DM_MMC) += mmc-uclass.o
 obj-$(CONFIG_$(SPL_)MMC_WRITE) += mmc_write.o
+obj-$(CONFIG_MMC_SDHCI_ADMA_HELPERS) += sdhci-adma.o
 
 ifndef CONFIG_$(SPL_)BLK
 obj-y += mmc_legacy.o
diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c
new file mode 100644
index 0000000000..2ec057fbb1
--- /dev/null
+++ b/drivers/mmc/sdhci-adma.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SDHCI ADMA2 helper functions.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <sdhci.h>
+#include <malloc.h>
+#include <asm/cache.h>
+
+static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
+    dma_addr_t addr, u16 len, bool end)
+{
+ u8 attr;
+
+ attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
+ if (end)
+ attr |= ADMA_DESC_ATTR_END;
+
+ desc->attr = attr;
+ desc->len = len;
+ desc->reserved = 0;
+ desc->addr_lo = lower_32_bits(addr);
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+ desc->addr_hi = upper_32_bits(addr);
+#endif
+}
+
+/**
+ * sdhci_prepare_adma_table() - Populate the ADMA table
+ *
+ * @table: Pointer to the ADMA table
+ * @data: Pointer to MMC data
+ * @addr: DMA address to write to or read from
+ *
+ * Fill the ADMA table according to the MMC data to read from or write to the
+ * given DMA address.
+ * Please note, that the table size depends on CONFIG_SYS_MMC_MAX_BLK_COUNT and
+ * we don't have to check for overflow.
+ */
+void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
+      struct mmc_data *data, dma_addr_t addr)
+{
+ uint trans_bytes = data->blocksize * data->blocks;
+ uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
+ struct sdhci_adma_desc *desc = table;
+ int i = desc_count;
+
+ while (--i) {
+ sdhci_adma_desc(desc, addr, ADMA_MAX_LEN, false);
+ addr += ADMA_MAX_LEN;
+ trans_bytes -= ADMA_MAX_LEN;
+ desc++;
+ }
+
+ sdhci_adma_desc(desc, addr, trans_bytes, true);
+
+ flush_cache((dma_addr_t)table,
+    ROUND(desc_count * sizeof(struct sdhci_adma_desc),
+  ARCH_DMA_MINALIGN));
+}
+
+/**
+ * sdhci_adma_init() - initialize the ADMA descriptor table
+ *
+ * @return pointer to the allocated descriptor table or NULL in case of an
+ * error.
+ */
+struct sdhci_adma_desc *sdhci_adma_init(void)
+{
+ return memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
+}
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 7673219fb3..d549a264d7 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -69,57 +69,6 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  }
 }
 
-#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
-static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
-    u16 len, bool end)
-{
- struct sdhci_adma_desc *desc;
- u8 attr;
-
- desc = &host->adma_desc_table[host->desc_slot];
-
- attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
- if (!end)
- host->desc_slot++;
- else
- attr |= ADMA_DESC_ATTR_END;
-
- desc->attr = attr;
- desc->len = len;
- desc->reserved = 0;
- desc->addr_lo = lower_32_bits(dma_addr);
-#ifdef CONFIG_DMA_ADDR_T_64BIT
- desc->addr_hi = upper_32_bits(dma_addr);
-#endif
-}
-
-static void sdhci_prepare_adma_table(struct sdhci_host *host,
-     struct mmc_data *data)
-{
- uint trans_bytes = data->blocksize * data->blocks;
- uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
- int i = desc_count;
- dma_addr_t dma_addr = host->start_addr;
-
- host->desc_slot = 0;
-
- while (--i) {
- sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
- dma_addr += ADMA_MAX_LEN;
- trans_bytes -= ADMA_MAX_LEN;
- }
-
- sdhci_adma_desc(host, dma_addr, trans_bytes, true);
-
- flush_cache((dma_addr_t)host->adma_desc_table,
-    ROUND(desc_count * sizeof(struct sdhci_adma_desc),
-  ARCH_DMA_MINALIGN));
-}
-#elif defined(CONFIG_MMC_SDHCI_SDMA)
-static void sdhci_prepare_adma_table(struct sdhci_host *host,
-     struct mmc_data *data)
-{}
-#endif
 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
       int *is_aligned, int trans_bytes)
@@ -156,8 +105,11 @@ static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  if (host->flags & USE_SDMA) {
  sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
  SDHCI_DMA_ADDRESS);
- } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
- sdhci_prepare_adma_table(host, data);
+ }
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+ else if (host->flags & (USE_ADMA | USE_ADMA64)) {
+ sdhci_prepare_adma_table(host->adma_desc_table, data,
+ host->start_addr);
 
  sdhci_writel(host, lower_32_bits(host->adma_addr),
      SDHCI_ADMA_ADDRESS);
@@ -165,6 +117,7 @@ static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  sdhci_writel(host, upper_32_bits(host->adma_addr),
      SDHCI_ADMA_ADDRESS_HI);
  }
+#endif
 }
 #else
 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
@@ -770,9 +723,9 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
        __func__);
  return -EINVAL;
  }
- host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
-
+ host->adma_desc_table = sdhci_adma_init();
  host->adma_addr = (dma_addr_t)host->adma_desc_table;
+
 #ifdef CONFIG_DMA_ADDR_T_64BIT
  host->flags |= USE_ADMA64;
 #else
diff --git a/include/sdhci.h b/include/sdhci.h
index 94fc3ed56a..f69d5f81fb 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -271,7 +271,6 @@ struct sdhci_ops {
  int (*deferred_probe)(struct sdhci_host *host);
 };
 
-#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 #define ADMA_MAX_LEN 65532
 #ifdef CONFIG_DMA_ADDR_T_64BIT
 #define ADMA_DESC_LEN 16
@@ -302,7 +301,7 @@ struct sdhci_adma_desc {
  u32 addr_hi;
 #endif
 } __packed;
-#endif
+
 struct sdhci_host {
  const char *name;
  void *ioaddr;
@@ -334,7 +333,6 @@ struct sdhci_host {
  dma_addr_t adma_addr;
 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  struct sdhci_adma_desc *adma_desc_table;
- uint desc_slot;
 #endif
 };
 
@@ -496,4 +494,8 @@ extern const struct dm_mmc_ops sdhci_ops;
 #else
 #endif
 
+struct sdhci_adma_desc *sdhci_adma_init(void);
+void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
+      struct mmc_data *data, dma_addr_t addr);
+
 #endif /* __SDHCI_HW_H */
--
2.20.1

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[PATCH 6/6] mmc: fsl_esdhc: add ADMA2 support

Michael Walle-2
In reply to this post by Michael Walle-2
Newer eSDHC controllers support ADMA2 descriptor tables which support
64bit DMA addresses. One notable user of addresses in the upper memory
segment is the EFI loader.

If support is enabled, but the controller doesn't support ADMA2, we
will fall back to SDMA (and thus 32 bit DMA addresses only).

Signed-off-by: Michael Walle <[hidden email]>
---
 drivers/mmc/Kconfig     |  8 +++++++
 drivers/mmc/fsl_esdhc.c | 50 ++++++++++++++++++++++++++++++++++++-----
 include/fsl_esdhc.h     | 14 ++++++++++++
 3 files changed, 67 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 88582db58c..14d7913986 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -755,6 +755,14 @@ config FSL_ESDHC
   This selects support for the eSDHC (Enhanced Secure Digital Host
   Controller) found on numerous Freescale/NXP SoCs.
 
+config FSL_ESDHC_SUPPORT_ADMA2
+ bool "enable ADMA2 support"
+ depends on FSL_ESDHC
+ select MMC_SDHCI_ADMA_HELPERS
+ help
+  This enables support for the ADMA2 transfer mode. If supported by the
+  eSDHC it will allow 64bit DMA addresses.
+
 config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
  bool "enable eSDHC workaround for 3.3v IO reliability issue"
  depends on FSL_ESDHC && DM_MMC
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c4acfe10dc..5b6cedd7d7 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -27,6 +27,7 @@
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
+#include <sdhci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,8 +53,9 @@ struct fsl_esdhc {
  char    reserved1[8]; /* reserved */
  uint    fevt; /* Force event register */
  uint    admaes; /* ADMA error status register */
- uint    adsaddr; /* ADMA system address register */
- char    reserved2[160];
+ uint    adsaddrl; /* ADMA system address low register */
+ uint    adsaddrh; /* ADMA system address high register */
+ char    reserved2[156];
  uint    hostver; /* Host controller version register */
  char    reserved3[4]; /* reserved */
  uint    dmaerraddr; /* DMA error address register */
@@ -92,6 +94,7 @@ struct fsl_esdhc_priv {
  struct mmc *mmc;
 #endif
  struct udevice *dev;
+ struct sdhci_adma_desc *adma_desc_table;
  dma_addr_t dma_addr;
 };
 
@@ -219,6 +222,7 @@ static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
 {
  uint trans_bytes = data->blocksize * data->blocks;
  struct fsl_esdhc *regs = priv->esdhc_regs;
+ phys_addr_t adma_addr;
  void *buf;
 
  if (data->flags & MMC_DATA_WRITE)
@@ -228,9 +232,29 @@ static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
 
  priv->dma_addr = dma_map_single(buf, trans_bytes,
  mmc_get_dma_dir(data));
- if (upper_32_bits(priv->dma_addr))
- printf("Cannot use 64 bit addresses with SDMA\n");
- esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
+
+ if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
+    priv->adma_desc_table) {
+ debug("Using ADMA2\n");
+ /* prefer ADMA2 if it is available */
+ sdhci_prepare_adma_table(priv->adma_desc_table, data,
+ priv->dma_addr);
+
+ adma_addr = virt_to_phys(priv->adma_desc_table);
+ esdhc_write32(&regs->adsaddrl, lower_32_bits(adma_addr));
+ if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
+ esdhc_write32(&regs->adsaddrh, upper_32_bits(adma_addr));
+ esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
+   PROCTL_DMAS_ADMA2);
+ } else {
+ debug("Using SDMA\n");
+ if (upper_32_bits(priv->dma_addr))
+ printf("Cannot use 64 bit addresses with SDMA\n");
+ esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
+ esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
+   PROCTL_DMAS_SDMA);
+ }
+
  esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 }
 
@@ -801,6 +825,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
  struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+ u32 caps, hostver;
  fdt_addr_t addr;
  struct mmc *mmc;
  int ret;
@@ -815,6 +840,21 @@ static int fsl_esdhc_probe(struct udevice *dev)
 #endif
  priv->dev = dev;
 
+ if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
+ /*
+ * Only newer eSDHC controllers can do ADMA2 if the ADMA flag
+ * is set in the host capabilities register.
+ */
+ caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
+ hostver = esdhc_read32(&priv->esdhc_regs->hostver);
+ if (caps & HOSTCAPBLT_DMAS &&
+    HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
+ priv->adma_desc_table = sdhci_adma_init();
+ if (!priv->adma_desc_table)
+ debug("Could not allocate ADMA tables, falling back to SDMA\n");
+ }
+ }
+
  if (gd->arch.sdhc_per_clk) {
  priv->sdhc_clk = gd->arch.sdhc_per_clk;
  priv->is_sdhc_per_clk = true;
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 7f8f8edc62..b903d15cb9 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -95,6 +95,10 @@
 #define PROCTL_DTW_4 0x00000002
 #define PROCTL_DTW_8 0x00000004
 #define PROCTL_D3CD 0x00000008
+#define PROCTL_DMAS_MASK 0x00000300
+#define PROCTL_DMAS_SDMA 0x00000000
+#define PROCTL_DMAS_ADMA1 0x00000100
+#define PROCTL_DMAS_ADMA2 0x00000300
 #define PROCTL_VOLT_SEL 0x00000400
 
 #define CMDARG 0x0002e008
@@ -162,6 +166,16 @@
 #define HOSTCAPBLT_DMAS 0x00400000
 #define HOSTCAPBLT_HSS 0x00200000
 
+#define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff)
+#define VENDOR_V_10 0x00
+#define VENDOR_V_20 0x10
+#define VENDOR_V_21 0x11
+#define VENDOR_V_22 0x12
+#define VENDOR_V_23 0x13
+#define VENDOR_V_30 0x20
+#define VENDOR_V_31 0x21
+#define VENDOR_V_32 0x22
+
 struct fsl_esdhc_cfg {
  phys_addr_t esdhc_base;
  u32 sdhc_clk;
--
2.20.1

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RE: [PATCH 0/6] mmc: fsl_esdhc: add ADMA2 support

Peng Fan-4
In reply to this post by Michael Walle-2
> Subject: [PATCH 0/6] mmc: fsl_esdhc: add ADMA2 support
>
> Add ADMA2 support mainly because it supports 64bit DMA addresses. These
> are for example used if you use EFI on a LS1028A board which has more than
> 2GB of RAM, because only the lower 2GB are mapped into the lower 32bit
> address space.
>
> Patches 1-4 clean the fsl_esdhc driver up. Patch 5 moves ADMA2 table
> handling code out of the sdhci core code. Patch 6 finally adds the ADMA2
> support to the fsl_esdhc driver.

Patch 4 and patch 6 was not able to apply after I take Y.b's patchset.
Please rebase for the 2 patches, I took 1,2,3,5.

Thanks,
Peng.

>
> This was tested on a custom board LS1028A board.
>
> A passing travis-ci build is available at:
>
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Ftravis-
> ci.org%2Fgithub%2Fmwalle%2Fu-boot%2Fbuilds%2F729431087&amp;data=0
> 2%7C01%7Cpeng.fan%40nxp.com%7C67b21c56cad74704e39d08d85fad71ea
> %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637364545846569
> 611&amp;sdata=hFwAYOV72ugy%2FPPQyx1aeC2qmIQSnhSqtwqDpDVUUy4
> %3D&amp;reserved=0
>
> Michael Walle (6):
>   mmc: fsl_esdhc: simplify 64bit check for SDMA transfers
>   mmc: fsl_esdhc: use dma-mapping API
>   mmc: fsl_esdhc: simplify esdhc_setup_data()
>   mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()
>   mmc: sdhci: move the ADMA2 table handling into own module
>   mmc: fsl_esdhc: add ADMA2 support
>
>  drivers/mmc/Kconfig      |  13 ++
>  drivers/mmc/Makefile     |   1 +
>  drivers/mmc/fsl_esdhc.c  | 267 ++++++++++++++++++++-------------------
>  drivers/mmc/sdhci-adma.c |  73 +++++++++++
>  drivers/mmc/sdhci.c      |  63 ++-------
>  include/fsl_esdhc.h      |  14 ++
>  include/sdhci.h          |   8 +-
>  7 files changed, 252 insertions(+), 187 deletions(-)  create mode 100644
> drivers/mmc/sdhci-adma.c
>
> --
> 2.20.1

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Re: [PATCH 0/6] mmc: fsl_esdhc: add ADMA2 support

Michael Walle-2
Hi Peng,

Am 2020-10-12 09:25, schrieb Peng Fan:

>> Subject: [PATCH 0/6] mmc: fsl_esdhc: add ADMA2 support
>>
>> Add ADMA2 support mainly because it supports 64bit DMA addresses.
>> These
>> are for example used if you use EFI on a LS1028A board which has more
>> than
>> 2GB of RAM, because only the lower 2GB are mapped into the lower 32bit
>> address space.
>>
>> Patches 1-4 clean the fsl_esdhc driver up. Patch 5 moves ADMA2 table
>> handling code out of the sdhci core code. Patch 6 finally adds the
>> ADMA2
>> support to the fsl_esdhc driver.
>
> Patch 4 and patch 6 was not able to apply after I take Y.b's patchset.
> Please rebase for the 2 patches, I took 1,2,3,5.

Thanks, I've rebased them, see:
   https://patchwork.ozlabs.org/project/uboot/list/?series=207252

-michael