[PATCH 0/4] Add Gateworks Venice board support

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[PATCH 0/4] Add Gateworks Venice board support

Tim Harvey
The Gateworks Venice product family consists of several boards based on
the i.MX 8M Mini SoC.

A challenge I've had with this is that the board model information is
stored in an I2C based EEPROM that must be read to know what PMIC is
on the board in order to adjust certain power rails before DRAM init
is called. I found this to be a challenge in the SPL as the SPL does
not free memory thus the conceprt of calling dm_uninit() followed by
dm_init_and_scan() to change dt's live in the SPL runs out of memory.
Therefore I can't rely on DT/DM within the SPL for things that may
differ board to board.

Best Regards,

Tim

Frieder Schrempf (1):
  Respect that some compression algos can be enabled separately for SPL

Tim Harvey (3):
  power: pmic: add driver for Monolithic Power mp5416
  arm: dts: imx8mm: add Gateworks i.MX8 Mini Dev kits
  board: gateworks: imx8mm: Add Gateworks Venice board support

 arch/arm/dts/Makefile                            |    4 +
 arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi    |  105 +
 arch/arm/dts/imx8mm-venice-gw700x.dtsi           |  495 +++++
 arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi |    5 +
 arch/arm/dts/imx8mm-venice-gw71xx-0x.dts         |   19 +
 arch/arm/dts/imx8mm-venice-gw71xx.dtsi           |  186 ++
 arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi |    5 +
 arch/arm/dts/imx8mm-venice-gw72xx-0x.dts         |   20 +
 arch/arm/dts/imx8mm-venice-gw72xx.dtsi           |  311 +++
 arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi |    5 +
 arch/arm/dts/imx8mm-venice-gw73xx-0x.dts         |   19 +
 arch/arm/dts/imx8mm-venice-gw73xx.dtsi           |  362 ++++
 arch/arm/dts/imx8mm-venice-u-boot.dtsi           |  103 +
 arch/arm/dts/imx8mm-venice.dts                   |  152 ++
 arch/arm/mach-imx/imx8m/Kconfig                  |    7 +
 board/gateworks/venice/Kconfig                   |   13 +
 board/gateworks/venice/MAINTAINERS               |    7 +
 board/gateworks/venice/Makefile                  |   12 +
 board/gateworks/venice/README                    |   34 +
 board/gateworks/venice/gsc.c                     |  687 ++++++
 board/gateworks/venice/gsc.h                     |   54 +
 board/gateworks/venice/imx8mm_venice.c           |  133 ++
 board/gateworks/venice/lpddr4_timing.c           | 2505 ++++++++++++++++++++++
 board/gateworks/venice/lpddr4_timing.h           |   12 +
 board/gateworks/venice/spl.c                     |  187 ++
 common/image.c                                   |   13 +-
 configs/imx8mm_venice_defconfig                  |  113 +
 drivers/power/pmic/Kconfig                       |   15 +
 drivers/power/pmic/Makefile                      |    1 +
 drivers/power/pmic/mp5416.c                      |   98 +
 include/configs/imx8mm_venice.h                  |  125 ++
 include/power/mp5416.h                           |   41 +
 32 files changed, 5842 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw700x.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
 create mode 100644 arch/arm/dts/imx8mm-venice-gw71xx.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
 create mode 100644 arch/arm/dts/imx8mm-venice-gw72xx.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
 create mode 100644 arch/arm/dts/imx8mm-venice-gw73xx.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice.dts
 create mode 100644 board/gateworks/venice/Kconfig
 create mode 100644 board/gateworks/venice/MAINTAINERS
 create mode 100644 board/gateworks/venice/Makefile
 create mode 100644 board/gateworks/venice/README
 create mode 100644 board/gateworks/venice/gsc.c
 create mode 100644 board/gateworks/venice/gsc.h
 create mode 100644 board/gateworks/venice/imx8mm_venice.c
 create mode 100644 board/gateworks/venice/lpddr4_timing.c
 create mode 100644 board/gateworks/venice/lpddr4_timing.h
 create mode 100644 board/gateworks/venice/spl.c
 create mode 100644 configs/imx8mm_venice_defconfig
 create mode 100644 drivers/power/pmic/mp5416.c
 create mode 100644 include/configs/imx8mm_venice.h
 create mode 100644 include/power/mp5416.h

--
2.7.4

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[PATCH 1/4] Respect that some compression algos can be enabled separately for SPL

Tim Harvey
From: Frieder Schrempf <[hidden email]>

Some compression algorithms currently can be enabled for SPL and
U-Boot proper separately. Therefore we need to use
CONFIG_IS_ENABLED() in these cases and also prevent compiling these
functions in case of a host tool build.

Signed-off-by: Frieder Schrempf <[hidden email]>
Signed-off-by: Tim Harvey <[hidden email]>
---
 common/image.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/common/image.c b/common/image.c
index 451fc68..bda19c0 100644
--- a/common/image.c
+++ b/common/image.c
@@ -72,6 +72,7 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
 
 #include <u-boot/crc.h>
 #include <imximage.h>
+#include <linux/kconfig.h>
 
 #ifndef CONFIG_SYS_BARGSIZE
 #define CONFIG_SYS_BARGSIZE 512
@@ -460,13 +461,13 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
  else
  ret = -ENOSPC;
  break;
-#ifdef CONFIG_GZIP
+#if CONFIG_IS_ENABLED(GZIP) && !defined(USE_HOSTCC)
  case IH_COMP_GZIP: {
  ret = gunzip(load_buf, unc_len, image_buf, &image_len);
  break;
  }
 #endif /* CONFIG_GZIP */
-#ifdef CONFIG_BZIP2
+#if CONFIG_IS_ENABLED(BZIP2) && !defined(USE_HOSTCC)
  case IH_COMP_BZIP2: {
  uint size = unc_len;
 
@@ -482,7 +483,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
  break;
  }
 #endif /* CONFIG_BZIP2 */
-#ifdef CONFIG_LZMA
+#if CONFIG_IS_ENABLED(LZMA) && !defined(USE_HOSTCC)
  case IH_COMP_LZMA: {
  SizeT lzma_len = unc_len;
 
@@ -492,7 +493,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
  break;
  }
 #endif /* CONFIG_LZMA */
-#ifdef CONFIG_LZO
+#if CONFIG_IS_ENABLED(LZO) && !defined(USE_HOSTCC)
  case IH_COMP_LZO: {
  size_t size = unc_len;
 
@@ -501,7 +502,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
  break;
  }
 #endif /* CONFIG_LZO */
-#ifdef CONFIG_LZ4
+#if CONFIG_IS_ENABLED(LZ4) && !defined(USE_HOSTCC)
  case IH_COMP_LZ4: {
  size_t size = unc_len;
 
@@ -510,7 +511,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
  break;
  }
 #endif /* CONFIG_LZ4 */
-#ifdef CONFIG_ZSTD
+#if CONFIG_IS_ENABLED(ZSTD) && !defined(USE_HOSTCC)
  case IH_COMP_ZSTD: {
  size_t size = unc_len;
  ZSTD_DStream *dstream;
--
2.7.4

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[PATCH 2/4] power: pmic: add driver for Monolithic Power mp5416

Tim Harvey
In reply to this post by Tim Harvey
This adds basic register access and child regulator binding
for the Monolithic MP5416 Power Management IC which integrates
four DC/DC switching converters and five LDO regulators.

Signed-off-by: Tim Harvey <[hidden email]>
---
 drivers/power/pmic/Kconfig  | 15 +++++++
 drivers/power/pmic/Makefile |  1 +
 drivers/power/pmic/mp5416.c | 98 +++++++++++++++++++++++++++++++++++++++++++++
 include/power/mp5416.h      | 41 +++++++++++++++++++
 4 files changed, 155 insertions(+)
 create mode 100644 drivers/power/pmic/mp5416.c
 create mode 100644 include/power/mp5416.h

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 7d51510..583fd3d 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -91,6 +91,21 @@ config DM_PMIC_FAN53555
   The driver implements read/write operations for use with the FAN53555
   regulator driver and binds the regulator driver to its node.
 
+config DM_PMIC_MP5416
+ bool "Enable Driver Model for PMIC MP5416"
+ depends on DM_PMIC
+ help
+  This config enables implementation of driver-model pmic uclass features
+  for PMIC MP5416. The driver implements read/write operations.
+
+config SPL_DM_PMIC_MP5416
+ bool "Enable Driver Model for PMIC MP5416 in SPL stage"
+ depends on DM_PMIC
+ help
+  This config enables implementation of driver-model pmic uclass
+  features for PMIC MP5416. The driver implements read/write
+  operations.
+
 config DM_PMIC_PCA9450
  bool "Enable Driver Model for PMIC PCA9450"
  depends on DM_PMIC
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 9cd6c37..2b2a6dd 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
 obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
 obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o
 obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c
new file mode 100644
index 0000000..458c4df
--- /dev/null
+++ b/drivers/power/pmic/mp5416.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier:      GPL-2.0+
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/mp5416.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ /* buck */
+ { .prefix = "b", .driver = MP6416_REGULATOR_DRIVER },
+ /* ldo */
+ { .prefix = "l", .driver = MP6416_REGULATOR_DRIVER },
+ { },
+};
+
+static int mp5416_reg_count(struct udevice *dev)
+{
+ return MP5416_NUM_OF_REGS - 1;
+}
+
+static int mp5416_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ pr_err("write error to device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int mp5416_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ pr_err("read error from device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int mp5416_bind(struct udevice *dev)
+{
+ int children;
+ ofnode regulators_node;
+
+ debug("%s %s\n", __func__, dev->name);
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!\n", __func__,
+      dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static int mp5416_probe(struct udevice *dev)
+{
+ debug("%s %s\n", __func__, dev->name);
+
+ return 0;
+}
+
+static struct dm_pmic_ops mp5416_ops = {
+ .reg_count = mp5416_reg_count,
+ .read = mp5416_read,
+ .write = mp5416_write,
+};
+
+static const struct udevice_id mp5416_ids[] = {
+ { .compatible = "mps,mp5416", },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_mp5416) = {
+ .name = "mp5416 pmic",
+ .id = UCLASS_PMIC,
+ .of_match = mp5416_ids,
+ .bind = mp5416_bind,
+ .probe = mp5416_probe,
+ .ops = &mp5416_ops,
+};
diff --git a/include/power/mp5416.h b/include/power/mp5416.h
new file mode 100644
index 0000000..dc096fe
--- /dev/null
+++ b/include/power/mp5416.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2020 Gateworks Corporation */
+
+#ifndef MP5416_H_
+#define MP5416_H_
+
+#define MP6416_REGULATOR_DRIVER "mp5416_regulator"
+
+enum {
+ MP5416_CTL0 = 0x00,
+ MP5416_CTL1 = 0x01,
+ MP5416_CTL2 = 0x02,
+ MP5416_ILIMIT = 0x03,
+ MP5416_VSET_SW1 = 0x04,
+ MP5416_VSET_SW2 = 0x05,
+ MP5416_VSET_SW3 = 0x06,
+ MP5416_VSET_SW4 = 0x07,
+ MP5416_VSET_LDO2 = 0x08,
+ MP5416_VSET_LDO3 = 0x09,
+ MP5416_VSET_LDO4 = 0x0a,
+ MP5416_VSET_LDO5 = 0x0b,
+ MP5416_STATUS1 = 0x0d,
+ MP5416_STATUS2 = 0x0e,
+ MP5416_STATUS3 = 0x0f,
+ MP5416_ID2 = 0x11,
+ MP5416_NUM_OF_REGS = 0x12,
+};
+
+#define MP5416_VSET_EN          BIT(7)
+#define MP5416_VSET_SW1_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
+#define MP5416_VSET_SW2_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
+#define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000)
+#define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500)
+#define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000)
+#define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500)
+#define MP5416_VSET_SW4_SVAL(x) (((x) - 800000) / 25000)
+
+#endif
--
2.7.4

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[PATCH 3/4] arm: dts: imx8mm: add Gateworks i.MX8 Mini Dev kits

Tim Harvey
In reply to this post by Tim Harvey
Add Gateworks i.MX 8M Mini Development kits from Mainline Linux

Signed-off-by: Tim Harvey <[hidden email]>
---
 arch/arm/dts/Makefile                    |   4 +
 arch/arm/dts/imx8mm-venice-gw700x.dtsi   | 495 +++++++++++++++++++++++++++++++
 arch/arm/dts/imx8mm-venice-gw71xx-0x.dts |  19 ++
 arch/arm/dts/imx8mm-venice-gw71xx.dtsi   | 186 ++++++++++++
 arch/arm/dts/imx8mm-venice-gw72xx-0x.dts |  20 ++
 arch/arm/dts/imx8mm-venice-gw72xx.dtsi   | 311 +++++++++++++++++++
 arch/arm/dts/imx8mm-venice-gw73xx-0x.dts |  19 ++
 arch/arm/dts/imx8mm-venice-gw73xx.dtsi   | 362 ++++++++++++++++++++++
 8 files changed, 1416 insertions(+)
 create mode 100644 arch/arm/dts/imx8mm-venice-gw700x.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
 create mode 100644 arch/arm/dts/imx8mm-venice-gw71xx.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
 create mode 100644 arch/arm/dts/imx8mm-venice-gw72xx.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
 create mode 100644 arch/arm/dts/imx8mm-venice-gw73xx.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e40..a0acf24 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -772,6 +772,10 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 
 dtb-$(CONFIG_ARCH_IMX8M) += \
  imx8mm-evk.dtb \
+ imx8mm-venice.dtb \
+ imx8mm-venice-gw71xx-0x.dtb \
+ imx8mm-venice-gw72xx-0x.dtb \
+ imx8mm-venice-gw73xx-0x.dtb \
  imx8mm-verdin.dtb \
  phycore-imx8mm.dtb \
  imx8mn-ddr4-evk.dtb \
diff --git a/arch/arm/dts/imx8mm-venice-gw700x.dtsi b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
new file mode 100644
index 0000000..c769fad
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw700x.dtsi
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck3_reg>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@16 {
+ gw,mode = <4>;
+ reg = <0x16>;
+ label = "fan_tach";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vdd_adc1";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_adc2";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_dram";
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_1p2";
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_1p0";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_0p95";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_1p8";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+
+ fan-controller@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "gw,gsc-fan";
+ reg = <0x0a>;
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+
+ pmic@69 {
+ compatible = "mps,mp5416";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x69>;
+
+ regulators {
+ buck1 {
+ regulator-name = "vdd_0p95";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-max-microamp = <2500000>;
+ regulator-boot-on;
+ };
+
+ buck2 {
+ regulator-name = "vdd_soc";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <900000>;
+ regulator-max-microamp = <1000000>;
+ regulator-boot-on;
+ };
+
+ buck3_reg: buck3 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <805000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-max-microamp = <2200000>;
+ regulator-boot-on;
+ };
+
+ buck4 {
+ regulator-name = "vdd_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-max-microamp = <500000>;
+ regulator-boot-on;
+ };
+
+ ldo1 {
+ regulator-name = "nvcc_snvs_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-max-microamp = <300000>;
+ regulator-boot-on;
+ };
+
+ ldo2 {
+ regulator-name = "vdd_snvs_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ };
+
+ ldo3 {
+ regulator-name = "vdd_0p95";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ };
+
+ ldo4 {
+ regulator-name = "vdd_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
new file mode 100644
index 0000000..3f88c4a
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-venice-gw700x.dtsi"
+#include "imx8mm-venice-gw71xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit";
+ compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi
new file mode 100644
index 0000000..905b68a
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw71xx.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
+ MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
new file mode 100644
index 0000000..b1e7540
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-venice-gw700x.dtsi"
+#include "imx8mm-venice-gw72xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit";
+ compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi
new file mode 100644
index 0000000..b7c91bd
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw72xx.dtsi
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* off-board header */
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* off-board header */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+/* RS232 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <&reg_usb_otg2_vbus>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_reg_usb2_en: regusb2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts b/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
new file mode 100644
index 0000000..6905437
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+#include "imx8mm-venice-gw700x.dtsi"
+#include "imx8mm-venice-gw73xx.dtsi"
+
+/ {
+ model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit";
+ compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi
new file mode 100644
index 0000000..d2ffd62
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw73xx.dtsi
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pps>;
+ gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2_en>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi_en: regulator-wifi-en {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wl";
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+/* off-board header */
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ accelerometer@19 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_accel>;
+ compatible = "st,lis2de12";
+ reg = <0x19>;
+ st,drdy-int-pin = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+ };
+};
+
+/* off-board header */
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+};
+
+/* off-board header */
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <24576000>;
+ status = "okay";
+};
+
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* bluetooth HCI */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
+ cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+/* RS232 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <&reg_usb_otg2_vbus>;
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <&reg_wifi_en>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
+ MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
+ MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
+ >;
+ };
+
+ pinctrl_accel: accelgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
+ >;
+ };
+
+ pinctrl_bten: btengrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pps: ppsgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
+ >;
+ };
+
+ pinctrl_reg_usb1_en: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
+ MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_reg_usb2_en: regusb2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
+ MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
+ MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
+ MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+ MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_spi2: spi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+};
--
2.7.4

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[PATCH 4/4] board: gateworks: imx8mm: Add Gateworks Venice board support

Tim Harvey
In reply to this post by Tim Harvey
Add initial support for Gateworks Venice product family based on the
i.MX 8M Mini SoC

Signed-off-by: Tim Harvey <[hidden email]>
---
 arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi    |  105 +
 arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi |    5 +
 arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi |    5 +
 arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi |    5 +
 arch/arm/dts/imx8mm-venice-u-boot.dtsi           |  103 +
 arch/arm/dts/imx8mm-venice.dts                   |  152 ++
 arch/arm/mach-imx/imx8m/Kconfig                  |    7 +
 board/gateworks/venice/Kconfig                   |   13 +
 board/gateworks/venice/MAINTAINERS               |    7 +
 board/gateworks/venice/Makefile                  |   12 +
 board/gateworks/venice/README                    |   34 +
 board/gateworks/venice/gsc.c                     |  687 ++++++
 board/gateworks/venice/gsc.h                     |   54 +
 board/gateworks/venice/imx8mm_venice.c           |  133 ++
 board/gateworks/venice/lpddr4_timing.c           | 2505 ++++++++++++++++++++++
 board/gateworks/venice/lpddr4_timing.h           |   12 +
 board/gateworks/venice/spl.c                     |  187 ++
 configs/imx8mm_venice_defconfig                  |  113 +
 include/configs/imx8mm_venice.h                  |  125 ++
 19 files changed, 4264 insertions(+)
 create mode 100644 arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-venice.dts
 create mode 100644 board/gateworks/venice/Kconfig
 create mode 100644 board/gateworks/venice/MAINTAINERS
 create mode 100644 board/gateworks/venice/Makefile
 create mode 100644 board/gateworks/venice/README
 create mode 100644 board/gateworks/venice/gsc.c
 create mode 100644 board/gateworks/venice/gsc.h
 create mode 100644 board/gateworks/venice/imx8mm_venice.c
 create mode 100644 board/gateworks/venice/lpddr4_timing.c
 create mode 100644 board/gateworks/venice/lpddr4_timing.h
 create mode 100644 board/gateworks/venice/spl.c
 create mode 100644 configs/imx8mm_venice_defconfig
 create mode 100644 include/configs/imx8mm_venice.h

diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
new file mode 100644
index 0000000..a4487e2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
new file mode 100644
index 0000000..f5d52c2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw71xx-0x-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+#include "imx8mm-venice-gw700x-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi
new file mode 100644
index 0000000..f5d52c2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw72xx-0x-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+#include "imx8mm-venice-gw700x-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi
new file mode 100644
index 0000000..f5d52c2
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw73xx-0x-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+#include "imx8mm-venice-gw700x-u-boot.dtsi"
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
new file mode 100644
index 0000000..5b06d87
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-venice.dts b/arch/arm/dts/imx8mm-venice.dts
new file mode 100644
index 0000000..54505a0
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice.dts
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice i.MX8MM board";
+ compatible = "gw,imx8mm-venice", "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ eeprom@52 {
+ compatible = "atmel,24c32";
+ reg = <0x52>;
+ pagesize = <32>;
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 8615dc3..b9c38cd 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -43,6 +43,12 @@ config TARGET_IMX8MM_EVK
  select SUPPORT_SPL
  select IMX8M_LPDDR4
 
+config TARGET_IMX8MM_VENICE
+ bool "Support Gateworks Venice iMX8M Mini module"
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+
 config TARGET_IMX8MN_EVK
  bool "imx8mn DDR4 EVK board"
  select IMX8MN
@@ -83,6 +89,7 @@ source "board/freescale/imx8mq_evk/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
 source "board/freescale/imx8mn_evk/Kconfig"
 source "board/freescale/imx8mp_evk/Kconfig"
+source "board/gateworks/venice/Kconfig"
 source "board/google/imx8mq_phanbell/Kconfig"
 source "board/technexion/pico-imx8mq/Kconfig"
 source "board/toradex/verdin-imx8mm/Kconfig"
diff --git a/board/gateworks/venice/Kconfig b/board/gateworks/venice/Kconfig
new file mode 100644
index 0000000..e11798f
--- /dev/null
+++ b/board/gateworks/venice/Kconfig
@@ -0,0 +1,13 @@
+if TARGET_IMX8MM_VENICE
+
+config SYS_BOARD
+ default "venice"
+
+config SYS_VENDOR
+ default "gateworks"
+
+config SYS_CONFIG_NAME
+ default "imx8mm_venice"
+
+endif
+
diff --git a/board/gateworks/venice/MAINTAINERS b/board/gateworks/venice/MAINTAINERS
new file mode 100644
index 0000000..07b9e2a
--- /dev/null
+++ b/board/gateworks/venice/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8MM Venice
+M: Tim Harvey <[hidden email]>
+S: Maintained
+F: arch/arm/dts/imx8mm-venice*
+F: board/gateworks/venice/
+F: include/configs/venice.h
+F: configs/imx8mm_venice_defconfig
diff --git a/board/gateworks/venice/Makefile b/board/gateworks/venice/Makefile
new file mode 100644
index 0000000..08f5c62
--- /dev/null
+++ b/board/gateworks/venice/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2021 Gateworks Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mm_venice.o gsc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/gateworks/venice/README b/board/gateworks/venice/README
new file mode 100644
index 0000000..6a0ab1e
--- /dev/null
+++ b/board/gateworks/venice/README
@@ -0,0 +1,34 @@
+U-Boot for the Gateworks i.MX8M Mini Venice Development Kit boards
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Flash to eMMC
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ git checkout imx_5.4.47_2.2.0
+$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31
+$ cp build/imx8mm/release/bl31.bin .
+
+Get the DDR Firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9.bin
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+============
+$ make imx8mm_venice_defconfig
+$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
+
+Update eMMC
+===========
+=> tftpboot $loadaddr flash.bin
+=> setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
+=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt
diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c
new file mode 100644
index 0000000..ad3f8d9
--- /dev/null
+++ b/board/gateworks/venice/gsc.c
@@ -0,0 +1,687 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hang.h>
+#include <hexdump.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <dm/uclass.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct venice_board_info som_info;
+struct venice_board_info base_info;
+char venice_model[32];
+
+/* return a mac address from EEPROM info */
+int gsc_getmac(int index, uint8_t *address)
+{
+ int i, j;
+ u32 maclow, machigh;
+ u64 mac;
+
+ j = 0;
+ if (som_info.macno) {
+ maclow = som_info.mac[5];
+ maclow |= som_info.mac[4] << 8;
+ maclow |= som_info.mac[3] << 16;
+ maclow |= som_info.mac[2] << 24;
+ machigh = som_info.mac[1];
+ machigh |= som_info.mac[0] << 8;
+ mac = machigh;
+ mac <<= 32;
+ mac |= maclow;
+ for (i = 0; i < som_info.macno; i++, j++) {
+ if (index == j)
+ goto out;
+ }
+ }
+
+ maclow = base_info.mac[5];
+ maclow |= base_info.mac[4] << 8;
+ maclow |= base_info.mac[3] << 16;
+ maclow |= base_info.mac[2] << 24;
+ machigh = base_info.mac[1];
+ machigh |= base_info.mac[0] << 8;
+ mac = machigh;
+ mac <<= 32;
+ mac |= maclow;
+ for (i = 0; i < base_info.macno; i++, j++) {
+ if (index == j)
+ goto out;
+ }
+
+ return -EINVAL;
+
+out:
+ mac += i;
+ address[0] = (mac >> 40) & 0xff;
+ address[1] = (mac >> 32) & 0xff;
+ address[2] = (mac >> 24) & 0xff;
+ address[3] = (mac >> 16) & 0xff;
+ address[4] = (mac >> 8) & 0xff;
+ address[5] = (mac >> 0) & 0xff;
+
+ return 0;
+}
+
+/* System Controller registers */
+enum {
+ GSC_SC_CTRL0 = 0,
+ GSC_SC_CTRL1 = 1,
+ GSC_SC_STATUS = 10,
+ GSC_SC_FWCRC = 12,
+ GSC_SC_FWVER = 14,
+ GSC_SC_WP = 15,
+ GSC_SC_RST_CAUSE = 16,
+ GSC_SC_THERM_PROTECT = 19,
+};
+
+/* System Controller Control1 bits */
+enum {
+ GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
+ GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
+ GSC_SC_CTRL1_BOOT_CHK   = 6, /* 1 = enable alt boot check */
+ GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
+};
+
+/* System Controller Interrupt bits */
+enum {
+ GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
+ GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
+ GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
+ GSC_SC_IRQ_GPIO = 4, /* GPIO change */
+ GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
+ GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
+ GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
+};
+
+/* System Controller WP bits */
+enum {
+ GSC_SC_WP_ALL = 0, /* Write Protect All EEPROM regions */
+ GSC_SC_WP_BOARDINFO = 1, /* Write Protect Board Info region */
+};
+
+/* System Controller Reset Cause */
+enum {
+ GSC_SC_RST_CAUSE_VIN = 0,
+ GSC_SC_RST_CAUSE_PB = 1,
+ GSC_SC_RST_CAUSE_WDT = 2,
+ GSC_SC_RST_CAUSE_CPU = 3,
+ GSC_SC_RST_CAUSE_TEMP_LOCAL = 4,
+ GSC_SC_RST_CAUSE_TEMP_REMOTE = 5,
+ GSC_SC_RST_CAUSE_SLEEP = 6,
+ GSC_SC_RST_CAUSE_BOOT_WDT = 7,
+ GSC_SC_RST_CAUSE_BOOT_WDT_MAN = 8,
+ GSC_SC_RST_CAUSE_SOFT_PWR = 9,
+ GSC_SC_RST_CAUSE_MAX = 10,
+};
+
+static struct udevice *gsc_get_dev(int busno, int slave)
+{
+ struct udevice *dev;
+ int ret;
+
+#if (IS_ENABLED(CONFIG_SPL_BUILD))
+ ret = i2c_get_chip_for_busnum(busno + 1, slave, 1, &dev);
+ if (ret)
+ return NULL;
+#else
+ struct udevice *bus;
+
+ busno--;
+
+ ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
+ if (ret) {
+ printf("i2c%d: no bus %d\n", busno + 1, ret);
+ return NULL;
+ }
+ ret = i2c_get_chip(bus, slave, 1, &dev);
+ if (ret) {
+ printf("i2c%d@0x%02x: no chip %d\n", busno + 1, slave, ret);
+ return NULL;
+ }
+#endif
+
+ return dev;
+}
+
+static int gsc_read_eeprom(int bus, int slave, int alen, struct venice_board_info *info)
+{
+ int i;
+ int chksum;
+ unsigned char *buf = (unsigned char *)info;
+ struct udevice *dev;
+ int ret;
+
+ /* probe device */
+ dev = gsc_get_dev(bus, slave);
+ if (!dev) {
+ if (slave == GSC_EEPROM_ADDR)
+ puts("ERROR: Failed to probe EEPROM\n");
+ return -ENODEV;
+ }
+
+ /* read eeprom config section */
+ memset(info, 0, sizeof(*info));
+ ret = i2c_set_chip_offset_len(dev, alen);
+ if (ret) {
+ puts("EEPROM: Failed to set alen\n");
+ return ret;
+ }
+ ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info));
+ if (ret) {
+ if (slave == GSC_EEPROM_ADDR)
+ printf("EEPROM: Failed to read EEPROM\n");
+ return ret;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++)
+ chksum += buf[i];
+ if ((info->chksum[0] != chksum >> 8) ||
+    (info->chksum[1] != (chksum & 0xff))) {
+ printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+ print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+ memset(info, 0, sizeof(*info));
+ return -EINVAL;
+ }
+
+ /* sanity check valid model */
+ if (info->model[0] != 'G' || info->model[1] != 'W') {
+ printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
+ print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
+ memset(info, 0, sizeof(*info));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const char *gsc_get_rst_cause(struct udevice *dev)
+{
+ static char str[64];
+ static const char * const names[] = {
+ "VIN",
+ "PB",
+ "WDT",
+ "CPU",
+ "TEMP_L",
+ "TEMP_R",
+ "SLEEP",
+ "BOOT_WDT1",
+ "BOOT_WDT2",
+ "SOFT_PWR",
+ };
+ unsigned char reg;
+
+ /* reset cause */
+ str[0] = 0;
+ if (!dm_i2c_read(dev, GSC_SC_RST_CAUSE, &reg, 1)) {
+ if (reg < ARRAY_SIZE(names))
+ sprintf(str, "%s", names[reg]);
+ else
+ sprintf(str, "0x%02x", reg);
+ }
+
+ /* thermal protection */
+ if (!dm_i2c_read(dev, GSC_SC_THERM_PROTECT, &reg, 1)) {
+ reg |= 1;
+ dm_i2c_write(dev, GSC_SC_THERM_PROTECT, &reg, 1);
+ strcat(str, " Thermal Protection Enabled");
+ }
+
+ return str;
+}
+
+/* display hardware monitor ADC channels */
+int gsc_hwmon(void)
+{
+ const void *fdt = gd->fdt_blob;
+ struct udevice *dev;
+ int node, reg, mode, len, val, offset;
+ const char *label;
+ u8 buf[2];
+ int ret;
+
+ node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
+ if (node <= 0)
+ return node;
+
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_HWMON_ADDR);
+ if (!dev) {
+ puts("ERROR: Failed to probe GSC HWMON\n");
+ return -ENODEV;
+ }
+
+ /* iterate over hwmon nodes */
+ node = fdt_first_subnode(fdt, node);
+ while (node > 0) {
+ reg = fdtdec_get_int(fdt, node, "reg", -1);
+ mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
+ offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
+ label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
+
+ if ((reg == -1) || (mode == -1) || !label)
+ printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
+
+ memset(buf, 0, sizeof(buf));
+ ret = dm_i2c_read(dev, reg, buf, sizeof(buf));
+ if (ret) {
+ printf("i2c error: %d\n", ret);
+ continue;
+ }
+ val = buf[0] | buf[1] << 8;
+ if (val >= 0) {
+ const u32 *div;
+ int r[2];
+
+ switch (mode) {
+ case 0: /* temperature (C*10) */
+ if (val > 0x8000)
+ val -= 0xffff;
+ printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
+ break;
+ case 1: /* prescaled voltage */
+ if (val != 0xffff)
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ case 2: /* scaled based on ref volt and resolution */
+ val *= 2500;
+ val /= 1 << 12;
+
+ /* apply pre-scaler voltage divider */
+ div  = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
+ if (div && (len == sizeof(uint32_t) * 2)) {
+ r[0] = fdt32_to_cpu(div[0]);
+ r[1] = fdt32_to_cpu(div[1]);
+ if (r[0] && r[1]) {
+ val *= (r[0] + r[1]);
+ val /= r[1];
+ }
+ }
+
+ /* adjust by offset */
+ val += offset;
+
+ printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
+ break;
+ }
+ }
+ node = fdt_next_subnode(fdt, node);
+ }
+
+ return 0;
+}
+
+/* determine BOM revision from model */
+int get_bom_rev(const char *str)
+{
+ int  rev_bom = 0;
+ int i;
+
+ for (i = strlen(str) - 1; i > 0; i--) {
+ if (str[i] == '-')
+ break;
+ if (str[i] >= '1' && str[i] <= '9') {
+ rev_bom = str[i] - '0';
+ break;
+ }
+ }
+ return rev_bom;
+}
+
+/* determine PCB revision from model */
+char get_pcb_rev(const char *str)
+{
+ char rev_pcb = 'A';
+ int i;
+
+ for (i = strlen(str) - 1; i > 0; i--) {
+ if (str[i] == '-')
+ break;
+ if (str[i] >= 'A') {
+ rev_pcb = str[i];
+ break;
+ }
+ }
+ return rev_pcb;
+}
+
+/*
+ * get dt name based on model and detail level:
+ *
+ * For boards that are a combination of a SoM plus a Baseboard:
+ *   Venice SoM part numbers are GW70xx where xx is:
+ *    7000-7019: same PCB with som dt of '0x'
+ *    7020-7039: same PCB with som dt of '2x'
+ *    7040-7059: same PCB with som dt of '4x'
+ *    7060-7079: same PCB with som dt of '6x'
+ *    7080-7099: same PCB with som dt of '8x'
+ *   Venice Baseboard part numbers are GW7xxx where xxx is:
+ *    7100-7199: same PCB with base dt of '71xx'
+ *    7200-7299: same PCB with base dt of '72xx'
+ *    7300-7399: same PCB with base dt of '73xx'
+ *    7400-7499: same PCB with base dt of '74xx'
+ *    7500-7599: same PCB with base dt of '75xx'
+ *    7600-7699: same PCB with base dt of '76xx'
+ *    7700-7799: same PCB with base dt of '77xx'
+ *    7800-7899: same PCB with base dt of '78xx'
+ *   DT name is comprised of:
+ *    gw<base dt>-<som dt>-[base-pcb-rev][base-bom-rev][som-pcb-rev][som-bom-rev]
+ *
+ * For board models from 7900-7999 each PCB is unique with its own dt:
+ *   DT name is comprised:
+ *    gw<model>-[pcb-rev][bom-rev]
+ *
+ */
+#define snprintfcat(dest, sz, fmt, ...) \
+ snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__)
+const char *gsc_get_dtb_name(int level, char *buf, int sz)
+{
+ const char *pre = "imx8mm-venice-gw";
+ int model, rev_pcb, rev_bom;
+
+ model = ((som_info.model[2] - '0') * 1000)
+ + ((som_info.model[3] - '0') * 100)
+ + ((som_info.model[4] - '0') * 10)
+ + (som_info.model[5] - '0');
+ rev_pcb = tolower(get_pcb_rev(som_info.model));
+ rev_bom = get_bom_rev(som_info.model);
+
+ /* som + baseboard*/
+ if (base_info.model[0]) {
+ /* baseboard id: 7100-7199->71; 7200-7299->72; etc */
+ int base = ((base_info.model[2] - '0') * 10) + (base_info.model[3] - '0');
+ /* som id: 7000-7019->1; 7020-7039->2; etc */
+ int som = ((model % 100) / 20) * 2;
+ int rev_base_pcb = tolower(get_pcb_rev(base_info.model));
+ int rev_base_bom = get_bom_rev(base_info.model);
+
+ snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som);
+ switch (level) {
+ case 0: /* full model (ie gw73xx-0x-a1a1) */
+ if (rev_base_bom)
+ snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+ else
+ snprintfcat(buf, sz, "-%c", rev_base_pcb);
+ if (rev_bom)
+ snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+ else
+ snprintfcat(buf, sz, "%c", rev_pcb);
+ break;
+ case 1: /* don't care about SoM revision */
+ if (rev_base_bom)
+ snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
+ else
+ snprintfcat(buf, sz, "-%c", rev_base_pcb);
+ snprintfcat(buf, sz, "xx");
+ break;
+ case 2: /* don't care about baseboard revision */
+ snprintfcat(buf, sz, "-xx");
+ if (rev_bom)
+ snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
+ else
+ snprintfcat(buf, sz, "%c", rev_pcb);
+ break;
+ case 3: /* don't care about SoM/baseboard revision */
+ break;
+ default:
+ return NULL;
+ }
+ } else {
+ snprintf(buf, sz, "%s%04d", pre, model);
+ switch (level) {
+ case 0: /* full model wth PCB and BOM revision first (ie gw7901-a1) */
+ if (rev_bom)
+ snprintfcat(buf, sz, "-%c%d", rev_pcb, rev_bom);
+ else
+ snprintfcat(buf, sz, "-%c", rev_pcb);
+ break;
+ case 1: /* don't care about BOM revision */
+ snprintfcat(buf, sz, "-%c", rev_pcb);
+ break;
+ case 2: /* don't care about PCB or BOM revision */
+ break;
+ default:
+ return NULL;
+ }
+ }
+
+ return buf;
+}
+
+static int gsc_read(void)
+{
+ int ret;
+
+ ret = gsc_read_eeprom(1, GSC_EEPROM_ADDR, 1, &som_info);
+ if (ret) {
+ memset(&som_info, 0, sizeof(som_info));
+ return ret;
+ }
+
+ /* read optional baseboard EEPROM */
+ return gsc_read_eeprom(2, 0x52, 2, &base_info);
+}
+
+static int gsc_info(int verbose)
+{
+ struct udevice *dev;
+ unsigned char buf[16];
+ char rev_pcb;
+ int rev_bom;
+
+ if (!base_info.model[0]) {
+ strcpy(venice_model, som_info.model);
+ printf("Model   : %s\n", som_info.model);
+ printf("Serial  : %d\n", som_info.serial);
+ printf("MFGDate : %02x-%02x-%02x%02x\n",
+       som_info.mfgdate[0], som_info.mfgdate[1],
+       som_info.mfgdate[2], som_info.mfgdate[3]);
+ } else {
+ sprintf(venice_model, "GW%c%c%c%c-%c%c-",
+ som_info.model[2], /* family */
+ base_info.model[3], /* baseboard */
+ base_info.model[4], base_info.model[5], /* subload of baseboard */
+ som_info.model[4], som_info.model[5]); /* last 2digits of SOM */
+
+ /* baseboard revision */
+ rev_pcb = get_pcb_rev(base_info.model);
+ rev_bom = get_bom_rev(base_info.model);
+ if (rev_bom)
+ sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+ else
+ sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+ /* som revision */
+ rev_pcb = get_pcb_rev(som_info.model);
+ rev_bom = get_bom_rev(som_info.model);
+ if (rev_bom)
+ sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
+ else
+ sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
+
+ if (verbose > 1) {
+ printf("SOM     : %s %d %02x-%02x-%02x%02x\n",
+       som_info.model, som_info.serial,
+       som_info.mfgdate[0], som_info.mfgdate[1],
+       som_info.mfgdate[2], som_info.mfgdate[3]);
+ printf("BASE    : %s %d %02x-%02x-%02x%02x\n",
+       base_info.model, base_info.serial,
+       base_info.mfgdate[0], base_info.mfgdate[1],
+       base_info.mfgdate[2], base_info.mfgdate[3]);
+ }
+ printf("Model   : %s\n", venice_model);
+ printf("Serial  : %d\n", som_info.serial);
+ printf("MFGDate : %02x-%02x-%02x%02x\n",
+       som_info.mfgdate[0], som_info.mfgdate[1],
+       som_info.mfgdate[2], som_info.mfgdate[3]);
+ }
+
+ /* Display RTC */
+ puts("RTC     : ");
+ dev = gsc_get_dev(1, GSC_RTC_ADDR);
+ if (!dev) {
+ puts("Failed to probe GSC RTC\n");
+ } else {
+ dm_i2c_read(dev, 0, buf, 6);
+ printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
+ }
+
+ return 0;
+}
+
+int gsc_init(int quiet)
+{
+ unsigned char buf[16];
+ struct udevice *dev;
+ int ret;
+
+ /*
+ * On a board with a missing/depleted backup battery for GSC, the
+ * board may be ready to probe the GSC before its firmware is
+ * running.  We will wait here indefinately for the GSC/EEPROM.
+ */
+ while (1) {
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_SC_ADDR);
+ if (dev)
+ break;
+ mdelay(1);
+ }
+
+ ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+ if (ret) {
+ puts("ERROR: Failed reading GSC\n");
+ return ret;
+ }
+ gsc_read();
+
+ /* banner */
+ if (!quiet) {
+ printf("GSC     : v%d 0x%04x", buf[GSC_SC_FWVER],
+       buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
+ printf(" RST:%s", gsc_get_rst_cause(dev));
+ printf("\n");
+ gsc_info(1);
+ }
+
+ if (ret)
+ hang();
+
+ return ((16 << som_info.sdram_size) / 1024);
+}
+
+const char *gsc_get_model(void)
+{
+ return venice_model;
+}
+
+#if !(IS_ENABLED(CONFIG_SPL_BUILD))
+static int gsc_sleep(unsigned long secs)
+{
+ unsigned char reg;
+ struct udevice *dev;
+ int ret;
+
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_SC_ADDR);
+ if (!dev)
+ return -ENODEV;
+
+ printf("GSC Sleeping for %ld seconds\n", secs);
+ reg = (secs >> 24) & 0xff;
+ ret = dm_i2c_write(dev, 9, &reg, 1);
+ if (ret)
+ goto err;
+ reg = (secs >> 16) & 0xff;
+ ret = dm_i2c_write(dev, 8, &reg, 1);
+ if (ret)
+ goto err;
+ reg = (secs >> 8) & 0xff;
+ ret = dm_i2c_write(dev, 7, &reg, 1);
+ if (ret)
+ goto err;
+ reg = secs & 0xff;
+ ret = dm_i2c_write(dev, 6, &reg, 1);
+ if (ret)
+ goto err;
+ ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
+ if (ret)
+ goto err;
+ reg |= (1 << 2);
+ ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+ if (ret)
+ goto err;
+ reg &= ~(1 << 2);
+ reg |= 0x3;
+ ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+ if (ret)
+ goto err;
+
+ return 0;
+
+err:
+ printf("i2c error\n");
+ return ret;
+}
+
+static int gsc_boot_wd_disable(void)
+{
+ u8 reg;
+ struct udevice *dev;
+ int ret;
+
+ /* probe device */
+ dev = gsc_get_dev(1, GSC_SC_ADDR);
+ if (!dev)
+ return -ENODEV;
+
+ ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
+ if (ret)
+ goto err;
+ reg |= (1 << GSC_SC_CTRL1_WDDIS);
+ reg &= ~(1 << GSC_SC_CTRL1_BOOT_CHK);
+ ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
+ if (ret)
+ goto err;
+ puts("GSC     : boot watchdog disabled\n");
+
+ return 0;
+
+err:
+ printf("i2c error");
+ return ret;
+}
+
+static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc < 2)
+ return gsc_info(2);
+
+ if (strcasecmp(argv[1], "sleep") == 0) {
+ if (argc < 3)
+ return CMD_RET_USAGE;
+ if (!gsc_sleep(simple_strtoul(argv[2], NULL, 10)))
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "hwmon") == 0) {
+ if (!gsc_hwmon())
+ return CMD_RET_SUCCESS;
+ } else if (strcasecmp(argv[1], "wd-disable") == 0) {
+ if (!gsc_boot_wd_disable())
+ return CMD_RET_SUCCESS;
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
+   "[sleep <secs>]|[hwmon]|[wd-disable]\n");
+#endif
diff --git a/board/gateworks/venice/gsc.h b/board/gateworks/venice/gsc.h
new file mode 100644
index 0000000..00bc6c0
--- /dev/null
+++ b/board/gateworks/venice/gsc.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef _GSC_H_
+#define _GSC_H_
+
+/* I2C slave addresses */
+#define GSC_SC_ADDR             0x20
+#define GSC_RTC_ADDR            0x68
+#define GSC_HWMON_ADDR          0x29
+#define GSC_EEPROM_ADDR         0x51
+
+/* MAX6642 temperature sensor */
+#define MAX6642_SLAVE           0x4a
+#define MAX6642_R_TEMP_LOCAL    0x00
+#define MAX6642_R_TEMP_REMOTE   0x01
+#define MAX6642_R_STATUS        0x02
+#define MAX6642_R_CONFIG        0x03
+#define MAX6642_R_LIMIT_LOCAL   0x05
+#define MAX6642_R_LIMIT_REMOTE  0x07
+#define MAX6642_W_CONFIG        0x09
+#define MAX6642_W_LIMIT_LOCAL   0x0b
+#define MAX6642_W_LIMIT_REMOTE  0x0d
+#define MAX6642_R_TEMP_LOCAL_E  0x10
+#define MAX6642_R_TEMP_REMOTE_E 0x11
+
+struct venice_board_info {
+ u8 mac[6]; /* 0x00: MAC base */
+ char equiv_dts[16]; /* 0x06: equivalent device-tree */
+ u8 res0[2]; /* 0x16: reserved */
+ u32 serial; /* 0x18: Serial Number */
+ u8 res1[4]; /* 0x1C: reserved */
+ u8 mfgdate[4]; /* 0x20: MFG date */
+ u8 macno; /* 0x24: number of mac addrs */
+ u8 res2[6]; /* 0x25 */
+ u8 sdram_size; /* 0x2B: (16 << n) MB */
+ u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
+ u8 sdram_width; /* 0x2D: (8 << n) bit */
+ u8 res3[2]; /* 0x2E */
+ char model[16]; /* 0x30: model string */
+ u8 res4[14]; /* 0x40 */
+ u8 chksum[2]; /* 0x4E */
+};
+
+int gsc_init(int quiet);
+int gsc_hwmon(void);
+const char *gsc_get_model(void);
+const char *gsc_get_dtb_name(int level, char *buf, int len);
+int gsc_getmac(int index, uint8_t *enetaddr);
+
+#endif
+
diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c
new file mode 100644
index 0000000..1d51b6e
--- /dev/null
+++ b/board/gateworks/venice/imx8mm_venice.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <init.h>
+#include <led.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+#include "gsc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+ int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
+
+ if (ddr_size == 0x4) {
+ *size = 0x100000000;
+ } else if (ddr_size == 0x3) {
+ *size = 0xc0000000;
+ } else if (ddr_size == 0x2) {
+ *size = 0x80000000;
+ } else if (ddr_size == 0x1) {
+ *size = 0x40000000;
+ } else {
+ printf("Unknown DDR type!!!\n");
+ *size = 0x40000000;
+ }
+
+ return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ int i  = 0;
+ const char *dtb;
+ char buf[32];
+
+ do {
+ dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
+ if (!strcmp(dtb, name))
+ return 0;
+ } while (dtb);
+
+ return -1;
+}
+
+#if (IS_ENABLED(CONFIG_FEC_MXC))
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ switch (phydev->phy_id) {
+ case 0x2000a231: /* TI DP83867 GbE PHY */
+ puts("DP83867 ");
+ /* LED configuration */
+ val = 0;
+ val |= 0x5 << 4; /* LED1(Amber;Speed)   : 1000BT link */
+ val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
+ phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
+ break;
+ }
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif // IS_ENABLED(CONFIG_FEC_MXC)
+
+int board_init(void)
+{
+ gsc_init(1);
+
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
+ gsc_hwmon();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ const char *ethmac;
+ char env[32];
+ int ret, i;
+ u8 enetaddr[6];
+
+ led_default_state();
+
+ /* Set mac addrs */
+ i = 0;
+ do {
+ if (i)
+ sprintf(env, "eth%daddr", i);
+ else
+ sprintf(env, "ethaddr");
+ ethmac = env_get(env);
+ if (!ethmac) {
+ ret = gsc_getmac(i, enetaddr);
+ if (!ret)
+ eth_env_set_enetaddr(env, enetaddr);
+ }
+ i++;
+ } while (!ret);
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
diff --git a/board/gateworks/venice/lpddr4_timing.c b/board/gateworks/venice/lpddr4_timing.c
new file mode 100644
index 0000000..47e93e1
--- /dev/null
+++ b/board/gateworks/venice/lpddr4_timing.c
@@ -0,0 +1,2505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b0087 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0x8d },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0xf070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc0012 },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x13 },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30005 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x5 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200c7, 0x21 },
+ { 0x1200ca, 0x24 },
+ { 0x2200c7, 0x21 },
+ { 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
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+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x100 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54011, 0x0 },
+ { 0x54012, 0x110 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401d, 0x0 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54023, 0x0 },
+ { 0x54024, 0x16 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x5d },
+ { 0x2000c, 0xbb },
+ { 0x2000d, 0x753 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg_1gb[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_1gb),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_1gb),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_1gb),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg_1gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_1gb),
+ },
+};
+
+/* lpddr4 timing config params */
+struct dram_timing_info dram_timing_1gb = {
+ .ddrc_cfg = lpddr4_ddrc_cfg_1gb,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_1gb),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg_1gb,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_1gb),
+ .fsp_msg = lpddr4_dram_fsp_msg_1gb,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_1gb),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
+
+static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = {
+ /** Initialize DDRC registers **/
+ { 0x3d400304, 0x1 },
+ { 0x3d400030, 0x1 },
+ { 0x3d400000, 0xa3080020 },
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x3a980 },
+ { 0x3d400064, 0x5b00d2 },
+ { 0x3d4000d0, 0xc00305ba },
+ { 0x3d4000d4, 0x940000 },
+ { 0x3d4000dc, 0xd4002d },
+ { 0x3d4000e0, 0x310000 },
+ { 0x3d4000e8, 0x66004d },
+ { 0x3d4000ec, 0x16004d },
+ { 0x3d400100, 0x191e1920 },
+ { 0x3d400104, 0x60630 },
+ { 0x3d40010c, 0xb0b000 },
+ { 0x3d400110, 0xe04080e },
+ { 0x3d400114, 0x2040c0c },
+ { 0x3d400118, 0x1010007 },
+ { 0x3d40011c, 0x401 },
+ { 0x3d400130, 0x20600 },
+ { 0x3d400134, 0xc100002 },
+ { 0x3d400138, 0xd8 },
+ { 0x3d400144, 0x96004b },
+ { 0x3d400180, 0x2ee0017 },
+ { 0x3d400184, 0x2605b8e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x497820a },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x170a },
+ { 0x3d4001a0, 0xe0400018 },
+ { 0x3d4001a4, 0xdf00e4 },
+ { 0x3d4001a8, 0x80000000 },
+ { 0x3d4001b0, 0x11 },
+ { 0x3d4001c0, 0x1 },
+ { 0x3d4001c4, 0x1 },
+ { 0x3d4000f4, 0xc99 },
+ { 0x3d400108, 0x70e1617 },
+ { 0x3d400200, 0x17 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x7070707 },
+ { 0x3d400250, 0x29001701 },
+ { 0x3d400254, 0x2c },
+ { 0x3d40025c, 0x4000030 },
+ { 0x3d400264, 0x900093e7 },
+ { 0x3d40026c, 0x2005574 },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x2100e07 },
+ { 0x3d400498, 0x620096 },
+ { 0x3d40049c, 0x1100e07 },
+ { 0x3d4004a0, 0xc8012c },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x7d00 },
+ { 0x3d402050, 0x20d040 },
+ { 0x3d402064, 0xc001c },
+ { 0x3d4020dc, 0x840000 },
+ { 0x3d4020e0, 0x310000 },
+ { 0x3d4020e8, 0x66004d },
+ { 0x3d4020ec, 0x16004d },
+ { 0x3d402100, 0xa040305 },
+ { 0x3d402104, 0x30407 },
+ { 0x3d402108, 0x203060b },
+ { 0x3d40210c, 0x505000 },
+ { 0x3d402110, 0x2040202 },
+ { 0x3d402114, 0x2030202 },
+ { 0x3d402118, 0x1010004 },
+ { 0x3d40211c, 0x301 },
+ { 0x3d402130, 0x20300 },
+ { 0x3d402134, 0xa100002 },
+ { 0x3d402138, 0x1d },
+ { 0x3d402144, 0x14000a },
+ { 0x3d402180, 0x640004 },
+ { 0x3d402190, 0x3818200 },
+ { 0x3d402194, 0x80303 },
+ { 0x3d4021b4, 0x100 },
+ { 0x3d4020f4, 0xc99 },
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0x1f40 },
+ { 0x3d403050, 0x20d040 },
+ { 0x3d403064, 0x30007 },
+ { 0x3d4030dc, 0x840000 },
+ { 0x3d4030e0, 0x310000 },
+ { 0x3d4030e8, 0x66004d },
+ { 0x3d4030ec, 0x16004d },
+ { 0x3d403100, 0xa010102 },
+ { 0x3d403104, 0x30404 },
+ { 0x3d403108, 0x203060b },
+ { 0x3d40310c, 0x505000 },
+ { 0x3d403110, 0x2040202 },
+ { 0x3d403114, 0x2030202 },
+ { 0x3d403118, 0x1010004 },
+ { 0x3d40311c, 0x301 },
+ { 0x3d403130, 0x20300 },
+ { 0x3d403134, 0xa100002 },
+ { 0x3d403138, 0x8 },
+ { 0x3d403144, 0x50003 },
+ { 0x3d403180, 0x190004 },
+ { 0x3d403190, 0x3818200 },
+ { 0x3d403194, 0x80303 },
+ { 0x3d4031b4, 0x100 },
+ { 0x3d4030f4, 0xc99 },
+ { 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg_4gb[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x3 },
+ { 0x110a3, 0x4 },
+ { 0x110a4, 0x5 },
+ { 0x110a5, 0x2 },
+ { 0x110a6, 0x7 },
+ { 0x110a7, 0x6 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x3 },
+ { 0x120a3, 0x2 },
+ { 0x120a4, 0x5 },
+ { 0x120a5, 0x4 },
+ { 0x120a6, 0x7 },
+ { 0x120a7, 0x6 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x2ee },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x21 },
+ { 0x1200c7, 0x21 },
+ { 0x2200c7, 0x21 },
+ { 0x200ca, 0x24 },
+ { 0x1200ca, 0x24 },
+ { 0x2200ca, 0x24 },
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp2_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg_4gb[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xbb8 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4d66 },
+ { 0x5401c, 0x4d00 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4d66 },
+ { 0x54022, 0x4d00 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x4d },
+ { 0x54036, 0x4d },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x4d },
+ { 0x5403c, 0x4d },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg_4gb[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_4gb),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_4gb),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_4gb),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg_4gb,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_4gb),
+ },
+};
+
+/* lpddr4 timing config params */
+struct dram_timing_info dram_timing_4gb = {
+ .ddrc_cfg = lpddr4_ddrc_cfg_4gb,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_4gb),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg_4gb,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_4gb),
+ .fsp_msg = lpddr4_dram_fsp_msg_4gb,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_4gb),
+ .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h
new file mode 100644
index 0000000..94445f8
--- /dev/null
+++ b/board/gateworks/venice/lpddr4_timing.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef __LPDDR4_TIMING_H__
+#define __LPDDR4_TIMING_H__
+
+extern struct dram_timing_info dram_timing_1gb;
+extern struct dram_timing_info dram_timing_4gb;
+
+#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
new file mode 100644
index 0000000..cdbbc32
--- /dev/null
+++ b/board/gateworks/venice/spl.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <i2c.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+#include <asm-generic/gpio.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <power/mp5416.h>
+
+#include "gsc.h"
+#include "lpddr4_timing.h"
+
+#define PCIE_RSTN IMX_GPIO_NR(4, 6)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(int size)
+{
+ struct dram_timing_info *dram_timing;
+
+ switch (size) {
+ case 1:
+ dram_timing = &dram_timing_1gb;
+ break;
+ case 4:
+ dram_timing = &dram_timing_4gb;
+ break;
+ default:
+ printf("Unknown DDR configuration: %d GiB\n", size);
+ dram_timing = &dram_timing_1gb;
+ size = 1;
+ }
+
+ printf("DRAM    : LPDDR4 %d GiB\n", size);
+ ddr_init(dram_timing);
+ writel(size, M4_BOOTROM_BASE_ADDR);
+}
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+/* Model specific PMIC adjustments necessary prior to DRAM init */
+static int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ /* attempt to probe PMIC on GW700x SoM */
+ ret = i2c_get_chip_for_busnum(2, 0x69, 1, &dev);
+ if (ret)
+ return ret;
+ puts("PMIC    : MP5416\n");
+ /* set VDD_ARM SW3 to 0.92V for 1.6GHz */
+ pmic_reg_write(dev, MP5416_VSET_SW3,
+       BIT(7) | MP5416_VSET_SW3_SVAL(920000));
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+ int dram_sz;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
+ gpio_request(PCIE_RSTN, "perst#");
+ gpio_direction_output(PCIE_RSTN, 0);
+
+ /* GSC */
+ dram_sz = gsc_init(0);
+
+ /* PMIC */
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init(dram_sz);
+
+ board_init_r(NULL, 0);
+}
+
+/* determine prioritized order of boot devices to load U-Boot from */
+void board_boot_order(u32 *spl_boot_list)
+{
+ /*
+ * If the SPL was loaded via serial loader, we try to get
+ * U-Boot proper via USB SDP.
+ */
+ if (spl_boot_device() == BOOT_DEVICE_BOARD)
+ spl_boot_list[0] = BOOT_DEVICE_BOARD;
+
+ /* we have only eMMC in default venice dt */
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+}
+
+/* return boot device based on where the SPL was loaded from */
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ /* SDHC2 */
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ /* SDHC3 */
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
new file mode 100644
index 0000000..a15c364
--- /dev/null
+++ b/configs/imx8mm_venice_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0xff0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_VENICE=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_ENV_OFFSET_REDUND=0xff8000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_FULL=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="gsc wd-disable"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_UUID=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_SPL_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_SPL_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_PMIC_MP5416=y
+CONFIG_SPL_DM_PMIC_MP5416=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_HEXDUMP=y
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
new file mode 100644
index 0000000..a406e91
--- /dev/null
+++ b/include/configs/imx8mm_venice.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#ifndef __IMX8MM_VENICE_H
+#define __IMX8MM_VENICE_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x920000
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x930000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "fdt_addr_r=0x44000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "scriptaddr=0x46000000\0"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Enable Distro Boot */
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 2) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef CONFIG_ISO_PARTITION
+#else
+#define BOOTENV
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "bootm_size=0x10000000\0" \
+ "ipaddr=192.168.1.22\0" \
+ "serverip=192.168.1.146\0" \
+ "dev=2\0" \
+ "preboot=gsc wd-disable\0" \
+ "console=ttymxc1,115200\0" \
+ "update_firmware=" \
+ "tftpboot $loadaddr $image && " \
+ "setexpr blkcnt $filesize + 0x1ff && " \
+ "setexpr blkcnt $blkcnt / 0x200 && " \
+ "mmc dev $dev && " \
+ "mmc write $loadaddr 0x42 $blkcnt\0" \
+ "boot_net=" \
+ "tftpboot $kernel_addr_r $image && " \
+ "booti $kernel_addr_r - $fdtcontroladdr\0" \
+ "update_rootfs=" \
+ "tftpboot $loadaddr $image && " \
+ "gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
+ "update_all=" \
+ "tftpboot $loadaddr $image && " \
+ "gzwrite mmc $dev $loadaddr $filesize\0" \
+ "erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+
+/* SDRAM configuration */
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
+#define CONFIG_SYS_BOOTM_LEN SZ_256M
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE SZ_2K
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* FEC */
+#define CONFIG_ETHPRIME                 "eth0"
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define FEC_QUIRK_ENET_MAC
+#define IMX_FEC_BASE 0x30BE0000
+
+#endif
--
2.7.4

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Re: [PATCH 2/4] power: pmic: add driver for Monolithic Power mp5416

Jaehoon Chung
In reply to this post by Tim Harvey
On 1/14/21 2:00 AM, Tim Harvey wrote:

> This adds basic register access and child regulator binding
> for the Monolithic MP5416 Power Management IC which integrates
> four DC/DC switching converters and five LDO regulators.
>
> Signed-off-by: Tim Harvey <[hidden email]>
> ---
>  drivers/power/pmic/Kconfig  | 15 +++++++
>  drivers/power/pmic/Makefile |  1 +
>  drivers/power/pmic/mp5416.c | 98 +++++++++++++++++++++++++++++++++++++++++++++
>  include/power/mp5416.h      | 41 +++++++++++++++++++
>  4 files changed, 155 insertions(+)
>  create mode 100644 drivers/power/pmic/mp5416.c
>  create mode 100644 include/power/mp5416.h
>
> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> index 7d51510..583fd3d 100644
> --- a/drivers/power/pmic/Kconfig
> +++ b/drivers/power/pmic/Kconfig
> @@ -91,6 +91,21 @@ config DM_PMIC_FAN53555
>    The driver implements read/write operations for use with the FAN53555
>    regulator driver and binds the regulator driver to its node.
>  
> +config DM_PMIC_MP5416
> + bool "Enable Driver Model for PMIC MP5416"
> + depends on DM_PMIC
> + help
> +  This config enables implementation of driver-model pmic uclass features
> +  for PMIC MP5416. The driver implements read/write operations.
> +
> +config SPL_DM_PMIC_MP5416
> + bool "Enable Driver Model for PMIC MP5416 in SPL stage"
> + depends on DM_PMIC
> + help
> +  This config enables implementation of driver-model pmic uclass
> +  features for PMIC MP5416. The driver implements read/write
> +  operations.
> +
>  config DM_PMIC_PCA9450
>   bool "Enable Driver Model for PMIC PCA9450"
>   depends on DM_PMIC
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index 9cd6c37..2b2a6dd 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
>  obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
>  obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
>  obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
> +obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o
>  obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
>  obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o
>  obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
> diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c
> new file mode 100644
> index 0000000..458c4df
> --- /dev/null
> +++ b/drivers/power/pmic/mp5416.c
> @@ -0,0 +1,98 @@
> +// SPDX-License-Identifier:      GPL-2.0+
> +/*
> + * Copyright 2020 Gateworks Corporation
> + */
> +#include <common.h>
> +#include <errno.h>
> +#include <dm.h>
> +#include <i2c.h>
> +#include <log.h>
> +#include <power/pmic.h>
> +#include <power/regulator.h>
> +#include <power/mp5416.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct pmic_child_info pmic_children_info[] = {
> + /* buck */
> + { .prefix = "b", .driver = MP6416_REGULATOR_DRIVER },
> + /* ldo */
> + { .prefix = "l", .driver = MP6416_REGULATOR_DRIVER },
> + { },
> +};
> +
> +static int mp5416_reg_count(struct udevice *dev)
> +{
> + return MP5416_NUM_OF_REGS - 1;
> +}
> +
> +static int mp5416_write(struct udevice *dev, uint reg, const uint8_t *buff,
> + int len)
> +{
> + if (dm_i2c_write(dev, reg, buff, len)) {
> + pr_err("write error to device: %p register: %#x!", dev, reg);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int mp5416_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
> +{
> + if (dm_i2c_read(dev, reg, buff, len)) {
> + pr_err("read error from device: %p register: %#x!", dev, reg);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int mp5416_bind(struct udevice *dev)
> +{
> + int children;
> + ofnode regulators_node;
> +
> + debug("%s %s\n", __func__, dev->name);
> + regulators_node = dev_read_subnode(dev, "regulators");
> + if (!ofnode_valid(regulators_node)) {
> + debug("%s: %s regulators subnode not found!\n", __func__,
> +      dev->name);
> + return -ENXIO;
> + }
> +
> + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
> +
> + children = pmic_bind_children(dev, regulators_node, pmic_children_info);
> + if (!children)
> + debug("%s: %s - no child found\n", __func__, dev->name);
> +
> + /* Always return success for this device */
> + return 0;
> +}
> +
> +static int mp5416_probe(struct udevice *dev)
> +{
> + debug("%s %s\n", __func__, dev->name);
> +
> + return 0;
> +}
> +
> +static struct dm_pmic_ops mp5416_ops = {
> + .reg_count = mp5416_reg_count,
> + .read = mp5416_read,
> + .write = mp5416_write,
> +};
> +
> +static const struct udevice_id mp5416_ids[] = {
> + { .compatible = "mps,mp5416", },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pmic_mp5416) = {
> + .name = "mp5416 pmic",
> + .id = UCLASS_PMIC,
> + .of_match = mp5416_ids,
> + .bind = mp5416_bind,
> + .probe = mp5416_probe,
> + .ops = &mp5416_ops,
> +};
> diff --git a/include/power/mp5416.h b/include/power/mp5416.h
> new file mode 100644
> index 0000000..dc096fe
> --- /dev/null
> +++ b/include/power/mp5416.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/* Copyright (C) 2020 Gateworks Corporation */
> +
> +#ifndef MP5416_H_
> +#define MP5416_H_
> +
> +#define MP6416_REGULATOR_DRIVER "mp5416_regulator"
> +
> +enum {
> + MP5416_CTL0 = 0x00,
> + MP5416_CTL1 = 0x01,
> + MP5416_CTL2 = 0x02,
> + MP5416_ILIMIT = 0x03,
> + MP5416_VSET_SW1 = 0x04,
> + MP5416_VSET_SW2 = 0x05,
> + MP5416_VSET_SW3 = 0x06,
> + MP5416_VSET_SW4 = 0x07,
> + MP5416_VSET_LDO2 = 0x08,
> + MP5416_VSET_LDO3 = 0x09,
> + MP5416_VSET_LDO4 = 0x0a,
> + MP5416_VSET_LDO5 = 0x0b,
> + MP5416_STATUS1 = 0x0d,
> + MP5416_STATUS2 = 0x0e,
> + MP5416_STATUS3 = 0x0f,
> + MP5416_ID2 = 0x11,
> + MP5416_NUM_OF_REGS = 0x12,
> +};
> +
> +#define MP5416_VSET_EN          BIT(7)
> +#define MP5416_VSET_SW1_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
> +#define MP5416_VSET_SW2_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> +#define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
> +#define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> +#define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> +#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> +#define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500)
> +#define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000)
> +#define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500)
> +#define MP5416_VSET_SW4_SVAL(x) (((x) - 800000) / 25000)

I didn't find where above macros are used, except MP5416_VSET_SW3_SVAL().

Best Regards,
Jaehoon Chung

> +
> +#endif
>

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Re: [PATCH 2/4] power: pmic: add driver for Monolithic Power mp5416

Tim Harvey
On Thu, Jan 14, 2021 at 2:07 PM Jaehoon Chung <[hidden email]> wrote:

>
> On 1/14/21 2:00 AM, Tim Harvey wrote:
> > This adds basic register access and child regulator binding
> > for the Monolithic MP5416 Power Management IC which integrates
> > four DC/DC switching converters and five LDO regulators.
> >
> > Signed-off-by: Tim Harvey <[hidden email]>
> > ---
> >  drivers/power/pmic/Kconfig  | 15 +++++++
> >  drivers/power/pmic/Makefile |  1 +
> >  drivers/power/pmic/mp5416.c | 98 +++++++++++++++++++++++++++++++++++++++++++++
> >  include/power/mp5416.h      | 41 +++++++++++++++++++
> >  4 files changed, 155 insertions(+)
> >  create mode 100644 drivers/power/pmic/mp5416.c
> >  create mode 100644 include/power/mp5416.h
> >
> > diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> > index 7d51510..583fd3d 100644
> > --- a/drivers/power/pmic/Kconfig
> > +++ b/drivers/power/pmic/Kconfig
> > @@ -91,6 +91,21 @@ config DM_PMIC_FAN53555
> >         The driver implements read/write operations for use with the FAN53555
> >         regulator driver and binds the regulator driver to its node.
> >
> > +config DM_PMIC_MP5416
> > +     bool "Enable Driver Model for PMIC MP5416"
> > +     depends on DM_PMIC
> > +     help
> > +       This config enables implementation of driver-model pmic uclass features
> > +       for PMIC MP5416. The driver implements read/write operations.
> > +
> > +config SPL_DM_PMIC_MP5416
> > +     bool "Enable Driver Model for PMIC MP5416 in SPL stage"
> > +     depends on DM_PMIC
> > +     help
> > +       This config enables implementation of driver-model pmic uclass
> > +       features for PMIC MP5416. The driver implements read/write
> > +       operations.
> > +
> >  config DM_PMIC_PCA9450
> >       bool "Enable Driver Model for PMIC PCA9450"
> >       depends on DM_PMIC
> > diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> > index 9cd6c37..2b2a6dd 100644
> > --- a/drivers/power/pmic/Makefile
> > +++ b/drivers/power/pmic/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
> >  obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
> >  obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
> >  obj-$(CONFIG_$(SPL_)DM_PMIC_BD71837) += bd71837.o
> > +obj-$(CONFIG_$(SPL_)DM_PMIC_MP5416) += mp5416.o
> >  obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
> >  obj-$(CONFIG_$(SPL_)DM_PMIC_PCA9450) += pca9450.o
> >  obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
> > diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c
> > new file mode 100644
> > index 0000000..458c4df
> > --- /dev/null
> > +++ b/drivers/power/pmic/mp5416.c
> > @@ -0,0 +1,98 @@
> > +// SPDX-License-Identifier:      GPL-2.0+
> > +/*
> > + * Copyright 2020 Gateworks Corporation
> > + */
> > +#include <common.h>
> > +#include <errno.h>
> > +#include <dm.h>
> > +#include <i2c.h>
> > +#include <log.h>
> > +#include <power/pmic.h>
> > +#include <power/regulator.h>
> > +#include <power/mp5416.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static const struct pmic_child_info pmic_children_info[] = {
> > +     /* buck */
> > +     { .prefix = "b", .driver = MP6416_REGULATOR_DRIVER },
> > +     /* ldo */
> > +     { .prefix = "l", .driver = MP6416_REGULATOR_DRIVER },
> > +     { },
> > +};
> > +
> > +static int mp5416_reg_count(struct udevice *dev)
> > +{
> > +     return MP5416_NUM_OF_REGS - 1;
> > +}
> > +
> > +static int mp5416_write(struct udevice *dev, uint reg, const uint8_t *buff,
> > +                     int len)
> > +{
> > +     if (dm_i2c_write(dev, reg, buff, len)) {
> > +             pr_err("write error to device: %p register: %#x!", dev, reg);
> > +             return -EIO;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int mp5416_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
> > +{
> > +     if (dm_i2c_read(dev, reg, buff, len)) {
> > +             pr_err("read error from device: %p register: %#x!", dev, reg);
> > +             return -EIO;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> > +static int mp5416_bind(struct udevice *dev)
> > +{
> > +     int children;
> > +     ofnode regulators_node;
> > +
> > +     debug("%s %s\n", __func__, dev->name);
> > +     regulators_node = dev_read_subnode(dev, "regulators");
> > +     if (!ofnode_valid(regulators_node)) {
> > +             debug("%s: %s regulators subnode not found!\n", __func__,
> > +                   dev->name);
> > +             return -ENXIO;
> > +     }
> > +
> > +     debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
> > +
> > +     children = pmic_bind_children(dev, regulators_node, pmic_children_info);
> > +     if (!children)
> > +             debug("%s: %s - no child found\n", __func__, dev->name);
> > +
> > +     /* Always return success for this device */
> > +     return 0;
> > +}
> > +
> > +static int mp5416_probe(struct udevice *dev)
> > +{
> > +     debug("%s %s\n", __func__, dev->name);
> > +
> > +     return 0;
> > +}
> > +
> > +static struct dm_pmic_ops mp5416_ops = {
> > +     .reg_count = mp5416_reg_count,
> > +     .read = mp5416_read,
> > +     .write = mp5416_write,
> > +};
> > +
> > +static const struct udevice_id mp5416_ids[] = {
> > +     { .compatible = "mps,mp5416", },
> > +     { }
> > +};
> > +
> > +U_BOOT_DRIVER(pmic_mp5416) = {
> > +     .name = "mp5416 pmic",
> > +     .id = UCLASS_PMIC,
> > +     .of_match = mp5416_ids,
> > +     .bind = mp5416_bind,
> > +     .probe = mp5416_probe,
> > +     .ops = &mp5416_ops,
> > +};
> > diff --git a/include/power/mp5416.h b/include/power/mp5416.h
> > new file mode 100644
> > index 0000000..dc096fe
> > --- /dev/null
> > +++ b/include/power/mp5416.h
> > @@ -0,0 +1,41 @@
> > +/* SPDX-License-Identifier: GPL-2.0-or-later */
> > +/* Copyright (C) 2020 Gateworks Corporation */
> > +
> > +#ifndef MP5416_H_
> > +#define MP5416_H_
> > +
> > +#define MP6416_REGULATOR_DRIVER "mp5416_regulator"
> > +
> > +enum {
> > +     MP5416_CTL0             = 0x00,
> > +     MP5416_CTL1             = 0x01,
> > +     MP5416_CTL2             = 0x02,
> > +     MP5416_ILIMIT           = 0x03,
> > +     MP5416_VSET_SW1         = 0x04,
> > +     MP5416_VSET_SW2         = 0x05,
> > +     MP5416_VSET_SW3         = 0x06,
> > +     MP5416_VSET_SW4         = 0x07,
> > +     MP5416_VSET_LDO2        = 0x08,
> > +     MP5416_VSET_LDO3        = 0x09,
> > +     MP5416_VSET_LDO4        = 0x0a,
> > +     MP5416_VSET_LDO5        = 0x0b,
> > +     MP5416_STATUS1          = 0x0d,
> > +     MP5416_STATUS2          = 0x0e,
> > +     MP5416_STATUS3          = 0x0f,
> > +     MP5416_ID2              = 0x11,
> > +     MP5416_NUM_OF_REGS      = 0x12,
> > +};
> > +
> > +#define MP5416_VSET_EN          BIT(7)
> > +#define MP5416_VSET_SW1_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
> > +#define MP5416_VSET_SW2_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> > +#define MP5416_VSET_SW3_GVAL(x) ((((x) & 0x7f) * 12500) + 600000)
> > +#define MP5416_VSET_SW4_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> > +#define MP5416_VSET_LDO_GVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> > +#define MP5416_VSET_LDO_SVAL(x) ((((x) & 0x7f) * 25000) + 800000)
> > +#define MP5416_VSET_SW1_SVAL(x) (((x) - 600000) / 12500)
> > +#define MP5416_VSET_SW2_SVAL(x) (((x) - 800000) / 25000)
> > +#define MP5416_VSET_SW3_SVAL(x) (((x) - 600000) / 12500)
> > +#define MP5416_VSET_SW4_SVAL(x) (((x) - 800000) / 25000)
>
> I didn't find where above macros are used, except MP5416_VSET_SW3_SVAL().
>

Jaehoon,

Thanks for the review!

Correct, the venice board support only requires MP5416_VSET_SW3_SVAL
currently but I figured if I needed to go to the trouble of creating a
pmic driver I would expose all the functionality for future users. Is
this not the right thing to do?

Best regards,

Tim
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Re: [PATCH 1/4] Respect that some compression algos can be enabled separately for SPL

sbabic
In reply to this post by Tim Harvey
Hi Tim,

there is a weird side effect with this patch, breaking m68k
architecture. For some reason, image.c is not compiled clean because gd
is not declared anymore.

In file included from tools/common/image.c:1:
./tools/../common/image.c: In function ‘get_table_entry_id’:
./tools/../common/image.c:982:41: error: ‘gd’ undeclared (first use in
this function)
  982 |   if (t->sname && strcasecmp(t->sname + gd->reloc_off, name) == 0)
      |                                         ^~
./tools/../common/image.c:982:41: note: each undeclared identifier is
reported only once for each functi

Can you take a look ? Thanks !

Best regards,
Stefano

On 13.01.21 18:00, Tim Harvey wrote:

> From: Frieder Schrempf <[hidden email]>
>
> Some compression algorithms currently can be enabled for SPL and
> U-Boot proper separately. Therefore we need to use
> CONFIG_IS_ENABLED() in these cases and also prevent compiling these
> functions in case of a host tool build.
>
> Signed-off-by: Frieder Schrempf <[hidden email]
> Signed-off-by: Tim Harvey <[hidden email]>
> ---
>  common/image.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/common/image.c b/common/image.c
> index 451fc68..bda19c0 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -72,6 +72,7 @@ static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
>  
>  #include <u-boot/crc.h>
>  #include <imximage.h>
> +#include <linux/kconfig.h>
>  
>  #ifndef CONFIG_SYS_BARGSIZE
>  #define CONFIG_SYS_BARGSIZE 512
> @@ -460,13 +461,13 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
>   else
>   ret = -ENOSPC;
>   break;
> -#ifdef CONFIG_GZIP
> +#if CONFIG_IS_ENABLED(GZIP) && !defined(USE_HOSTCC)
>   case IH_COMP_GZIP: {
>   ret = gunzip(load_buf, unc_len, image_buf, &image_len);
>   break;
>   }
>  #endif /* CONFIG_GZIP */
> -#ifdef CONFIG_BZIP2
> +#if CONFIG_IS_ENABLED(BZIP2) && !defined(USE_HOSTCC)
>   case IH_COMP_BZIP2: {
>   uint size = unc_len;
>  
> @@ -482,7 +483,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
>   break;
>   }
>  #endif /* CONFIG_BZIP2 */
> -#ifdef CONFIG_LZMA
> +#if CONFIG_IS_ENABLED(LZMA) && !defined(USE_HOSTCC)
>   case IH_COMP_LZMA: {
>   SizeT lzma_len = unc_len;
>  
> @@ -492,7 +493,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
>   break;
>   }
>  #endif /* CONFIG_LZMA */
> -#ifdef CONFIG_LZO
> +#if CONFIG_IS_ENABLED(LZO) && !defined(USE_HOSTCC)
>   case IH_COMP_LZO: {
>   size_t size = unc_len;
>  
> @@ -501,7 +502,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
>   break;
>   }
>  #endif /* CONFIG_LZO */
> -#ifdef CONFIG_LZ4
> +#if CONFIG_IS_ENABLED(LZ4) && !defined(USE_HOSTCC)
>   case IH_COMP_LZ4: {
>   size_t size = unc_len;
>  
> @@ -510,7 +511,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
>   break;
>   }
>  #endif /* CONFIG_LZ4 */
> -#ifdef CONFIG_ZSTD
> +#if CONFIG_IS_ENABLED(ZSTD) && !defined(USE_HOSTCC)
>   case IH_COMP_ZSTD: {
>   size_t size = unc_len;
>   ZSTD_DStream *dstream;
>


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