[PATCH 0/3] RISC-V tracing support

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[PATCH 0/3] RISC-V tracing support

Pragnesh Patel
This series add a support of tracing for RISC-V arch.

This series is also available here [1] for testing.
Series depends on [2].

[1] https://github.com/pragnesh26992/u-boot/tree/trace
[2] https://patchwork.ozlabs.org/project/uboot/cover/20200729095636.1077054-1-seanga2@.../

How to test this patch:
1) Enable tracing in "configs/sifive_fu540_defconfig"
CONFIG_TRACE=y
CONFIG_TRACE_BUFFER_SIZE=0x01000000
CONFIG_TRACE_CALL_DEPTH_LIMIT=15
CONFIG_CMD_TRACE=y

2) make FTRACE=1 sifive_fu540_defconfig
3) make FTRACE=1

Following are the boot messages on FU540 five cores SMP platform:

U-Boot 2020.10-rc1-02837-g8613dc2e66 (Aug 24 2020 - 20:03:47 +0530)

CPU:   rv64imac
Model: SiFive HiFive Unleashed A00
DRAM:  8 GiB
trace: enabled
MMC:   spi@10050000:mmc@0: 0
Loading Environment from SPIFlash... SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
OK
In:    serial@10010000
Out:   serial@10010000
Err:   serial@10010000
Board serial number should not be 0 !!
Net:
Warning: ethernet@10090000 (eth0) using random MAC address - 92:a1:a7:02:5a:14
eth0: ethernet@10090000
Hit any key to stop autoboot:  0
=> trace stats
        177,722 function sites
     37,057,350 function calls
              1 untracked function calls
      1,279,612 traced function calls (36015585 dropped due to overflow)
             19 maximum observed call depth
             15 call depth limit
     37,055,565 calls not traced due to depth
=>


Pragnesh Patel (3):
  riscv: Add timer_get_us() for tracing
  riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with
    'notrace'
  riscv: Mark andes_plmt_get_count() with 'notrace'

 arch/riscv/lib/Makefile       |  1 +
 arch/riscv/lib/andes_plmt.c   |  2 +-
 arch/riscv/lib/sifive_clint.c |  2 +-
 arch/riscv/lib/timer.c        | 50 +++++++++++++++++++++++++++++++++++
 drivers/timer/riscv_timer.c   |  2 +-
 5 files changed, 54 insertions(+), 3 deletions(-)
 create mode 100644 arch/riscv/lib/timer.c

--
2.17.1

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[PATCH 1/3] riscv: Add timer_get_us() for tracing

Pragnesh Patel
timer_get_us() will use timer_ops->get_count() function for timer counter.
For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer counter and
For M-mode U-Boot, mtime register will provide the same.

Signed-off-by: Pragnesh Patel <[hidden email]>
---
 arch/riscv/lib/Makefile |  1 +
 arch/riscv/lib/timer.c  | 50 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 arch/riscv/lib/timer.c

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 10ac5b06d3..fbb68e583b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -26,6 +26,7 @@ obj-y   += setjmp.o
 obj-$(CONFIG_$(SPL_)SMP) += smp.o
 obj-$(CONFIG_SPL_BUILD) += spl.o
 obj-y   += fdt_fixup.o
+obj-$(CONFIG_TIMER) += timer.o
 
 # For building EFI apps
 CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
diff --git a/arch/riscv/lib/timer.c b/arch/riscv/lib/timer.c
new file mode 100644
index 0000000000..3e423f2805
--- /dev/null
+++ b/arch/riscv/lib/timer.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <[hidden email]>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct udevice *timer;
+
+ulong notrace timer_get_us(void)
+{
+ u64 count;
+ ulong rate;
+ int ret;
+
+ /**
+ * gd->timer will become NULL in initr_dm(), so assign gd->timer
+ * to other static global timer, so that timer_get_us() can use it.
+ */
+ if (!timer && gd->timer)
+ timer = (struct udevice *)gd->timer;
+
+ if (timer) {
+ ret = timer_get_count(timer, &count);
+ if (ret)
+ return ret;
+
+ rate = timer_get_rate(timer);
+ }
+
+ return (ulong)count / rate;
+}
+
+int timer_init(void)
+{
+ int ret;
+
+ ret = dm_timer_init();
+ if (ret)
+ return ret;
+
+ return 0;
+}
--
2.17.1

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[PATCH 2/3] riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with 'notrace'

Pragnesh Patel
In reply to this post by Pragnesh Patel
Mark them as 'notrace' so that it doesn't cause infinite recursion.

Signed-off-by: Pragnesh Patel <[hidden email]>
---
 arch/riscv/lib/sifive_clint.c | 2 +-
 drivers/timer/riscv_timer.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index 3345a17ad2..1cf74a6cf4 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -62,7 +62,7 @@ int riscv_get_ipi(int hart, int *pending)
  return 0;
 }
 
-static int sifive_clint_get_count(struct udevice *dev, u64 *count)
+static int notrace sifive_clint_get_count(struct udevice *dev, u64 *count)
 {
  *count = readq((void __iomem *)MTIME_REG(dev->priv));
 
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 449fcfcfd5..342e0354dc 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@
 #include <timer.h>
 #include <asm/csr.h>
 
-static int riscv_timer_get_count(struct udevice *dev, u64 *count)
+static int notrace riscv_timer_get_count(struct udevice *dev, u64 *count)
 {
  if (IS_ENABLED(CONFIG_64BIT)) {
  *count = csr_read(CSR_TIME);
--
2.17.1

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[PATCH 3/3] riscv: Mark andes_plmt_get_count() with 'notrace'

Pragnesh Patel
In reply to this post by Pragnesh Patel
For M-mode U-boot, andes_plmt_get_count() will provide timer counter.
Mark it as 'notrace' so that it doesn't cause infinite recursion.

Signed-off-by: Pragnesh Patel <[hidden email]>
---
 arch/riscv/lib/andes_plmt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
index b0245d0b52..488a98406b 100644
--- a/arch/riscv/lib/andes_plmt.c
+++ b/arch/riscv/lib/andes_plmt.c
@@ -17,7 +17,7 @@
 /* mtime register */
 #define MTIME_REG(base) ((ulong)(base))
 
-static int andes_plmt_get_count(struct udevice *dev, u64 *count)
+static int notrace andes_plmt_get_count(struct udevice *dev, u64 *count)
 {
  *count = readq((void __iomem *)MTIME_REG(dev->priv));
 
--
2.17.1

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Re: [PATCH 0/3] RISC-V tracing support

Sean Anderson
In reply to this post by Pragnesh Patel
On 8/24/20 10:44 AM, Pragnesh Patel wrote:

> This series add a support of tracing for RISC-V arch.
>
> This series is also available here [1] for testing.
> Series depends on [2].
>
> [1] https://github.com/pragnesh26992/u-boot/tree/trace
> [2] https://patchwork.ozlabs.org/project/uboot/cover/20200729095636.1077054-1-seanga2@.../
>
> How to test this patch:
> 1) Enable tracing in "configs/sifive_fu540_defconfig"
> CONFIG_TRACE=y
> CONFIG_TRACE_BUFFER_SIZE=0x01000000
> CONFIG_TRACE_CALL_DEPTH_LIMIT=15
> CONFIG_CMD_TRACE=y
>
> 2) make FTRACE=1 sifive_fu540_defconfig
> 3) make FTRACE=1
>
> Following are the boot messages on FU540 five cores SMP platform:
>
> U-Boot 2020.10-rc1-02837-g8613dc2e66 (Aug 24 2020 - 20:03:47 +0530)
>
> CPU:   rv64imac
> Model: SiFive HiFive Unleashed A00
> DRAM:  8 GiB
> trace: enabled
> MMC:   spi@10050000:mmc@0: 0
> Loading Environment from SPIFlash... SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
> OK
> In:    serial@10010000
> Out:   serial@10010000
> Err:   serial@10010000
> Board serial number should not be 0 !!
> Net:
> Warning: ethernet@10090000 (eth0) using random MAC address - 92:a1:a7:02:5a:14
> eth0: ethernet@10090000
> Hit any key to stop autoboot:  0
> => trace stats
>         177,722 function sites
>      37,057,350 function calls
>               1 untracked function calls
>       1,279,612 traced function calls (36015585 dropped due to overflow)
>              19 maximum observed call depth
>              15 call depth limit
>      37,055,565 calls not traced due to depth
> =>
>
>
> Pragnesh Patel (3):
>   riscv: Add timer_get_us() for tracing
>   riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with
>     'notrace'
>   riscv: Mark andes_plmt_get_count() with 'notrace'
>
>  arch/riscv/lib/Makefile       |  1 +
>  arch/riscv/lib/andes_plmt.c   |  2 +-
>  arch/riscv/lib/sifive_clint.c |  2 +-
>  arch/riscv/lib/timer.c        | 50 +++++++++++++++++++++++++++++++++++
>  drivers/timer/riscv_timer.c   |  2 +-
>  5 files changed, 54 insertions(+), 3 deletions(-)
>  create mode 100644 arch/riscv/lib/timer.c
>

Tested-by: Sean Anderson <[hidden email]>

I tested this on a K210 and had to reduce CONFIG_TRACE_BUFFER_SIZE to
0x100000 (1M) because of its reduced ram. Here is some example output:

U-Boot 2020.10-rc1-00164-gbb14d962f5 (Sep 01 2020 - 16:17:43 -0400)

DRAM:  8 MiB
trace: enabled
In:    serial@38000000
Out:   serial@38000000
Err:   serial@38000000
=> trace stats
         76,948 function sites
     82,375,426 function calls
              1 untracked function calls
         36,075 traced function calls (164135507 dropped due to overflow)
             17 maximum observed call depth
             15 call depth limit
        679,059 calls not traced due to depth
=>

--Sean
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Re: [PATCH 0/3] RISC-V tracing support

Rick Chen
In reply to this post by Pragnesh Patel
> From: Pragnesh Patel [mailto:[hidden email]]
> Sent: Monday, August 24, 2020 10:44 PM
> To: [hidden email]; [hidden email]; [hidden email]; [hidden email]; [hidden email]; Rick Jian-Zhi Chen(陳建志)
> Cc: [hidden email]; Pragnesh Patel
> Subject: [PATCH 0/3] RISC-V tracing support
>
> This series add a support of tracing for RISC-V arch.
>
> This series is also available here [1] for testing.
> Series depends on [2].
>
> [1] https://github.com/pragnesh26992/u-boot/tree/trace
> [2] https://patchwork.ozlabs.org/project/uboot/cover/20200729095636.1077054-1-seanga2@.../
>
> How to test this patch:
> 1) Enable tracing in "configs/sifive_fu540_defconfig"
> CONFIG_TRACE=y
> CONFIG_TRACE_BUFFER_SIZE=0x01000000
> CONFIG_TRACE_CALL_DEPTH_LIMIT=15
> CONFIG_CMD_TRACE=y
>
> 2) make FTRACE=1 sifive_fu540_defconfig
> 3) make FTRACE=1
>
> Following are the boot messages on FU540 five cores SMP platform:
>
> U-Boot 2020.10-rc1-02837-g8613dc2e66 (Aug 24 2020 - 20:03:47 +0530)
>
> CPU:   rv64imac
> Model: SiFive HiFive Unleashed A00
> DRAM:  8 GiB
> trace: enabled
> MMC:   spi@10050000:mmc@0: 0
> Loading Environment from SPIFlash... SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB
> OK
> In:    serial@10010000
> Out:   serial@10010000
> Err:   serial@10010000
> Board serial number should not be 0 !!
> Net:
> Warning: ethernet@10090000 (eth0) using random MAC address - 92:a1:a7:02:5a:14
> eth0: ethernet@10090000
> Hit any key to stop autoboot:  0
> => trace stats
>         177,722 function sites
>      37,057,350 function calls
>               1 untracked function calls
>       1,279,612 traced function calls (36015585 dropped due to overflow)
>              19 maximum observed call depth
>              15 call depth limit
>      37,055,565 calls not traced due to depth
> =>
>
>
> Pragnesh Patel (3):
>   riscv: Add timer_get_us() for tracing
>   riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with
>     'notrace'
>   riscv: Mark andes_plmt_get_count() with 'notrace'
>
>  arch/riscv/lib/Makefile       |  1 +
>  arch/riscv/lib/andes_plmt.c   |  2 +-
>  arch/riscv/lib/sifive_clint.c |  2 +-
>  arch/riscv/lib/timer.c        | 50 +++++++++++++++++++++++++++++++++++
>  drivers/timer/riscv_timer.c   |  2 +-
>  5 files changed, 54 insertions(+), 3 deletions(-)
>  create mode 100644 arch/riscv/lib/timer.c
>
> --

Tested-by: Rick Chen <[hidden email]>

I have verified it in AE350 platfom as below:

U-Boot 2020.10-rc1-05918-g658fb7e-dirty (Sep 03 2020 - 08:08:28 +0800)

DRAM:  1 GiB
trace: enabled
Flash: 64 MiB
MMC:   mmc@f0e00000: 0
Loading Environment from SPIFlash... SF: Detected mx25u1635e with page
size 256 Bytes, erase size 4 KiB, total 2 MiB
OK
In:    serial@f0300000
Out:   serial@f0300000
Err:   serial@f0300000
Net:   no alias for ethernet0

Warning: mac@e0100000 (eth0) using random MAC address - 2a:6c:3c:57:4b:30
eth0: mac@e0100000
Hit any key to stop autoboot:  0
RISC-V #
RISC-V # trace stats
        166,074 function sites
      1,071,417 function calls
              1 untracked function calls
      1,030,665 traced function calls
             19 maximum observed call depth
             15 call depth limit
      1,145,728 calls not traced due to depth

RISC-V # trace stats
        166,074 function sites
      2,552,905 function calls
              1 untracked function calls
      1,287,378 traced function calls (958047 dropped due to overflow)
             19 maximum observed call depth
             15 call depth limit
      2,900,311 calls not traced due to depth
RISC-V #

Thanks,
Rick
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Re: [PATCH 1/3] riscv: Add timer_get_us() for tracing

Bin Meng-2
In reply to this post by Pragnesh Patel
Hi Pragnesh,

On Mon, Aug 24, 2020 at 10:45 PM Pragnesh Patel
<[hidden email]> wrote:

>
> timer_get_us() will use timer_ops->get_count() function for timer counter.
> For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer counter and
> For M-mode U-Boot, mtime register will provide the same.
>
> Signed-off-by: Pragnesh Patel <[hidden email]>
> ---
>  arch/riscv/lib/Makefile |  1 +
>  arch/riscv/lib/timer.c  | 50 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 51 insertions(+)
>  create mode 100644 arch/riscv/lib/timer.c
>
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index 10ac5b06d3..fbb68e583b 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -26,6 +26,7 @@ obj-y   += setjmp.o
>  obj-$(CONFIG_$(SPL_)SMP) += smp.o
>  obj-$(CONFIG_SPL_BUILD)        += spl.o
>  obj-y   += fdt_fixup.o
> +obj-$(CONFIG_TIMER) += timer.o
>
>  # For building EFI apps
>  CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
> diff --git a/arch/riscv/lib/timer.c b/arch/riscv/lib/timer.c
> new file mode 100644
> index 0000000000..3e423f2805
> --- /dev/null
> +++ b/arch/riscv/lib/timer.c
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 SiFive, Inc
> + *
> + * Authors:
> + *   Pragnesh Patel <[hidden email]>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <timer.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct udevice *timer;
> +
> +ulong notrace timer_get_us(void)

Does the weak one in lib/time.c not work on RISC-V?

> +{
> +       u64 count;
> +       ulong rate;
> +       int ret;
> +
> +       /**
> +        * gd->timer will become NULL in initr_dm(), so assign gd->timer
> +        * to other static global timer, so that timer_get_us() can use it.
> +        */
> +       if (!timer && gd->timer)
> +               timer = (struct udevice *)gd->timer;
> +
> +       if (timer) {
> +               ret = timer_get_count(timer, &count);
> +               if (ret)
> +                       return ret;
> +
> +               rate = timer_get_rate(timer);
> +       }
> +
> +       return (ulong)count / rate;
> +}
> +
> +int timer_init(void)

Why is this function necessary?

> +{
> +       int ret;
> +
> +       ret = dm_timer_init();

Does enabling CONFIG_TIMER_EARLY help?

> +       if (ret)
> +               return ret;
> +
> +       return 0;
> +}

Regards,
Bin
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Re: [PATCH 1/3] riscv: Add timer_get_us() for tracing

Rick Chen
Hi Pragnesh

> From: Bin Meng [mailto:[hidden email]]
> Sent: Friday, September 11, 2020 2:48 PM
> To: Pragnesh Patel
> Cc: U-Boot Mailing List; Atish Patra; Anup Patel; Sagar Kadam; Rick Jian-Zhi Chen(陳建志); Paul Walmsley; Bin Meng; Lukas Auer; Sean Anderson
> Subject: Re: [PATCH 1/3] riscv: Add timer_get_us() for tracing
>
> Hi Pragnesh,
>
> On Mon, Aug 24, 2020 at 10:45 PM Pragnesh Patel
> <[hidden email]> wrote:
> >
> > timer_get_us() will use timer_ops->get_count() function for timer counter.
> > For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer counter and
> > For M-mode U-Boot, mtime register will provide the same.
> >
> > Signed-off-by: Pragnesh Patel <[hidden email]>
> > ---
> >  arch/riscv/lib/Makefile |  1 +
> >  arch/riscv/lib/timer.c  | 50 +++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 51 insertions(+)
> >  create mode 100644 arch/riscv/lib/timer.c
> >
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index 10ac5b06d3..fbb68e583b 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -26,6 +26,7 @@ obj-y   += setjmp.o
> >  obj-$(CONFIG_$(SPL_)SMP) += smp.o
> >  obj-$(CONFIG_SPL_BUILD)        += spl.o
> >  obj-y   += fdt_fixup.o
> > +obj-$(CONFIG_TIMER) += timer.o
> >
> >  # For building EFI apps
> >  CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
> > diff --git a/arch/riscv/lib/timer.c b/arch/riscv/lib/timer.c
> > new file mode 100644
> > index 0000000000..3e423f2805
> > --- /dev/null
> > +++ b/arch/riscv/lib/timer.c
> > @@ -0,0 +1,50 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2020 SiFive, Inc
> > + *
> > + * Authors:
> > + *   Pragnesh Patel <[hidden email]>
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <timer.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +static struct udevice *timer;
> > +
> > +ulong notrace timer_get_us(void)
>
> Does the weak one in lib/time.c not work on RISC-V?

Do you have any comments about Bin's reply ?

Thanks,
Rick

>
> > +{
> > +       u64 count;
> > +       ulong rate;
> > +       int ret;
> > +
> > +       /**
> > +        * gd->timer will become NULL in initr_dm(), so assign gd->timer
> > +        * to other static global timer, so that timer_get_us() can use it.
> > +        */
> > +       if (!timer && gd->timer)
> > +               timer = (struct udevice *)gd->timer;
> > +
> > +       if (timer) {
> > +               ret = timer_get_count(timer, &count);
> > +               if (ret)
> > +                       return ret;
> > +
> > +               rate = timer_get_rate(timer);
> > +       }
> > +
> > +       return (ulong)count / rate;
> > +}
> > +
> > +int timer_init(void)
>
> Why is this function necessary?
>
> > +{
> > +       int ret;
> > +
> > +       ret = dm_timer_init();
>
> Does enabling CONFIG_TIMER_EARLY help?
>
> > +       if (ret)
> > +               return ret;
> > +
> > +       return 0;
> > +}
>
> Regards,
> Bin
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RE: [PATCH 1/3] riscv: Add timer_get_us() for tracing

Pragnesh Patel-2
Hi Bin,

>-----Original Message-----
>From: Rick Chen <[hidden email]>
>Sent: 21 October 2020 08:58
>To: Pragnesh Patel <[hidden email]>
>Cc: U-Boot Mailing List <[hidden email]>; Atish Patra
><[hidden email]>; Anup Patel <[hidden email]>; Sagar Kadam
><[hidden email]>; Bin Meng <[hidden email]>; Lukas Auer
><[hidden email]>; Sean Anderson <[hidden email]>; rick
><[hidden email]>; Alan Kao <[hidden email]>
>Subject: Re: [PATCH 1/3] riscv: Add timer_get_us() for tracing
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>Hi Pragnesh
>
>> From: Bin Meng [mailto:[hidden email]]
>> Sent: Friday, September 11, 2020 2:48 PM
>> To: Pragnesh Patel
>> Cc: U-Boot Mailing List; Atish Patra; Anup Patel; Sagar Kadam; Rick
>> Jian-Zhi Chen(陳建志); Paul Walmsley; Bin Meng; Lukas Auer; Sean Anderson
>> Subject: Re: [PATCH 1/3] riscv: Add timer_get_us() for tracing
>>
>> Hi Pragnesh,
>>
>> On Mon, Aug 24, 2020 at 10:45 PM Pragnesh Patel
>> <[hidden email]> wrote:
>> >
>> > timer_get_us() will use timer_ops->get_count() function for timer counter.
>> > For S-mode U-Boot, CSR_TIMEH and CSR_TIME will provide a timer
>> > counter and For M-mode U-Boot, mtime register will provide the same.
>> >
>> > Signed-off-by: Pragnesh Patel <[hidden email]>
>> > ---
>> >  arch/riscv/lib/Makefile |  1 +
>> >  arch/riscv/lib/timer.c  | 50
>> > +++++++++++++++++++++++++++++++++++++++++
>> >  2 files changed, 51 insertions(+)
>> >  create mode 100644 arch/riscv/lib/timer.c
>> >
>> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
>> > 10ac5b06d3..fbb68e583b 100644
>> > --- a/arch/riscv/lib/Makefile
>> > +++ b/arch/riscv/lib/Makefile
>> > @@ -26,6 +26,7 @@ obj-y   += setjmp.o
>> >  obj-$(CONFIG_$(SPL_)SMP) += smp.o
>> >  obj-$(CONFIG_SPL_BUILD)        += spl.o
>> >  obj-y   += fdt_fixup.o
>> > +obj-$(CONFIG_TIMER) += timer.o
>> >
>> >  # For building EFI apps
>> >  CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) diff --git
>> > a/arch/riscv/lib/timer.c b/arch/riscv/lib/timer.c new file mode
>> > 100644 index 0000000000..3e423f2805
>> > --- /dev/null
>> > +++ b/arch/riscv/lib/timer.c
>> > @@ -0,0 +1,50 @@
>> > +// SPDX-License-Identifier: GPL-2.0+
>> > +/*
>> > + * Copyright (C) 2020 SiFive, Inc
>> > + *
>> > + * Authors:
>> > + *   Pragnesh Patel <[hidden email]>
>> > + */
>> > +
>> > +#include <common.h>
>> > +#include <dm.h>
>> > +#include <timer.h>
>> > +
>> > +DECLARE_GLOBAL_DATA_PTR;
>> > +
>> > +static struct udevice *timer;
>> > +
>> > +ulong notrace timer_get_us(void)
>>
>> Does the weak one in lib/time.c not work on RISC-V?

No because if "gd->timer" is set early then also it will become NULL in initr_dm()

static int initr_dm(void) {
...
#ifdef CONFIG_TIMER
        gd->timer = NULL;
#endif
...
}

So timer_get_us() again try to call dm_timer_init() to initialize "gd->timer" and it got stuck in tracing.

Not all the functins are marked with notrace in dm_timer_init().

>
>Do you have any comments about Bin's reply ?
>
>Thanks,
>Rick
>
>>
>> > +{
>> > +       u64 count;
>> > +       ulong rate;
>> > +       int ret;
>> > +
>> > +       /**
>> > +        * gd->timer will become NULL in initr_dm(), so assign gd->timer
>> > +        * to other static global timer, so that timer_get_us() can use it.
>> > +        */
>> > +       if (!timer && gd->timer)
>> > +               timer = (struct udevice *)gd->timer;
>> > +
>> > +       if (timer) {
>> > +               ret = timer_get_count(timer, &count);
>> > +               if (ret)
>> > +                       return ret;
>> > +
>> > +               rate = timer_get_rate(timer);
>> > +       }
>> > +
>> > +       return (ulong)count / rate;
>> > +}
>> > +
>> > +int timer_init(void)
>>
>> Why is this function necessary?
>>
>> > +{
>> > +       int ret;
>> > +
>> > +       ret = dm_timer_init();
>>
>> Does enabling CONFIG_TIMER_EARLY help?

I need to implement timer_early_get_count() and timer_early_get_rate() for that. Will look into this

>>
>> > +       if (ret)
>> > +               return ret;
>> > +
>> > +       return 0;
>> > +}
>>
>> Regards,
>> Bin