[PATCH 0/3] PowerPC: keymile: Add support for kmcent2 board

classic Classic list List threaded Threaded
4 messages Options
Reply | Threaded
Open this post in threaded view
|

[PATCH 0/3] PowerPC: keymile: Add support for kmcent2 board

Niel Fourie
This patch series adds basic support for the Hitachi Power Grids
(previously Keymile and ABB) kmcent2 board, based on the NXP QorIQ
T1040 SoC.

Patch 1/3 pulls in the device trees from Linux 5.10
Patch 2/3 fixes a minor bug common to all the Keymile boards.
Patch 3/3 finally adds the U-boot support for the kmcent2

Niel Fourie (3):
  PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10
  keymile: common: Fix pram variable radix
  PowerPC: keymile: Add support for kmcent2 board

 arch/powerpc/cpu/mpc85xx/Kconfig       |   4 +
 arch/powerpc/dts/Makefile              |   1 +
 arch/powerpc/dts/elo3-dma-0.dtsi       |  55 ++
 arch/powerpc/dts/elo3-dma-1.dtsi       |  55 ++
 arch/powerpc/dts/kmcent2-u-boot.dtsi   |  97 ++++
 arch/powerpc/dts/kmcent2.dts           | 338 ++++++++++++
 arch/powerpc/dts/qoriq-bman1.dtsi      |  14 +
 arch/powerpc/dts/qoriq-duart-0.dtsi    |  24 +
 arch/powerpc/dts/qoriq-duart-1.dtsi    |  24 +
 arch/powerpc/dts/qoriq-esdhc-0.dtsi    |  13 +
 arch/powerpc/dts/qoriq-espi-0.dtsi     |  14 +
 arch/powerpc/dts/qoriq-mpic.dtsi       |  79 +++
 arch/powerpc/dts/qoriq-qman3.dtsi      |  14 +
 arch/powerpc/dts/qoriq-sata2-0.dtsi    |  12 +
 arch/powerpc/dts/qoriq-sata2-1.dtsi    |  12 +
 arch/powerpc/dts/qoriq-sec5.0-0.dtsi   |  83 +++
 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi  |  14 +
 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi |  14 +
 arch/powerpc/dts/t1040si-post.dtsi     | 727 +++++++++++++++++++++++++
 arch/powerpc/dts/t104xsi-pre.dtsi      |  88 +++
 board/keymile/Kconfig                  |   1 +
 board/keymile/common/common.c          |   2 +-
 board/keymile/common/ivm.c             |   5 +
 board/keymile/kmcent2/Kconfig          |  17 +
 board/keymile/kmcent2/MAINTAINERS      |   8 +
 board/keymile/kmcent2/Makefile         |  15 +
 board/keymile/kmcent2/ddr.c            |  88 +++
 board/keymile/kmcent2/kmcent2.c        | 349 ++++++++++++
 board/keymile/kmcent2/law.c            |  40 ++
 board/keymile/kmcent2/tlb.c            | 120 ++++
 configs/kmcent2_defconfig              |  90 +++
 include/configs/kmcent2.h              | 537 ++++++++++++++++++
 32 files changed, 2953 insertions(+), 1 deletion(-)
 create mode 100644 arch/powerpc/dts/elo3-dma-0.dtsi
 create mode 100644 arch/powerpc/dts/elo3-dma-1.dtsi
 create mode 100644 arch/powerpc/dts/kmcent2-u-boot.dtsi
 create mode 100644 arch/powerpc/dts/kmcent2.dts
 create mode 100644 arch/powerpc/dts/qoriq-bman1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-esdhc-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-espi-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-mpic.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-qman3.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sec5.0-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
 create mode 100644 arch/powerpc/dts/t1040si-post.dtsi
 create mode 100644 arch/powerpc/dts/t104xsi-pre.dtsi
 create mode 100644 board/keymile/kmcent2/Kconfig
 create mode 100644 board/keymile/kmcent2/MAINTAINERS
 create mode 100644 board/keymile/kmcent2/Makefile
 create mode 100644 board/keymile/kmcent2/ddr.c
 create mode 100644 board/keymile/kmcent2/kmcent2.c
 create mode 100644 board/keymile/kmcent2/law.c
 create mode 100644 board/keymile/kmcent2/tlb.c
 create mode 100644 configs/kmcent2_defconfig
 create mode 100644 include/configs/kmcent2.h

--
2.29.2

Reply | Threaded
Open this post in threaded view
|

[PATCH 1/3] PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10

Niel Fourie
Pulled in the kmcent2.dts and all its dependents from Linux 5.10,
commit 2c85ebc57b3e upstream. Replaced the license text with
SPDX License Identifiers.

Signed-off-by: Niel Fourie <[hidden email]>
Cc: Holger Brunck <[hidden email]>
Cc: Heiko Schocher <[hidden email]>
Cc: Priyanka Jain <[hidden email]>
---
 arch/powerpc/dts/elo3-dma-0.dtsi       |  55 ++
 arch/powerpc/dts/elo3-dma-1.dtsi       |  55 ++
 arch/powerpc/dts/kmcent2.dts           | 338 ++++++++++++
 arch/powerpc/dts/qoriq-bman1.dtsi      |  14 +
 arch/powerpc/dts/qoriq-duart-0.dtsi    |  24 +
 arch/powerpc/dts/qoriq-duart-1.dtsi    |  24 +
 arch/powerpc/dts/qoriq-esdhc-0.dtsi    |  13 +
 arch/powerpc/dts/qoriq-espi-0.dtsi     |  14 +
 arch/powerpc/dts/qoriq-mpic.dtsi       |  79 +++
 arch/powerpc/dts/qoriq-qman3.dtsi      |  14 +
 arch/powerpc/dts/qoriq-sata2-0.dtsi    |  12 +
 arch/powerpc/dts/qoriq-sata2-1.dtsi    |  12 +
 arch/powerpc/dts/qoriq-sec5.0-0.dtsi   |  83 +++
 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi  |  14 +
 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi |  14 +
 arch/powerpc/dts/t1040si-post.dtsi     | 727 +++++++++++++++++++++++++
 arch/powerpc/dts/t104xsi-pre.dtsi      |  88 +++
 17 files changed, 1580 insertions(+)
 create mode 100644 arch/powerpc/dts/elo3-dma-0.dtsi
 create mode 100644 arch/powerpc/dts/elo3-dma-1.dtsi
 create mode 100644 arch/powerpc/dts/kmcent2.dts
 create mode 100644 arch/powerpc/dts/qoriq-bman1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-esdhc-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-espi-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-mpic.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-qman3.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sec5.0-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
 create mode 100644 arch/powerpc/dts/t1040si-post.dtsi
 create mode 100644 arch/powerpc/dts/t104xsi-pre.dtsi

diff --git a/arch/powerpc/dts/elo3-dma-0.dtsi b/arch/powerpc/dts/elo3-dma-0.dtsi
new file mode 100644
index 0000000000..c3f7737256
--- /dev/null
+++ b/arch/powerpc/dts/elo3-dma-0.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma0: dma@100300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elo3-dma";
+ reg = <0x100300 0x4>,
+      <0x100600 0x4>;
+ ranges = <0x0 0x100100 0x500>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ interrupts = <28 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ interrupts = <29 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ interrupts = <30 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ interrupts = <31 2 0 0>;
+ };
+ dma-channel@300 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x300 0x80>;
+ interrupts = <76 2 0 0>;
+ };
+ dma-channel@380 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x380 0x80>;
+ interrupts = <77 2 0 0>;
+ };
+ dma-channel@400 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x400 0x80>;
+ interrupts = <78 2 0 0>;
+ };
+ dma-channel@480 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x480 0x80>;
+ interrupts = <79 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/elo3-dma-1.dtsi b/arch/powerpc/dts/elo3-dma-1.dtsi
new file mode 100644
index 0000000000..a61c88649c
--- /dev/null
+++ b/arch/powerpc/dts/elo3-dma-1.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma1: dma@101300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elo3-dma";
+ reg = <0x101300 0x4>,
+      <0x101600 0x4>;
+ ranges = <0x0 0x101100 0x500>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ interrupts = <32 2 0 0>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ interrupts = <33 2 0 0>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ interrupts = <34 2 0 0>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ interrupts = <35 2 0 0>;
+ };
+ dma-channel@300 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x300 0x80>;
+ interrupts = <80 2 0 0>;
+ };
+ dma-channel@380 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x380 0x80>;
+ interrupts = <81 2 0 0>;
+ };
+ dma-channel@400 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x400 0x80>;
+ interrupts = <82 2 0 0>;
+ };
+ dma-channel@480 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x480 0x80>;
+ interrupts = <83 2 0 0>;
+ };
+};
diff --git a/arch/powerpc/dts/kmcent2.dts b/arch/powerpc/dts/kmcent2.dts
new file mode 100644
index 0000000000..5d23ecb34b
--- /dev/null
+++ b/arch/powerpc/dts/kmcent2.dts
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
+ *
+ * (C) Copyright 2016
+ * Valentin Longchamp, Keymile AG, [hidden email]
+ *
+ * Copyright 2014 - 2015 Freescale Semiconductor Inc.
+ */
+
+/include/ "t104xsi-pre.dtsi"
+
+/ {
+ model = "keymile,kmcent2";
+ compatible = "keymile,kmcent2";
+
+ aliases {
+ front_phy = &front_phy;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ bman_fbpr: bman-fbpr {
+ size = <0 0x1000000>;
+ alignment = <0 0x1000000>;
+ };
+ qman_fqd: qman-fqd {
+ size = <0 0x400000>;
+ alignment = <0 0x400000>;
+ };
+ qman_pfdr: qman-pfdr {
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ };
+ };
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe8000000 0x04000000
+  1 0 0xf 0xfa000000 0x00010000
+  2 0 0xf 0xfb000000 0x00010000
+  4 0 0xf 0xc0000000 0x08000000
+  6 0 0xf 0xd0000000 0x08000000
+  7 0 0xf 0xd8000000 0x08000000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x04000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x1 0x0 0x10000>;
+ };
+
+ board-control@2,0 {
+ compatible = "keymile,qriox";
+ reg = <0x2 0x0 0x80>;
+ };
+
+ chassis-mgmt@6,0 {
+ compatible = "keymile,bfticu";
+ reg = <6 0 0x100>;
+ interrupt-controller;
+ interrupt-parent = <&mpic>;
+ interrupts = <11 1 0 0>;
+ #interrupt-cells = <1>;
+ };
+
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ dcsr: dcsr@f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01072000>;
+ };
+
+ bportals: bman-portals@ff4000000 {
+ ranges = <0x0 0xf 0xf4000000 0x2000000>;
+ };
+
+ qportals: qman-portals@ff6000000 {
+ ranges = <0x0 0xf 0xf6000000 0x2000000>;
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ spi@110000 {
+ network-clock@1 {
+ compatible = "zarlink,zl30364";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+
+ sdhc@114000 {
+ status = "disabled";
+ };
+
+ i2c@118000 {
+ clock-frequency = <100000>;
+
+ mux@70 {
+ compatible = "nxp,pca9547";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-mux-idle-disconnect;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@54 {
+ compatible = "atmel,24c02";
+ reg = <0x54>;
+ pagesize = <2>;
+ read-only;
+ label = "ddr3-spd";
+ };
+ };
+
+ i2c@7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ temp-sensor@48 {
+ compatible = "national,lm75";
+ reg = <0x48>;
+ label = "SENSOR_0";
+ };
+ temp-sensor@4a {
+ compatible = "national,lm75";
+ reg = <0x4a>;
+ label = "SENSOR_2";
+ };
+ temp-sensor@4b {
+ compatible = "national,lm75";
+ reg = <0x4b>;
+ label = "SENSOR_3";
+ };
+ };
+ };
+ };
+
+ i2c@118100 {
+ clock-frequency = <100000>;
+
+ eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+ };
+
+ i2c@119000 {
+ status = "disabled";
+ };
+
+ i2c@119100 {
+ status = "disabled";
+ };
+
+ serial2: serial@11d500 {
+ status = "disabled";
+ };
+
+ serial3: serial@11d600 {
+ status = "disabled";
+ };
+
+ usb0: usb@210000 {
+ status = "disabled";
+ };
+ usb1: usb@211000 {
+ status = "disabled";
+ };
+
+ display@180000 {
+ status = "disabled";
+ };
+
+ sata@220000 {
+ status = "disabled";
+ };
+ sata@221000 {
+ status = "disabled";
+ };
+
+ fman@400000 {
+ ethernet@e0000 {
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet@e2000 {
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ ethernet@e4000 {
+ status = "disabled";
+ };
+
+ ethernet@e6000 {
+ status = "disabled";
+ };
+
+ ethernet@e8000 {
+ phy-handle = <&front_phy>;
+ phy-mode = "rgmii-id";
+ };
+
+ mdio0: mdio@fc000 {
+ front_phy: ethernet-phy@11 {
+ reg = <0x11>;
+ };
+ };
+ };
+ };
+
+ pci0: pcie@ffe240000 {
+ reg = <0xf 0xfe240000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+  0x02000000 0 0xe0000000
+  0 0x20000000
+
+  0x01000000 0 0x00000000
+  0x01000000 0 0x00000000
+  0 0x00010000>;
+ };
+ };
+
+ pci1: pcie@ffe250000 {
+ status = "disabled";
+ reg = <0xf 0xfe250000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
+  0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+  0x02000000 0 0xe0000000
+  0 0x10000000
+
+  0x01000000 0 0x00000000
+  0x01000000 0 0x00000000
+  0 0x00010000>;
+ };
+ };
+
+ pci2: pcie@ffe260000 {
+ status = "disabled";
+ reg = <0xf 0xfe260000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
+  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+  0x02000000 0 0xe0000000
+  0 0x10000000
+
+  0x01000000 0 0x00000000
+  0x01000000 0 0x00000000
+  0 0x00010000>;
+ };
+ };
+
+ pci3: pcie@ffe270000 {
+ status = "disabled";
+ reg = <0xf 0xfe270000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
+  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+  0x02000000 0 0xe0000000
+  0 0x10000000
+
+  0x01000000 0 0x00000000
+  0x01000000 0 0x00000000
+  0 0x00010000>;
+ };
+ };
+
+ qe: qe@ffe140000 {
+ ranges = <0x0 0xf 0xfe140000 0x40000>;
+ reg = <0xf 0xfe140000 0 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <0>;
+
+ si1: si@700 {
+ compatible = "fsl,t1040-qe-si";
+ reg = <0x700 0x80>;
+ };
+
+ siram1: siram@1000 {
+ compatible = "fsl,t1040-qe-siram";
+ reg = <0x1000 0x800>;
+ };
+
+ ucc_hdlc: ucc@2000 {
+ device_type = "hdlc";
+ compatible = "fsl,ucc-hdlc";
+ rx-clock-name = "clk9";
+ tx-clock-name = "clk9";
+ fsl,hdlc-bus;
+ };
+ };
+};
+
+#include "t1040si-post.dtsi"
diff --git a/arch/powerpc/dts/qoriq-bman1.dtsi b/arch/powerpc/dts/qoriq-bman1.dtsi
new file mode 100644
index 0000000000..d6164bac8a
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-bman1.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ BMan device tree stub [ controller @ offset 0x31a000 ]
+ *
+ * Copyright 2011 - 2014 Freescale Semiconductor Inc.
+ */
+
+bman: bman@31a000 {
+ compatible = "fsl,bman";
+ reg = <0x31a000 0x1000>;
+ interrupts = <16 2 1 2>;
+ fsl,bman-portals = <&bportals>;
+ memory-region = <&bman_fbpr>;
+};
diff --git a/arch/powerpc/dts/qoriq-duart-0.dtsi b/arch/powerpc/dts/qoriq-duart-0.dtsi
new file mode 100644
index 0000000000..0ac4843840
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-duart-0.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+serial0: serial@11c500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11c500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+};
+
+serial1: serial@11c600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11c600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <36 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-duart-1.dtsi b/arch/powerpc/dts/qoriq-duart-1.dtsi
new file mode 100644
index 0000000000..c712146aa6
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-duart-1.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+serial2: serial@11d500 {
+ cell-index = <2>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11d500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+};
+
+serial3: serial@11d600 {
+ cell-index = <3>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x11d600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <37 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-esdhc-0.dtsi b/arch/powerpc/dts/qoriq-esdhc-0.dtsi
new file mode 100644
index 0000000000..dd24a49095
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-esdhc-0.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sdhc: sdhc@114000 {
+ compatible = "fsl,esdhc";
+ reg = <0x114000 0x1000>;
+ interrupts = <48 2 0 0>;
+ clock-frequency = <0>;
+};
diff --git a/arch/powerpc/dts/qoriq-espi-0.dtsi b/arch/powerpc/dts/qoriq-espi-0.dtsi
new file mode 100644
index 0000000000..e87e6dd49b
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-espi-0.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+spi@110000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc8536-espi";
+ reg = <0x110000 0x1000>;
+ interrupts = <53 0x2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-mpic.dtsi b/arch/powerpc/dts/qoriq-mpic.dtsi
new file mode 100644
index 0000000000..bec7c04e69
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-mpic.dtsi
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic", "chrp,open-pic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+};
+
+timer@41100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x41100 0x100 0x41300 4>;
+ interrupts = <0 0 3 0
+      1 0 3 0
+      2 0 3 0
+      3 0 3 0>;
+};
+
+msi0: msi@41600 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200 0x44140 4>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+};
+
+msi1: msi@41800 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41800 0x200 0x45140 4>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0>;
+};
+
+msi2: msi@41a00 {
+ compatible = "fsl,mpic-msi";
+ reg = <0x41a00 0x200 0x46140 4>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0>;
+};
+
+timer@42100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x42100 0x100 0x42300 4>;
+ interrupts = <4 0 3 0
+      5 0 3 0
+      6 0 3 0
+      7 0 3 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-qman3.dtsi b/arch/powerpc/dts/qoriq-qman3.dtsi
new file mode 100644
index 0000000000..b1f8a777a2
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-qman3.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ QMan rev3 device tree stub [ controller @ offset 0x318000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ */
+
+qman: qman@318000 {
+ compatible = "fsl,qman";
+ reg = <0x318000 0x2000>;
+ interrupts = <16 2 1 3>;
+ fsl,qman-portals = <&qportals>;
+ memory-region = <&qman_fqd &qman_pfdr>;
+};
diff --git a/arch/powerpc/dts/qoriq-sata2-0.dtsi b/arch/powerpc/dts/qoriq-sata2-0.dtsi
new file mode 100644
index 0000000000..385b91784d
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sata2-0.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sata@220000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x220000 0x1000>;
+ interrupts = <68 0x2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sata2-1.dtsi b/arch/powerpc/dts/qoriq-sata2-1.dtsi
new file mode 100644
index 0000000000..d72dd39e02
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sata2-1.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+sata@221000 {
+ compatible = "fsl,pq-sata-v2";
+ reg = <0x221000 0x1000>;
+ interrupts = <69 0x2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec5.0-0.dtsi b/arch/powerpc/dts/qoriq-sec5.0-0.dtsi
new file mode 100644
index 0000000000..af0bb9dd6e
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec5.0-0.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <5>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+     "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+     "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+     "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+     "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v5.0-rtic",
+     "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+     "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+     "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+     "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v5.0-rtic-memory",
+     "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi b/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
new file mode 100644
index 0000000000..ee135c67ca
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+usb@211000 {
+ compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ reg = <0x211000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <45 0x2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi b/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
new file mode 100644
index 0000000000..8579cc1e06
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+usb@210000 {
+ compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ reg = <0x210000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <44 0x2 0 0>;
+};
diff --git a/arch/powerpc/dts/t1040si-post.dtsi b/arch/powerpc/dts/t1040si-post.dtsi
new file mode 100644
index 0000000000..c71cf33f8a
--- /dev/null
+++ b/arch/powerpc/dts/t1040si-post.dtsi
@@ -0,0 +1,727 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * T1040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2013 - 2014 Freescale Semiconductor Inc.
+ */
+
+#include <dt-bindings/thermal/thermal.h>
+
+&bman_fbpr {
+ compatible = "fsl,bman-fbpr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&qman_fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&qman_pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0x10000 0>;
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc", "simple-bus";
+ interrupts = <25 2 0 0>;
+};
+
+&pci0 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ interrupts = <20 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <20 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+};
+
+&pci1 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0 0xff>;
+ interrupts = <21 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <21 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ };
+};
+
+&pci2 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ interrupts = <22 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <22 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ };
+};
+
+&pci3 {
+ compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ interrupts = <23 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <23 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 43 1 0 0
+ 0000 0 0 2 &mpic 0 1 0 0
+ 0000 0 0 3 &mpic 4 1 0 0
+ 0000 0 0 4 &mpic 8 1 0 0
+ >;
+ };
+};
+
+&dcsr {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+
+ dcsr-epu@0 {
+ compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
+ interrupts = <52 2 0 0
+      84 2 0 0
+      85 2 0 0>;
+ reg = <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
+ reg = <0x1000 0x1000 0x1002000 0x10000>;
+ };
+ dcsr-nxc@2000 {
+ compatible = "fsl,dcsr-nxc";
+ reg = <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible = "fsl,dcsr-corenet";
+ reg = <0x8000 0x1000 0x1A000 0x1000>;
+ };
+ dcsr-dpaa@9000 {
+ compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg = <0x9000 0x1000>;
+ };
+ dcsr-ocn@11000 {
+ compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
+ reg = <0x11000 0x1000>;
+ };
+ dcsr-ddr@12000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr1>;
+ reg = <0x12000 0x1000>;
+ };
+ dcsr-nal@18000 {
+ compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
+ reg = <0x18000 0x1000>;
+ };
+ dcsr-rcpm@22000 {
+ compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg = <0x22000 0x1000>;
+ };
+ dcsr-snpc@30000 {
+ compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+ reg = <0x30000 0x1000 0x1022000 0x10000>;
+ };
+ dcsr-snpc@31000 {
+ compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
+ reg = <0x31000 0x1000 0x1042000 0x10000>;
+ };
+ dcsr-cpu-sb-proxy@100000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu0>;
+ reg = <0x100000 0x1000 0x101000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@108000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x108000 0x1000 0x109000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@110000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu2>;
+ reg = <0x110000 0x1000 0x111000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@118000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu3>;
+ reg = <0x118000 0x1000 0x119000 0x1000>;
+ };
+};
+
+&bportals {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "simple-bus";
+
+ bman-portal@0 {
+ compatible = "fsl,bman-portal";
+ reg = <0x0 0x4000>, <0x1000000 0x1000>;
+ interrupts = <105 2 0 0>;
+ };
+ bman-portal@4000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+ interrupts = <107 2 0 0>;
+ };
+ bman-portal@8000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+ interrupts = <109 2 0 0>;
+ };
+ bman-portal@c000 {
+ compatible = "fsl,bman-portal";
+ reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+ interrupts = <111 2 0 0>;
+ };
+ bman-portal@10000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+ interrupts = <113 2 0 0>;
+ };
+ bman-portal@14000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+ interrupts = <115 2 0 0>;
+ };
+ bman-portal@18000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+ interrupts = <117 2 0 0>;
+ };
+ bman-portal@1c000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+ interrupts = <119 2 0 0>;
+ };
+ bman-portal@20000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+ interrupts = <121 2 0 0>;
+ };
+ bman-portal@24000 {
+ compatible = "fsl,bman-portal";
+ reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+ interrupts = <123 2 0 0>;
+ };
+};
+
+&qportals {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "simple-bus";
+
+ qportal0: qman-portal@0 {
+ compatible = "fsl,qman-portal";
+ reg = <0x0 0x4000>, <0x1000000 0x1000>;
+ interrupts = <104 0x2 0 0>;
+ cell-index = <0x0>;
+ };
+ qportal1: qman-portal@4000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x4000 0x4000>, <0x1001000 0x1000>;
+ interrupts = <106 0x2 0 0>;
+ cell-index = <0x1>;
+ };
+ qportal2: qman-portal@8000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x8000 0x4000>, <0x1002000 0x1000>;
+ interrupts = <108 0x2 0 0>;
+ cell-index = <0x2>;
+ };
+ qportal3: qman-portal@c000 {
+ compatible = "fsl,qman-portal";
+ reg = <0xc000 0x4000>, <0x1003000 0x1000>;
+ interrupts = <110 0x2 0 0>;
+ cell-index = <0x3>;
+ };
+ qportal4: qman-portal@10000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x10000 0x4000>, <0x1004000 0x1000>;
+ interrupts = <112 0x2 0 0>;
+ cell-index = <0x4>;
+ };
+ qportal5: qman-portal@14000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x14000 0x4000>, <0x1005000 0x1000>;
+ interrupts = <114 0x2 0 0>;
+ cell-index = <0x5>;
+ };
+ qportal6: qman-portal@18000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x18000 0x4000>, <0x1006000 0x1000>;
+ interrupts = <116 0x2 0 0>;
+ cell-index = <0x6>;
+ };
+ qportal7: qman-portal@1c000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
+ interrupts = <118 0x2 0 0>;
+ cell-index = <0x7>;
+ };
+ qportal8: qman-portal@20000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x20000 0x4000>, <0x1008000 0x1000>;
+ interrupts = <120 0x2 0 0>;
+ cell-index = <0x8>;
+ };
+ qportal9: qman-portal@24000 {
+ compatible = "fsl,qman-portal";
+ reg = <0x24000 0x4000>, <0x1009000 0x1000>;
+ interrupts = <122 0x2 0 0>;
+ cell-index = <0x9>;
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <16>;
+ };
+
+ ddr1: memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v5.0",
+ "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,t1040-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000>;
+ interrupts = <16 2 1 27>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x1000>;
+ ranges = <0 0x20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ pamu0: pamu@0 {
+ reg = <0 0x1000>;
+ fsl,primary-cache-geometry = <128 1>;
+ fsl,secondary-cache-geometry = <16 2>;
+ };
+ };
+
+/include/ "qoriq-mpic.dtsi"
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ fsl,liodn-bits = <12>;
+ };
+
+/include/ "qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
+ compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.1";
+ reg = <0xe2000 0x1000>;
+ };
+
+ sfp: sfp@e8000 {
+ compatible = "fsl,t1040-sfp";
+ reg   = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes@ea000 {
+ compatible = "fsl,t1040-serdes";
+ reg   = <0xea000 0x4000>;
+ };
+
+ tmu: tmu@f0000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0xf0000 0x1000>;
+ interrupts = <18 2 0 0>;
+ fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
+ fsl,tmu-calibration = <0x00000000 0x00000025
+       0x00000001 0x00000028
+       0x00000002 0x0000002d
+       0x00000003 0x00000031
+       0x00000004 0x00000036
+       0x00000005 0x0000003a
+       0x00000006 0x00000040
+       0x00000007 0x00000044
+       0x00000008 0x0000004a
+       0x00000009 0x0000004f
+       0x0000000a 0x00000054
+
+       0x00010000 0x0000000d
+       0x00010001 0x00000013
+       0x00010002 0x00000019
+       0x00010003 0x0000001f
+       0x00010004 0x00000025
+       0x00010005 0x0000002d
+       0x00010006 0x00000033
+       0x00010007 0x00000043
+       0x00010008 0x0000004b
+       0x00010009 0x00000053
+
+       0x00020000 0x00000010
+       0x00020001 0x00000017
+       0x00020002 0x0000001f
+       0x00020003 0x00000029
+       0x00020004 0x00000031
+       0x00020005 0x0000003c
+       0x00020006 0x00000042
+       0x00020007 0x0000004d
+       0x00020008 0x00000056
+
+       0x00030000 0x00000012
+       0x00030001 0x0000001d>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu1 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map2 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu2 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ map3 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu3 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ scfg: global-utilities@fc000 {
+ compatible = "fsl,t1040-scfg";
+ reg = <0xfc000 0x1000>;
+ };
+
+/include/ "elo3-dma-0.dtsi"
+/include/ "elo3-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+ spi@110000 {
+ fsl,espi-num-chipselects = <4>;
+ };
+
+/include/ "qoriq-esdhc-0.dtsi"
+ sdhc@114000 {
+ compatible = "fsl,t1040-esdhc", "fsl,esdhc";
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
+ sdhci,auto-cmd12;
+ };
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-gpio-1.dtsi"
+/include/ "qoriq-gpio-2.dtsi"
+/include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+ usb0: usb@210000 {
+ compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
+ phy_type = "utmi";
+ port0;
+ };
+/include/ "qoriq-usb2-dr-0.dtsi"
+ usb1: usb@211000 {
+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+ display@180000 {
+ compatible = "fsl,t1040-diu", "fsl,diu";
+ reg = <0x180000 1000>;
+ interrupts = <74 2 0 0>;
+ };
+
+/include/ "qoriq-sata2-0.dtsi"
+ sata@220000 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
+ };
+/include/ "qoriq-sata2-1.dtsi"
+ sata@221000 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
+ };
+/include/ "qoriq-sec5.0-0.dtsi"
+/include/ "qoriq-qman3.dtsi"
+/include/ "qoriq-bman1.dtsi"
+
+/include/ "qoriq-fman3l-0.dtsi"
+/include/ "qoriq-fman3-0-1g-0.dtsi"
+/include/ "qoriq-fman3-0-1g-1.dtsi"
+/include/ "qoriq-fman3-0-1g-2.dtsi"
+/include/ "qoriq-fman3-0-1g-3.dtsi"
+/include/ "qoriq-fman3-0-1g-4.dtsi"
+ fman@400000 {
+ enet0: ethernet@e0000 {
+ };
+
+ enet1: ethernet@e2000 {
+ };
+
+ enet2: ethernet@e4000 {
+ };
+
+ enet3: ethernet@e6000 {
+ };
+
+ enet4: ethernet@e8000 {
+ };
+
+ mdio@fc000 {
+ interrupts = <100 1 0 0>;
+ };
+
+ mdio@fd000 {
+ status = "disabled";
+ };
+ };
+
+ seville_switch: ethernet-switch@800000 {
+ compatible = "mscc,vsc9953-switch";
+ reg = <0x800000 0x290000>;
+ interrupts = <26 2 0 0>;
+ interrupt-names = "xtr";
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ seville_port0: port@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ seville_port1: port@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+
+ seville_port2: port@2 {
+ reg = <2>;
+ status = "disabled";
+ };
+
+ seville_port3: port@3 {
+ reg = <3>;
+ status = "disabled";
+ };
+
+ seville_port4: port@4 {
+ reg = <4>;
+ status = "disabled";
+ };
+
+ seville_port5: port@5 {
+ reg = <5>;
+ status = "disabled";
+ };
+
+ seville_port6: port@6 {
+ reg = <6>;
+ status = "disabled";
+ };
+
+ seville_port7: port@7 {
+ reg = <7>;
+ status = "disabled";
+ };
+
+ seville_port8: port@8 {
+ reg = <8>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+
+ seville_port9: port@9 {
+ reg = <9>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+
+&qe {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ interrupts = <95 2 0 0  94 2 0 0>; //high:79 low:78
+ };
+
+ ucc@2000 {
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ };
+
+ ucc@2200 {
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ interrupts = <34>;
+ interrupt-parent = <&qeic>;
+ };
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x10000 0x6000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0x6000>;
+ };
+ };
+};
diff --git a/arch/powerpc/dts/t104xsi-pre.dtsi b/arch/powerpc/dts/t104xsi-pre.dtsi
new file mode 100644
index 0000000000..025872cfea
--- /dev/null
+++ b/arch/powerpc/dts/t104xsi-pre.dtsi
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * T1040/T1042 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2013-2014 Freescale Semiconductor Inc.
+ */
+
+/dts-v1/;
+
+/include/ "e5500_power_isa.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+ dcsr = &dcsr;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ pci3 = &pci3;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ sdhc = &sdhc;
+
+ crypto = &crypto;
+
+ fman0 = &fman0;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&clockgen 1 0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ clocks = <&clockgen 1 1>;
+ next-level-cache = <&L2_2>;
+ #cooling-cells = <2>;
+ L2_2: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type = "cpu";
+ reg = <2>;
+ clocks = <&clockgen 1 2>;
+ next-level-cache = <&L2_3>;
+ #cooling-cells = <2>;
+ L2_3: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type = "cpu";
+ reg = <3>;
+ clocks = <&clockgen 1 3>;
+ next-level-cache = <&L2_4>;
+ #cooling-cells = <2>;
+ L2_4: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+};
--
2.29.2


Reply | Threaded
Open this post in threaded view
|

[PATCH 2/3] keymile: common: Fix pram variable radix

Niel Fourie
In reply to this post by Niel Fourie
In set_km_env() the pram variable was set to an hexadecimal value,
while initr_mem() expects an unsigned decimal. Set the pram variable
to an unsigned decimal instead.

Signed-off-by: Niel Fourie <[hidden email]>
Cc: Holger Brunck <[hidden email]>
Cc: Heiko Schocher <[hidden email]>
Cc: Priyanka Jain <[hidden email]>
---
 board/keymile/common/common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 03c7ce9da7..106787efd5 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -60,7 +60,7 @@ int set_km_env(void)
  strict_strtoul(p, 16, &rootfssize);
  pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
  CONFIG_KM_PNVRAM) / 0x400;
- sprintf((char *)buf, "0x%x", pram);
+ sprintf((char *)buf, "%u", pram);
  env_set("pram", (char *)buf);
 
  varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
--
2.29.2

Reply | Threaded
Open this post in threaded view
|

[PATCH 3/3] PowerPC: keymile: Add support for kmcent2 board

Niel Fourie
In reply to this post by Niel Fourie
Add basic support for the Hitachi Power Grids kmcent2 board, based
on the NXP QorIQ T1040 SoC.

Signed-off-by: Valentin Longchamp <[hidden email]>
Signed-off-by: Rainer Boschung <[hidden email]>
Signed-off-by: Niel Fourie <[hidden email]>
Cc: Holger Brunck <[hidden email]>
Cc: Heiko Schocher <[hidden email]>
Cc: Priyanka Jain <[hidden email]>
---
 arch/powerpc/cpu/mpc85xx/Kconfig     |   4 +
 arch/powerpc/dts/Makefile            |   1 +
 arch/powerpc/dts/kmcent2-u-boot.dtsi |  97 +++++
 board/keymile/Kconfig                |   1 +
 board/keymile/common/ivm.c           |   5 +
 board/keymile/kmcent2/Kconfig        |  17 +
 board/keymile/kmcent2/MAINTAINERS    |   8 +
 board/keymile/kmcent2/Makefile       |  15 +
 board/keymile/kmcent2/ddr.c          |  88 +++++
 board/keymile/kmcent2/kmcent2.c      | 349 +++++++++++++++++
 board/keymile/kmcent2/law.c          |  40 ++
 board/keymile/kmcent2/tlb.c          | 120 ++++++
 configs/kmcent2_defconfig            |  90 +++++
 include/configs/kmcent2.h            | 537 +++++++++++++++++++++++++++
 14 files changed, 1372 insertions(+)
 create mode 100644 arch/powerpc/dts/kmcent2-u-boot.dtsi
 create mode 100644 board/keymile/kmcent2/Kconfig
 create mode 100644 board/keymile/kmcent2/MAINTAINERS
 create mode 100644 board/keymile/kmcent2/Makefile
 create mode 100644 board/keymile/kmcent2/ddr.c
 create mode 100644 board/keymile/kmcent2/kmcent2.c
 create mode 100644 board/keymile/kmcent2/law.c
 create mode 100644 board/keymile/kmcent2/tlb.c
 create mode 100644 configs/kmcent2_defconfig
 create mode 100644 include/configs/kmcent2.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 54c7fd9522..c1a3770671 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -256,6 +256,10 @@ config TARGET_KMP204X
  bool "Support kmp204x"
  select VENDOR_KM
 
+config TARGET_KMCENT2
+ bool "Support kmcent2"
+ select VENDOR_KM
+
 config TARGET_XPEDITE520X
  bool "Support xpedite520x"
  select ARCH_MPC8548
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 266d345f72..3ecda36538 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb
 dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
 dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
 dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi
new file mode 100644
index 0000000000..ab76a9f122
--- /dev/null
+++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2021  Niel Fourie <[hidden email]>
+ */
+
+#include <config.h>
+
+/ {
+
+ aliases {
+ spi0 = "/soc@ffe000000/spi@110000";
+ i2c0 = "/soc@ffe000000/i2c@118000";
+ i2c1 = "/soc@ffe000000/i2c@118000/mux@70/i2c@0";
+ i2c2 = "/soc@ffe000000/i2c@118000/mux@70/i2c@1";
+ i2c3 = "/soc@ffe000000/i2c@118000/mux@70/i2c@7";
+ i2c4 = "/soc@ffe000000/i2c@118100";
+ /delete-property/ pci1;
+ /delete-property/ pci2;
+ /delete-property/ pci3;
+ };
+
+ chosen {
+ stdout-path = "/soc@ffe000000/serial@11c500";
+ };
+
+ soc@ffe000000 {
+ u-boot,dm-pre-reloc;
+ spi@110000 {
+ /* This documents where km_fpgacfg should be appear */
+ fpga@0 {
+ compatible = "keymile,fpga-conf";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ sdhc@114000 {
+ status = "okay";
+ };
+
+ i2c@118000 {
+ u-boot,dm-pre-reloc;
+ mux@70 {
+ i2c@1 { /* IVM bus */
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
+ serial@11c500 {
+ u-boot,dm-pre-reloc;
+ clock-frequency = <200000000>;
+ };
+
+ fman@400000 {
+ ethernet@e0000 {
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e2000 {
+ phy-connection-type = "sgmii";
+ };
+
+ ethernet@e8000 {
+ phy-connection-type = "rgmii-id";
+ };
+ };
+
+ };
+
+ pcie@ffe240000 {
+ compatible = "fsl,pcie-t104x";
+ law_trgt_if = <0>;
+ };
+
+ binman {
+ filename = "u-boot-with-dtb.bin";
+ skip-at-start = <CONFIG_SYS_TEXT_BASE>;
+ sort-by-offset;
+ pad-byte = <0xff>;
+ size = <CONFIG_SYS_MONITOR_LEN>;
+
+ u-boot-with-ucode-ptr {
+ offset = <CONFIG_SYS_TEXT_BASE>;
+ optional-ucode;
+ };
+
+ u-boot-dtb-with-ucode {
+ align = <256>;
+ };
+ powerpc-mpc85xx-bootpg-resetvec {
+ offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
+ };
+ };
+};
diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig
index e5906906f3..6b7377c200 100644
--- a/board/keymile/Kconfig
+++ b/board/keymile/Kconfig
@@ -114,6 +114,7 @@ config SYS_IVM_EEPROM_PAGE_LEN
   Page size of inventory in EEPROM.
 
 source "board/keymile/km83xx/Kconfig"
+source "board/keymile/kmcent2/Kconfig"
 source "board/keymile/kmp204x/Kconfig"
 source "board/keymile/km_arm/Kconfig"
 
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index 60b89fe348..608406dacd 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -321,6 +321,11 @@ static int ivm_populate_env(unsigned char *buf, int len, int mac_address_offset)
  process_mac(valbuf, page2, mac_address_offset, true);
  env_set((char *)"eth1addr", (char *)valbuf);
 #endif
+#if defined(CONFIG_TARGET_KMCENT2)
+/* 3rd ethernet interface */
+ process_mac(valbuf, page2, 2, true);
+ env_set((char *)"eth4addr", (char *)valbuf);
+#endif
 
  return 0;
 }
diff --git a/board/keymile/kmcent2/Kconfig b/board/keymile/kmcent2/Kconfig
new file mode 100644
index 0000000000..848d230fbd
--- /dev/null
+++ b/board/keymile/kmcent2/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_KMCENT2
+
+config SYS_BOARD
+ default "kmcent2"
+
+config SYS_VENDOR
+ default "keymile"
+
+config SYS_CONFIG_NAME
+ default "kmcent2"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_T1040
+ select PHYS_64BIT
+
+endif
diff --git a/board/keymile/kmcent2/MAINTAINERS b/board/keymile/kmcent2/MAINTAINERS
new file mode 100644
index 0000000000..1426475556
--- /dev/null
+++ b/board/keymile/kmcent2/MAINTAINERS
@@ -0,0 +1,8 @@
+KMCENT2 BOARD
+M: Niel Fourie <[hidden email]>
+S: Maintained
+F: board/keymile/kmcent2/
+F: include/configs/kmcent2.h
+F: configs/kmcent2_defconfig
+F: arch/powerpc/dts/kmcent2.dts
+F: arch/powerpc/dts/kmcent2-u-boot.dtsi
diff --git a/board/keymile/kmcent2/Makefile b/board/keymile/kmcent2/Makefile
new file mode 100644
index 0000000000..c1c951e014
--- /dev/null
+++ b/board/keymile/kmcent2/Makefile
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 Keymile AG
+# Rainer Boschung <[hidden email]>
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+
+obj-y += kmcent2.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += ../common/common.o
+obj-y += ../common/ivm.o
+obj-y += ../common/qrio.o
+
diff --git a/board/keymile/kmcent2/ddr.c b/board/keymile/kmcent2/ddr.c
new file mode 100644
index 0000000000..2b4e58795a
--- /dev/null
+++ b/board/keymile/kmcent2/ddr.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <[hidden email]>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
+#include <init.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DQSn_POS(n) (3 - (((n) - 1) % 4)) * 8
+#define DQSn_START(n, start) ((start) << DQSn_POS(n))
+void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
+   unsigned int ctrl_num)
+{
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+
+ /* 1/2 clk delay between wr command and data strobe */
+ popts->write_data_delay = 4;
+ /* clk lauched 1/2 applied cylcle after address command */
+ popts->clk_adjust = 4;
+ /* 1T timing: command/address held for only 1 cycle */
+ popts->twot_en = 0;
+ popts->threet_en = 0;
+
+ /* optimize cpo for erratum A-009942 */
+ popts->cpo_sample = 0x3b;
+
+ /* we have only one module, half str should be OK */
+ popts->half_strength_driver_enable = 1;
+ /*
+ * Write leveling override
+ */
+ /* set for DDR3-1600 */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x7;
+ /* DQS write leveling start time according layout */
+ popts->wrlvl_ctl_2 = (DQSn_START(1, 0x06) |
+      DQSn_START(2, 0x06) |
+      DQSn_START(3, 0x07) |
+      DQSn_START(4, 0x07));
+ popts->wrlvl_ctl_3 = (DQSn_START(5, 0x07) |
+      DQSn_START(6, 0x08) |
+      DQSn_START(7, 0x08) |
+      DQSn_START(8, 0x08));
+
+ /*
+ * rtt and wtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+int dram_init(void)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ gd->ram_size = dram_size;
+
+ return 0;
+}
diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
new file mode 100644
index 0000000000..3d6bd8328e
--- /dev/null
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <[hidden email]>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <hwconfig.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_fdt.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+#include <net.h>
+#include <image.h>
+#include <fdt_support.h>
+#include <vsc9953.h>
+
+#include "../common/common.h"
+#include "../common/qrio.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
+
+int checkboard(void)
+{
+ printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
+
+ return 0;
+}
+
+#define RSTRQSR1_WDT_RR 0x00200000
+#define RSTRQSR1_SW_RR 0x00100000
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ bool cpuwd_flag = false;
+
+ /* board specific IFC configuration: increased bus turnaround time */
+ setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ /* configure mode for uP reset request */
+ qrio_uprstreq(UPREQ_CORE_RST);
+
+ /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
+ setbits_be32(&gur->ddrclkdr, 0x40000000);
+
+ /* set reset reason according CPU register */
+ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
+    RSTRQSR1_WDT_RR)
+ cpuwd_flag = true;
+
+ qrio_cpuwd_flag(cpuwd_flag);
+ /* clear CPU bits by writing 1 */
+ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
+
+ /* configure PRST lines for the application. */
+ /* ETHSW_DDR_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_ETHSW_DDR_RST, true);
+ /* XES_PHY_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_XES_PHY_RST, true);
+ /* ES_PHY_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_ES_PHY_RST, true);
+ /* EFE_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_EFE_RST, true);
+ /* BFTIC4_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_BFTIC4_RST, true);
+ /* DPAXE_RST:
+ * reset at power-up and unit reset only and enable WD on it
+ */
+ qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_DPAXE_RST, true);
+ /* PEXSW_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_PEXSW_RST, false, false);
+ /* PEXSW_NT_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_PEXSW_NT_RST, false, false);
+ /* BOBCAT_RST:
+ * reset at power-up and unit reset only, deassert reset w/o WD
+ */
+ qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prst(KM_BOBCAT_RST, false, false);
+ /* FEMT_RST:
+ * reset at power-up and unit reset only and enable WD
+ */
+ qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_FEMT_RST, true);
+ /* FOAM_RST:
+ * reset at power-up and unit reset only and enable WD
+ */
+ qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_wdmask(KM_FOAM_RST, true);
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ int ret = 0;
+
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ int flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ if (flash_esel == -1) {
+ /* very unlikely unless something is messed up */
+ puts("Error: Could not find TLB for FLASH BASE\n");
+ flash_esel = 2; /* give our best effort to continue */
+ } else {
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+ }
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+ setup_qbman_portals();
+
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
+ return ret;
+}
+
+unsigned long get_serial_clock(unsigned long dummy)
+{
+ return (gd->bus_clk / 2);
+}
+
+unsigned long get_board_sys_clk(unsigned long dummy)
+{
+ return 66666666;
+}
+
+int misc_init_f(void)
+{
+ /* configure QRIO pis for i2c deblocking */
+ i2c_deblock_gpio_cfg();
+
+ /* CFE_RST (front phy):
+ * reset at power-up, unit and core reset, deasset reset w/o WD
+ */
+ qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(KM_CFE_RST, false, false);
+
+ /* ZL30158_RST (PTP clock generator):
+ * reset at power-up only, deassert reset and enable WD on it
+ */
+ qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
+ qrio_prst(KM_ZL30158_RST, false, false);
+
+ /* ZL30364_RST (EEC generator):
+ * reset at power-up only, deassert reset and enable WD on it
+ */
+ qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
+ qrio_prst(KM_ZL30364_RST, false, false);
+
+ return 0;
+}
+
+#define USED_SRDS_BANK 0
+#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
+
+#define BRG01_IOCLK12 0x02000000
+#define EC2_GTX_CLK125 0x08000000
+
+int misc_init_r(void)
+{
+ serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG;
+ ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* check SERDES bank 0 reference clock */
+ u32 actual = in_be32(&regs->bank[USED_SRDS_BANK].pllcr0);
+
+ if (actual & SRDS_PLLCR0_POFF)
+ printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
+ if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
+ printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
+       USED_SRDS_BANK,
+       serdes_clock_to_string(EXPECTED_SRDS_RFCK),
+       serdes_clock_to_string(actual));
+ }
+
+ /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
+ out_be32(&scfg->qeioclkcr,
+ in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
+
+ ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
+ CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
+
+ /* Fix polarity of Card Detect and Write Protect */
+ out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
+
+ /* EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
+ * to EC2
+ */
+ out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
+
+ return 0;
+}
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+ ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_LAST_STAGE_INIT)
+int last_stage_init(void)
+{
+ const char *kmem;
+ /* DIP switch support on BFTIC */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)SYS_BFTIC_BASE;
+ u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP:   Enabled\n");
+ env_set("actual_bank", "0");
+ }
+
+ set_km_env();
+
+ /* bootm_size is used to fixup the FDT memory node
+ * set it to kernelmem that has the same value
+ */
+ kmem = env_get("kernelmem");
+ if (kmem)
+ env_set("bootm_size", kmem);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_DPAA_FMAN)
+void fdt_fixup_fman_mac_addresses(void *blob)
+{
+ int node, ret;
+ char path[24];
+ unsigned char mac_addr[6];
+
+ /* just the fm1-mac5 must be set by us, u-boot handle the 2 others */
+ /* get the mac addr from env
+ */
+ if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
+ printf("eth4addr env variable not defined\n");
+ return;
+ }
+
+ /* local management port */
+ strcpy(path, "/soc/fman/ethernet@e8000");
+ node = fdt_path_offset(blob, path);
+ if (node < 0) {
+ printf("no %s\n", path);
+ return;
+ }
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("%s\n\terror setting local-mac-address property\n",
+       path);
+ }
+}
+#endif
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = env_get_bootm_low();
+ size = env_get_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ fdt_fixup_liodn(blob);
+
+#if defined(CONFIG_SYS_DPAA_FMAN)
+ fdt_fixup_fman_mac_addresses(blob);
+#endif
+
+ if (hwconfig("qe-tdm"))
+ fdt_del_diu(blob);
+ return 0;
+}
+
+#if defined(CONFIG_POST)
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT QRIO_GPIO_A
+#define SELFTEST_PIN 0
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
+
diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c
new file mode 100644
index 0000000000..44f704f698
--- /dev/null
+++ b/board/keymile/kmcent2/law.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <[hidden email]>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#if defined(CONFIG_SYS_DCSRBAR_PHYS)
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#if defined(CONFIG_SYS_FLASH_BASE_PHYS)
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
+#endif
+#if defined(CONFIG_SYS_NAND_BASE_PHYS)
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+#if defined(CONFIG_SYS_QRIO_BASE_PHYS)
+ SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+#if defined(SYS_LAWAPP_BASE_PHYS)
+ SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC),
+#endif
+
+/* other application LAW are not used in u-boot */
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
+
diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c
new file mode 100644
index 0000000000..8a726fbd17
--- /dev/null
+++ b/board/keymile/kmcent2/tlb.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <[hidden email]>
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+      0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+      0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+      0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+      0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+      MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
+      0, 2, BOOKE_PAGESZ_128M, 1),
+
+#if defined(CONFIG_PCIE1)
+ /* *I*G* - PCI1 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI1 I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+ /* Bman/Qman */
+#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+      0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+      0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+
+#if defined(CONFIG_SYS_DCSRBAR_PHYS)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#if defined(CONFIG_SYS_NAND_BASE)
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+ /* QRIO */
+#if defined(CONFIG_SYS_QRIO_BASE)
+ SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 11, BOOKE_PAGESZ_64K, 1),
+#endif
+ /* MRAM */
+#if defined(CONFIG_SYS_MRAM_BASE)
+ SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 12, BOOKE_PAGESZ_128M, 1),
+#endif
+ /* BFTIC */
+#if defined(SYS_BFTIC_BASE)
+ SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
+      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 13, BOOKE_PAGESZ_128M, 1),
+#endif
+ /* entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so do not use them here!!.
+ */
+ /* PAXE */
+#if defined(CONFIG_SYS_PAXE_BASE)
+ SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
+      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+      0, 16, BOOKE_PAGESZ_128M, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
new file mode 100644
index 0000000000..df206850fd
--- /dev/null
+++ b/configs/kmcent2_defconfig
@@ -0,0 +1,90 @@
+CONFIG_PPC=y
+CONFIG_SYS_TEXT_BASE=0xebf40000
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_KM_DEF_NETDEV="eth2"
+CONFIG_KM_IVM_BUS=2
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020
+CONFIG_DEFAULT_DEVICE_TREE="kmcent2"
+CONFIG_MPC85xx=y
+CONFIG_TARGET_KMCENT2=y
+CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND_TRIMFFS=y
+# CONFIG_CMD_SATA is not set
+CONFIG_CMD_SPI=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_ETHSW=y
+CONFIG_MP=y
+CONFIG_CMD_CRAMFS=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_ADDR=0xebf20000
+CONFIG_ENV_ADDR_REDUND=0xebf00000
+CONFIG_DM=y
+# CONFIG_FSL_SATA is not set
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_FSL_CAAM=y
+CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_10G=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_PHY_GIGE=y
+CONFIG_FMAN_ENET=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_FSL=y
+CONFIG_U_QE=y
+CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_FSL_ESPI=y
+CONFIG_WATCHDOG=y
+CONFIG_FS_CRAMFS=y
+CONFIG_BCH=y
+CONFIG_PANIC_HANG=y
+CONFIG_LZO=y
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
new file mode 100644
index 0000000000..a0f3a09057
--- /dev/null
+++ b/include/configs/kmcent2.h
@@ -0,0 +1,537 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung <[hidden email]>
+ *
+ */
+
+#ifndef __KMCENT2_H
+#define __KMCENT2_H
+
+#define CONFIG_HOSTNAME "kmcent2"
+#define KM_BOARD_NAME CONFIG_HOSTNAME
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=ffa000000.flash"
+
+#define MTDPARTS_DEFAULT "mtdparts=" \
+ "fe8000000.nor:" \
+ "128k(RCW)," \
+ "128k(fman)," \
+ "128k(QE)," \
+ "128k(zarlink)," \
+ "512k(res)," \
+ "62m(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")," \
+ "128k(envred)," \
+ "128k(env)," \
+ "768k(u-boot);" \
+ "ffa000000.flash:" \
+ "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
+
+/*
+ * The Linux fsl_fman driver needs to be able to process frames with more
+ * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot
+ * parameters
+ */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558"
+
+#include "km/keymile-common.h"
+
+/* Application IFC chip selects */
+#define SYS_LAWAPP_BASE 0xc0000000
+#define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE)
+
+/* Application IFC CS4 MRAM */
+#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE
+#define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS
+#define SYS_MRAM_CSPR_EXT (0x0f)
+#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \
+ CSPR_PORT_SIZE_8 | /* 8 bit */ \
+ CSPR_MSEL_GPCM   | /* msel = gpcm */ \
+ CSPR_V /* bank is valid */)
+#define SYS_MRAM_AMASK IFC_AMASK(2 * 1024 * 1024) /* 2 MiB */
+#define SYS_MRAM_CSOR CSOR_GPCM_TRHZ_40
+/* MRAM Timing parameters for IFC CS4 */
+#define SYS_MRAM_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8)  | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_MRAM_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0xe))
+#define SYS_MRAM_FTIM2 (FTIM2_GPCM_TCS(0x2) | \
+ FTIM2_GPCM_TCH(0x2)  | \
+ FTIM2_GPCM_TWP(0x8))
+#define SYS_MRAM_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT
+#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR
+#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK
+#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR
+#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0
+#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1
+#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2
+#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3
+
+/* Application IFC CS6: BFTIC */
+#define SYS_BFTIC_BASE 0xd0000000
+#define SYS_BFTIC_BASE_PHYS (0xf00000000ull | SYS_BFTIC_BASE)
+#define SYS_BFTIC_CSPR_EXT (0x0f)
+#define SYS_BFTIC_CSPR (CSPR_PHYS_ADDR(SYS_BFTIC_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
+ CSPR_V)            /* valid */
+#define SYS_BFTIC_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
+#define SYS_BFTIC_CSOR  CSOR_GPCM_TRHZ_40
+/* BFTIC Timing parameters for IFC CS6 */
+#define SYS_BFTIC_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_BFTIC_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_BFTIC_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_BFTIC_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT
+#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR
+#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK
+#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR
+#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0
+#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1
+#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2
+#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3
+
+/* Application IFC CS7 PAXE */
+#define CONFIG_SYS_PAXE_BASE 0xd8000000
+#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE)
+#define SYS_PAXE_CSPR_EXT (0x0f)
+#define SYS_PAXE_CSPR  (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
+ CSPR_V)            /* valid */
+#define SYS_PAXE_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
+#define SYS_PAXE_CSOR  CSOR_GPCM_TRHZ_40
+/* PAXE Timing parameters for IFC CS7 */
+#define SYS_PAXE_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_PAXE_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x12))
+#define SYS_PAXE_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x12))
+#define SYS_PAXE_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT
+#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR
+#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK
+#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR
+#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0
+#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1
+#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2
+#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3
+
+/* PRST */
+#define KM_BFTIC4_RST 0
+#define KM_DPAXE_RST 1
+#define KM_FEMT_RST 3
+#define KM_FOAM_RST 4
+#define KM_EFE_RST 5
+#define KM_ES_PHY_RST 6
+#define KM_XES_PHY_RST 7
+#define KM_ZL30158_RST 8
+#define KM_ZL30364_RST 9
+#define KM_BOBCAT_RST 10
+#define KM_ETHSW_DDR_RST 12
+#define KM_CFE_RST 13
+#define KM_PEXSW_RST 14
+#define KM_PEXSW_NT_RST 15
+
+/* QRIO GPIOs used for deblocking */
+#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
+#define KM_I2C_DEBLOCK_SCL 20
+#define KM_I2C_DEBLOCK_SDA 21
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+
+#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1 /* PCIE controller 1 */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+/* Environment in parallel NOR-Flash */
+#define CONFIG_ENV_TOTAL_SIZE 0x040000
+#define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
+#define CONFIG_BTB /* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+/* POST memory regions test */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
+#define CONFIG_SYS_L3_SIZE 256 << 10
+
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DDR_CLK_FREQ 66666666
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_IVM_EEPROM_ADR
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE 0x0
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM
+ */
+#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR flash on IFC CS0 */
+#define CONFIG_SYS_FLASH_BASE 0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \
+ CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\
+ 0x00000010 |    /* drive TE high */\
+ CSPR_MSEL_NOR |    /* MSEL = NOR */\
+ CSPR_V)    /* valid */
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD toggle */\
+ CSOR_NOR_TRHZ_20 | \
+ CSOR_NOR_BCTLD)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
+ FTIM0_NOR_TEADC(0x7) | \
+ FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
+ FTIM1_NOR_TRAD_NOR(0x21) | \
+ FTIM1_NOR_TSEQRAD_NOR(0x21))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCH(0x1) | \
+ FTIM2_NOR_TCS(0x1) | \
+ FTIM2_NOR_TWP(0xb) | \
+ FTIM2_NOR_TWPH(0x6))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+/* More NOR Flash params */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC CS1*/
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xfa000000
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0x0f)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\
+ 0x00000010 |   /* drive TE high */\
+ CSPR_MSEL_NAND |   /* MSEL = NAND */\
+ CSPR_V)   /* valid */
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \
+ CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */   \
+ CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */        \
+ CSOR_NAND_RAL_3      | /* RAL = 3Bytes */     \
+ CSOR_NAND_PGS_2K     | /* Page size = 2K */   \
+ CSOR_NAND_SPRZ_128   | /* Spare size = 128 */ \
+ CSOR_NAND_PB(64)     | /* 64 Pages/Block */   \
+ CSOR_NAND_TRHZ_40    | /**/                   \
+ CSOR_NAND_BCTLD)       /**/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \
+ FTIM0_NAND_TWP(0x8) | \
+ FTIM0_NAND_TWCHT(0x3) | \
+ FTIM0_NAND_TWH(0x5))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \
+ FTIM1_NAND_TWBE(0x1e) | \
+ FTIM1_NAND_TRR(0x6) | \
+ FTIM1_NAND_TRP(0x8))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \
+ FTIM2_NAND_TREH(0x5) | \
+ FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e))
+
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+/* More NAND Flash Params */
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+/* QRIO on IFC CS2 */
+#define CONFIG_SYS_QRIO_BASE 0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE)
+#define SYS_QRIO_CSPR_EXT (0x0f)
+#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \
+ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\
+ 0x00000010 |   /* drive TE high */\
+ CSPR_MSEL_GPCM |   /* MSEL = GPCM */\
+ CSPR_V)           /* valid */
+#define SYS_QRIO_AMASK IFC_AMASK(64 * 1024)  /* 64kB */
+#define SYS_QRIO_CSOR (CSOR_GPCM_TRHZ_20 |\
+ CSOR_GPCM_BCTLD)
+/* QRIO Timing parameters for IFC CS2 */
+#define SYS_QRIO_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \
+ FTIM0_GPCM_TEADC(0x8) | \
+ FTIM0_GPCM_TEAHC(0x2))
+#define SYS_QRIO_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
+ FTIM1_GPCM_TRAD(0x6))
+#define SYS_QRIO_FTIM2 (FTIM2_GPCM_TCS(0x1) | \
+ FTIM2_GPCM_TCH(0x1) | \
+ FTIM2_GPCM_TWP(0x7))
+#define SYS_QRIO_FTIM3 0x04000000
+#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT
+#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR
+#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK
+#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR
+#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3
+
+#define CONFIG_MISC_INIT_F
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_LEN 0xc0000         /* 768k */
+
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/*
+ * Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ * Retain non-DM serial port for debug purposes.
+ */
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
+#endif
+
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1 */
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#endif
+
+#define CONFIG_SYS_BMAN_NUM_PORTALS 10
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+ CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS 10
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+ CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#define CONFIG_SYS_FMAN_FW_ADDR 0xE8020000
+#define CONFIG_SYS_QE_FW_ADDR 0xE8040000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+/* Qman / Bman */
+/* RGMII (FM1@DTESC5) is local managemant interface */
+#define CONFIG_SYS_RGMII2_PHY_ADDR             0x11
+#define CONFIG_ETHPRIME "fm1-mac5"
+
+/*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */
+#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV
+#endif
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_KM_DEF_ENV_CPU \
+ "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
+ "cramfsloadfdt=" \
+ "cramfsload ${fdt_addr_r} " \
+ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
+ "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize}\0" \
+ "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize} && " \
+ "cp.b ${load_addr_r} " \
+ __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \
+ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \
+ "set_fdthigh=true\0" \
+ "checkfdt=true\0" \
+ "fpgacfg=true\0" \
+ ""
+
+#define CONFIG_HW_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
+ "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+ "usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV \
+ "newenv=protect off " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "erase " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \
+ "protect on " __stringify(ENV_DEL_ADDR) \
+ " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_KM_DEF_ENV \
+ CONFIG_KM_DEF_ARCH \
+ CONFIG_KM_NEW_ENV \
+ CONFIG_HW_ENV_SETTINGS \
+ "EEprom_ivm=pca9547:70:9\0" \
+ ""
+
+#endif /* __KMCENT2_H */
--
2.29.2